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author | Antonio Nino Diaz <antonio.ninodiaz@arm.com> | 2018-09-24 17:15:54 +0100 |
---|---|---|
committer | Antonio Nino Diaz <antonio.ninodiaz@arm.com> | 2018-09-28 15:34:17 +0100 |
commit | b8424642bcbe38433eea0c332aaedadd78fd45d4 (patch) | |
tree | e9671d3f8af692b01acd1a8a641ac1c9aa997f4a /plat/mediatek/mt6795 | |
parent | 35795b4e878467300b3bdccc37d7486a9c8942c6 (diff) | |
download | platform_external_arm-trusted-firmware-b8424642bcbe38433eea0c332aaedadd78fd45d4.tar.gz platform_external_arm-trusted-firmware-b8424642bcbe38433eea0c332aaedadd78fd45d4.tar.bz2 platform_external_arm-trusted-firmware-b8424642bcbe38433eea0c332aaedadd78fd45d4.zip |
mediatek: Migrate to new interfaces
- mt6795: Migrate to new GIC interfaces.
- Remove support for PSCI platform compatibility layer.
- Migrate to bl31_early_platform_setup2().
- Migrate from cm_init_context() to cm_init_my_context().
- Use PLAT_VIRT_ADDR_SPACE_SIZE and PLAT_PHY_ADDR_SPACE_SIZE.
- Update Makefile paths.
- Use private definition of bl31_params_t.
This is an incomplete migration, mt6795 doesn't currently compile.
Change-Id: Icf9307637066cd6f2166524715e4f117f5ce2350
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
Diffstat (limited to 'plat/mediatek/mt6795')
-rw-r--r-- | plat/mediatek/mt6795/bl31_plat_setup.c | 14 | ||||
-rw-r--r-- | plat/mediatek/mt6795/include/plat_macros.S | 1 | ||||
-rw-r--r-- | plat/mediatek/mt6795/include/platform_def.h | 18 | ||||
-rw-r--r-- | plat/mediatek/mt6795/plat_mt_gic.c | 13 | ||||
-rw-r--r-- | plat/mediatek/mt6795/plat_pm.c | 1 | ||||
-rw-r--r-- | plat/mediatek/mt6795/platform.mk | 10 |
6 files changed, 21 insertions, 36 deletions
diff --git a/plat/mediatek/mt6795/bl31_plat_setup.c b/plat/mediatek/mt6795/bl31_plat_setup.c index 32f015721..d9577a6fc 100644 --- a/plat/mediatek/mt6795/bl31_plat_setup.c +++ b/plat/mediatek/mt6795/bl31_plat_setup.c @@ -4,7 +4,6 @@ * SPDX-License-Identifier: BSD-3-Clause */ #include <arch_helpers.h> -#include <arm_gic.h> #include <assert.h> #include <bl_common.h> #include <cci.h> @@ -172,16 +171,15 @@ entry_point_info_t *bl31_plat_get_next_image_ep_info(uint32_t type) * BL2 has flushed this information to memory, so we are guaranteed to pick up * good data. ******************************************************************************/ -void bl31_early_platform_setup(bl31_params_t *from_bl2, - void *plat_params_from_bl2) +void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1, + u_register_t arg2, u_register_t arg3) { - struct mtk_bl_param_t *pmtk_bl_param = - (struct mtk_bl_param_t *)from_bl2; + struct mtk_bl_param_t *pmtk_bl_param = (struct mtk_bl_param_t *)arg0; struct atf_arg_t *teearg; unsigned long long normal_base; unsigned long long atf_base; - assert(from_bl2 != NULL); + assert(pmtk_bl_param != NULL); /* * Mediatek preloader(i.e, BL2) is in 32 bit state, high 32bits * of 64 bit GP registers are UNKNOWN if CPU warm reset from 32 bit @@ -190,8 +188,6 @@ void bl31_early_platform_setup(bl31_params_t *from_bl2, */ pmtk_bl_param = (struct mtk_bl_param_t *)((uint64_t)pmtk_bl_param & 0x00000000ffffffff); - plat_params_from_bl2 = - (void *)((uint64_t)plat_params_from_bl2 & 0x00000000ffffffff); teearg = (struct atf_arg_t *)pmtk_bl_param->tee_info_addr; @@ -445,6 +441,6 @@ void bl31_prepare_kernel_entry(uint64_t k32_64) INFO("BL3-1: Next image address = 0x%llx\n", (unsigned long long) next_image_info->pc); INFO("BL3-1: Next image spsr = 0x%x\n", next_image_info->spsr); - cm_init_context(read_mpidr_el1(), next_image_info); + cm_init_my_context(next_image_info); cm_prepare_el3_exit(image_type); } diff --git a/plat/mediatek/mt6795/include/plat_macros.S b/plat/mediatek/mt6795/include/plat_macros.S index 48bf28f9c..7485647f3 100644 --- a/plat/mediatek/mt6795/include/plat_macros.S +++ b/plat/mediatek/mt6795/include/plat_macros.S @@ -5,7 +5,6 @@ */ #include <cci.h> -#include <gic_v2.h> #include <platform_def.h> .section .rodata.gic_reg_name, "aS" diff --git a/plat/mediatek/mt6795/include/platform_def.h b/plat/mediatek/mt6795/include/platform_def.h index 0fa63a1a6..0110e192d 100644 --- a/plat/mediatek/mt6795/include/platform_def.h +++ b/plat/mediatek/mt6795/include/platform_def.h @@ -117,10 +117,6 @@ #define FIQ_SMP_CALL_SGI MT_IRQ_SEC_SGI_5 -#define PLAT_ARM_G0_IRQS FIQ_SMP_CALL_SGI - -#define DEBUG_XLAT_TABLE 0 - /******************************************************************************* * Platform binary types for linking ******************************************************************************/ @@ -132,9 +128,7 @@ ******************************************************************************/ /* Size of cacheable stacks */ -#if DEBUG_XLAT_TABLE -#define PLATFORM_STACK_SIZE 0x800 -#elif defined(IMAGE_BL1) +#if defined(IMAGE_BL1) #define PLATFORM_STACK_SIZE 0x440 #elif defined(IMAGE_BL2) #define PLATFORM_STACK_SIZE 0x400 @@ -145,11 +139,10 @@ #endif #define FIRMWARE_WELCOME_STR "Booting Trusted Firmware\n" -#if ENABLE_PLAT_COMPAT -#define PLATFORM_MAX_AFFLVL MPIDR_AFFLVL2 -#else #define PLAT_MAX_PWR_LVL U(2) /* MPIDR_AFFLVL2 */ -#endif + +#define PLAT_MAX_RET_STATE U(1) +#define PLAT_MAX_OFF_STATE U(2) #define PLATFORM_CACHE_LINE_SIZE 64 #define PLATFORM_SYSTEM_COUNT 1 @@ -198,7 +191,8 @@ /******************************************************************************* * Platform specific page table and MMU setup constants ******************************************************************************/ -#define ADDR_SPACE_SIZE (1ULL << 32) +#define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 32) +#define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 32) #define MAX_XLAT_TABLES 7 #define MAX_MMAP_REGIONS 16 diff --git a/plat/mediatek/mt6795/plat_mt_gic.c b/plat/mediatek/mt6795/plat_mt_gic.c index 47a23dfe1..11282fc54 100644 --- a/plat/mediatek/mt6795/plat_mt_gic.c +++ b/plat/mediatek/mt6795/plat_mt_gic.c @@ -1,23 +1,24 @@ /* - * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2016-2018, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ #include <gicv2.h> -#include <plat_arm.h> +#include <interrupt_props.h> #include <platform.h> #include <platform_def.h> -const unsigned int g0_interrupt_array[] = { - PLAT_ARM_G0_IRQS +static const interrupt_prop_t g0_interrupt_props[] = { + INTR_PROP_DESC(FIQ_SMP_CALL_SGI, GIC_HIGHEST_SEC_PRIORITY, + GICV2_INTR_GROUP0, GIC_INTR_CFG_LEVEL), }; gicv2_driver_data_t arm_gic_data = { .gicd_base = BASE_GICD_BASE, .gicc_base = BASE_GICC_BASE, - .g0_interrupt_num = ARRAY_SIZE(g0_interrupt_array), - .g0_interrupt_array = g0_interrupt_array, + .interrupt_props = g0_interrupt_props, + .interrupt_props_num = ARRAY_SIZE(g0_interrupt_props), }; void plat_mt_gic_driver_init(void) diff --git a/plat/mediatek/mt6795/plat_pm.c b/plat/mediatek/mt6795/plat_pm.c index bd47bd8b1..d0506645f 100644 --- a/plat/mediatek/mt6795/plat_pm.c +++ b/plat/mediatek/mt6795/plat_pm.c @@ -5,7 +5,6 @@ */ #include <arch_helpers.h> -#include <arm_gic.h> #include <assert.h> #include <bakery_lock.h> #include <cci.h> diff --git a/plat/mediatek/mt6795/platform.mk b/plat/mediatek/mt6795/platform.mk index 1bdf30af3..c2fd511e6 100644 --- a/plat/mediatek/mt6795/platform.mk +++ b/plat/mediatek/mt6795/platform.mk @@ -26,7 +26,8 @@ PLAT_INCLUDES := -I${MTK_PLAT}/common/ \ -Iinclude/common/tbbr/ \ ${OEMS_INCLUDES} -PLAT_BL_COMMON_SOURCES := lib/aarch64/xlat_tables.c \ +PLAT_BL_COMMON_SOURCES := lib/xlat_tables/aarch64/xlat_tables.c \ + lib/xlat_tables/xlat_tables_common.c \ plat/common/plat_gic.c BL31_SOURCES += drivers/arm/cci/cci.c \ @@ -35,7 +36,7 @@ BL31_SOURCES += drivers/arm/cci/cci.c \ drivers/arm/gic/v2/gicv2_main.c \ drivers/arm/gic/v2/gicv2_helpers.c \ plat/common/plat_gicv2.c \ - drivers/console/console.S \ + drivers/console/aarch64/console.S \ drivers/delay_timer/delay_timer.c \ lib/cpus/aarch64/cortex_a53.S \ ${MTK_PLAT_SOC}/bl31_plat_setup.c \ @@ -52,11 +53,6 @@ BL31_SOURCES += drivers/arm/cci/cci.c \ ${MTK_PLAT_SOC}/scu.c \ ${OEMS_SOURCES} -# Flag used by the MTK_platform port to determine the version of ARM GIC -# architecture to use for interrupt management in EL3. -ARM_GIC_ARCH := 2 -$(eval $(call add_define,ARM_GIC_ARCH)) - # Enable workarounds for selected Cortex-A53 erratas. ERRATA_A53_826319 := 1 ERRATA_A53_836870 := 1 |