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| author | Sandrine Bailleux <sandrine.bailleux@arm.com> | 2020-02-12 15:54:02 +0000 |
|---|---|---|
| committer | TrustedFirmware Code Review <review@review.trustedfirmware.org> | 2020-02-12 15:54:02 +0000 |
| commit | 78fcbd65be86dbef25512d9a8bcb1ece3989d27b (patch) | |
| tree | 621f95206c9d5375c477a88834277e705950f776 /plat/intel | |
| parent | c83d66ec63484fdd7905fabcf48fe04f9ebf5feb (diff) | |
| parent | 77fc46971eb7d83ac66071aca7c684e626e8a2f1 (diff) | |
| download | platform_external_arm-trusted-firmware-78fcbd65be86dbef25512d9a8bcb1ece3989d27b.tar.gz platform_external_arm-trusted-firmware-78fcbd65be86dbef25512d9a8bcb1ece3989d27b.tar.bz2 platform_external_arm-trusted-firmware-78fcbd65be86dbef25512d9a8bcb1ece3989d27b.zip | |
Merge "intel: Change boot source selection" into integration
Diffstat (limited to 'plat/intel')
| -rw-r--r-- | plat/intel/soc/agilex/bl2_plat_setup.c | 3 | ||||
| -rw-r--r-- | plat/intel/soc/agilex/include/socfpga_plat_def.h | 1 | ||||
| -rw-r--r-- | plat/intel/soc/common/include/socfpga_handoff.h | 1 | ||||
| -rw-r--r-- | plat/intel/soc/stratix10/bl2_plat_setup.c | 3 | ||||
| -rw-r--r-- | plat/intel/soc/stratix10/include/socfpga_plat_def.h | 3 |
5 files changed, 5 insertions, 6 deletions
diff --git a/plat/intel/soc/agilex/bl2_plat_setup.c b/plat/intel/soc/agilex/bl2_plat_setup.c index 9587d4859..f32820777 100644 --- a/plat/intel/soc/agilex/bl2_plat_setup.c +++ b/plat/intel/soc/agilex/bl2_plat_setup.c @@ -46,7 +46,7 @@ const mmap_region_t agilex_plat_mmap[] = { {0}, }; -boot_source_type boot_source; +boot_source_type boot_source = BOOT_SOURCE; void bl2_el3_early_platform_setup(u_register_t x0, u_register_t x1, u_register_t x2, u_register_t x4) @@ -59,7 +59,6 @@ void bl2_el3_early_platform_setup(u_register_t x0, u_register_t x1, if (socfpga_get_handoff(&reverse_handoff_ptr)) return; config_pinmux(&reverse_handoff_ptr); - boot_source = reverse_handoff_ptr.boot_source; config_clkmgr_handoff(&reverse_handoff_ptr); enable_nonsecure_access(); diff --git a/plat/intel/soc/agilex/include/socfpga_plat_def.h b/plat/intel/soc/agilex/include/socfpga_plat_def.h index b4e09210f..6c9d81ceb 100644 --- a/plat/intel/soc/agilex/include/socfpga_plat_def.h +++ b/plat/intel/soc/agilex/include/socfpga_plat_def.h @@ -12,6 +12,7 @@ /* Platform Setting */ #define PLATFORM_MODEL PLAT_SOCFPGA_AGILEX +#define BOOT_SOURCE BOOT_SOURCE_SDMMC /* Register Mapping */ #define SOCFPGA_MMC_REG_BASE 0xff808000 diff --git a/plat/intel/soc/common/include/socfpga_handoff.h b/plat/intel/soc/common/include/socfpga_handoff.h index 889d13767..ba0f7f377 100644 --- a/plat/intel/soc/common/include/socfpga_handoff.h +++ b/plat/intel/soc/common/include/socfpga_handoff.h @@ -125,7 +125,6 @@ typedef struct handoff_t { uint32_t misc_magic; uint32_t misc_length; uint32_t _pad_0x618_0x620[2]; - uint32_t boot_source; } handoff; int verify_handoff_image(handoff *hoff_ptr, handoff *reverse_hoff_ptr); diff --git a/plat/intel/soc/stratix10/bl2_plat_setup.c b/plat/intel/soc/stratix10/bl2_plat_setup.c index 7d183db0d..78ca253e7 100644 --- a/plat/intel/soc/stratix10/bl2_plat_setup.c +++ b/plat/intel/soc/stratix10/bl2_plat_setup.c @@ -45,7 +45,7 @@ const mmap_region_t plat_stratix10_mmap[] = { {0}, }; -boot_source_type boot_source; +boot_source_type boot_source = BOOT_SOURCE; void bl2_el3_early_platform_setup(u_register_t x0, u_register_t x1, u_register_t x2, u_register_t x4) @@ -58,7 +58,6 @@ void bl2_el3_early_platform_setup(u_register_t x0, u_register_t x1, if (socfpga_get_handoff(&reverse_handoff_ptr)) return; config_pinmux(&reverse_handoff_ptr); - boot_source = reverse_handoff_ptr.boot_source; config_clkmgr_handoff(&reverse_handoff_ptr); enable_nonsecure_access(); diff --git a/plat/intel/soc/stratix10/include/socfpga_plat_def.h b/plat/intel/soc/stratix10/include/socfpga_plat_def.h index 9dc51514c..a2bd57b08 100644 --- a/plat/intel/soc/stratix10/include/socfpga_plat_def.h +++ b/plat/intel/soc/stratix10/include/socfpga_plat_def.h @@ -10,7 +10,8 @@ #include <platform_def.h> /* Platform Setting */ -#define PLATFORM_MODEL PLAT_SOCFPGA_STRATIX10 +#define PLATFORM_MODEL PLAT_SOCFPGA_STRATIX10 +#define BOOT_SOURCE BOOT_SOURCE_SDMMC /* Register Mapping */ #define SOCFPGA_MMC_REG_BASE 0xff808000 |