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| author | Leo Yan <leo.yan@linaro.org> | 2017-08-29 14:38:06 +0800 |
|---|---|---|
| committer | Leo Yan <leo.yan@linaro.org> | 2017-08-29 14:38:06 +0800 |
| commit | 3506ff110c703db6a1b27d716dd46c318e4f37d6 (patch) | |
| tree | 9dc9eed0d80b1057fae4bb768e4f6809c130e843 /plat/hisilicon | |
| parent | f91e8d1af6bbe64747de138f5afdabbd901e17d5 (diff) | |
| download | platform_external_arm-trusted-firmware-3506ff110c703db6a1b27d716dd46c318e4f37d6.tar.gz platform_external_arm-trusted-firmware-3506ff110c703db6a1b27d716dd46c318e4f37d6.tar.bz2 platform_external_arm-trusted-firmware-3506ff110c703db6a1b27d716dd46c318e4f37d6.zip | |
Hikey: enable watchdog reset
At the system boot time we need enable watchdog reset, otherwise after
the watchdog is timeout it cannot reset the SoC. We need set the bit 0
and bit 16 together, the bit 16 is mask bit so after set bit 16 we have
permission to operate bit 0 and bit 0 is watchdog reset enabling bit.
Signed-off-by: Leo Yan <leo.yan@linaro.org>
Diffstat (limited to 'plat/hisilicon')
| -rw-r--r-- | plat/hisilicon/hikey/hisi_pwrc.c | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/plat/hisilicon/hikey/hisi_pwrc.c b/plat/hisilicon/hikey/hisi_pwrc.c index ade408d44..8e9d1fc44 100644 --- a/plat/hisilicon/hikey/hisi_pwrc.c +++ b/plat/hisilicon/hikey/hisi_pwrc.c @@ -75,8 +75,13 @@ int hisi_pwrc_setup(void) pm_asm_code_end - pm_asm_code); reg = mmio_read_32(AO_SC_SYS_CTRL1); + /* Remap SRAM address for ACPU */ reg |= AO_SC_SYS_CTRL1_REMAP_SRAM_AARM | AO_SC_SYS_CTRL1_REMAP_SRAM_AARM_MSK; + + /* Enable reset signal for watchdog */ + reg |= AO_SC_SYS_CTRL1_AARM_WD_RST_CFG | + AO_SC_SYS_CTRL1_AARM_WD_RST_CFG_MSK; mmio_write_32(AO_SC_SYS_CTRL1, reg); return 0; |