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| author | Alistair Delva <adelva@google.com> | 2021-02-16 21:01:22 +0000 |
|---|---|---|
| committer | Automerger Merge Worker <android-build-automerger-merge-worker@system.gserviceaccount.com> | 2021-02-16 21:01:22 +0000 |
| commit | efb2826bb8160e2d8e0fcec85133a7468484f9fd (patch) | |
| tree | 37a21c69306801ee7cdda5167a30896c8740155b /plat/brcm/board/stingray/include/swreg.h | |
| parent | b00a71fc312c9781fa6f404dccfb55b062b2ccac (diff) | |
| parent | faa476c0caaa598afa5a6109d17102db5fe35ec6 (diff) | |
| download | platform_external_arm-trusted-firmware-master.tar.gz platform_external_arm-trusted-firmware-master.tar.bz2 platform_external_arm-trusted-firmware-master.zip | |
Merge branch 'aosp/upstream-master' into HEAD am: faa476c0caHEADandroid-s-beta-5android-s-beta-4android-s-beta-3android-s-beta-2android-s-beta-1mastermain-cg-testing-releaseandroid-s-beta-5android-s-beta-4
Original change: https://android-review.googlesource.com/c/platform/external/arm-trusted-firmware/+/1589611
MUST ONLY BE SUBMITTED BY AUTOMERGER
Change-Id: I3a25534ceed4f8e188510641080d8b8ed49b8f62
Diffstat (limited to 'plat/brcm/board/stingray/include/swreg.h')
| -rw-r--r-- | plat/brcm/board/stingray/include/swreg.h | 36 |
1 files changed, 36 insertions, 0 deletions
diff --git a/plat/brcm/board/stingray/include/swreg.h b/plat/brcm/board/stingray/include/swreg.h new file mode 100644 index 000000000..6e971ce34 --- /dev/null +++ b/plat/brcm/board/stingray/include/swreg.h @@ -0,0 +1,36 @@ +/* + * Copyright (c) 2017 - 2020, Broadcom + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef SWREG_H +#define SWREG_H + +/* default voltage if no valid OTP */ +#define VDDC_CORE_DEF_VOLT 910000 /* 0.91v */ +#define IHOST_DEF_VOLT 940000 /* 0.94v */ + +#define B0_VDDC_CORE_DEF_VOLT 950000 /* 0.95v */ +#define B0_IHOST_DEF_VOLT 950000 /* 0.95v */ +#define B0_DDR_VDDC_DEF_VOLT 1000000 /* 1v */ + +#define SWREG_IHOST1_DIS 4 +#define SWREG_IHOST1_REG_RESETB 5 +#define SWREG_IHOST1_PMU_STABLE 2 + +enum sw_reg { + DDR_VDDC = 1, + IHOST03, + IHOST12, + IHOST_ARRAY, + DDRIO_SLAVE, + VDDC_CORE, + VDDC1, + DDRIO_MASTER +}; + +int set_swreg(enum sw_reg reg_id, uint32_t micro_volts); +int swreg_firmware_update(void); + +#endif |