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| author | Oliver Swede <oli.swede@arm.com> | 2020-01-15 10:20:09 +0000 |
|---|---|---|
| committer | Oliver Swede <oli.swede@arm.com> | 2020-03-26 20:41:59 +0000 |
| commit | 4b5793c9a873f84f27eb560b453f999eb8437755 (patch) | |
| tree | 592d667d7e6a412105ba2af3596a8d6b628b2e5b /plat/arm | |
| parent | 62056e4e8f9dcd298b441454b372c0720ed2abc1 (diff) | |
| download | platform_external_arm-trusted-firmware-4b5793c9a873f84f27eb560b453f999eb8437755.tar.gz platform_external_arm-trusted-firmware-4b5793c9a873f84f27eb560b453f999eb8437755.tar.bz2 platform_external_arm-trusted-firmware-4b5793c9a873f84f27eb560b453f999eb8437755.zip | |
plat/arm/board/arm_fpga: Compile with additional CPU libraries
This change is part of the goal of enabling the port to be compatible
with multiple FPGA images.
BL31 behaves differently depending on whether or not the CPUs in the
system use cache coherency, and as a result any CPU libraries that are
compiled together must serve processors that are consistent in this
regard.
This compiles a different set of CPU libraries depending on whether or
not the HW_ASSISTED_COHERENCY is enabled at build-time to indicate the
CPUs support hardware-level support for cache coherency. This build
flag is used in the makefile in the same way as the Arm FVP port.
Signed-off-by: Oliver Swede <oli.swede@arm.com>
Change-Id: I18300b4443176b89767015e3688c0f315a91c27e
Diffstat (limited to 'plat/arm')
| -rw-r--r-- | plat/arm/board/arm_fpga/platform.mk | 31 |
1 files changed, 28 insertions, 3 deletions
diff --git a/plat/arm/board/arm_fpga/platform.mk b/plat/arm/board/arm_fpga/platform.mk index 194c59551..b4f38fab4 100644 --- a/plat/arm/board/arm_fpga/platform.mk +++ b/plat/arm/board/arm_fpga/platform.mk @@ -35,11 +35,36 @@ endif # Treating this as a memory-constrained port for now USE_COHERENT_MEM := 0 -# The CPU in the initial image makes use of this feature +# This can be overridden depending on CPU(s) used in the FPGA image HW_ASSISTED_COHERENCY := 1 -FPGA_CPU_LIBS := lib/cpus/${ARCH}/aem_generic.S \ - lib/cpus/aarch64/neoverse_zeus.S +FPGA_CPU_LIBS := lib/cpus/${ARCH}/aem_generic.S + +# select a different set of CPU files, depending on whether we compile for +# hardware assisted coherency cores or not +ifeq (${HW_ASSISTED_COHERENCY}, 0) +# Cores used without DSU + FPGA_CPU_LIBS += lib/cpus/aarch64/cortex_a35.S \ + lib/cpus/aarch64/cortex_a53.S \ + lib/cpus/aarch64/cortex_a57.S \ + lib/cpus/aarch64/cortex_a72.S \ + lib/cpus/aarch64/cortex_a73.S +else +# AArch64-only cores + FPGA_CPU_LIBS += lib/cpus/aarch64/cortex_a76.S \ + lib/cpus/aarch64/cortex_a76ae.S \ + lib/cpus/aarch64/cortex_a77.S \ + lib/cpus/aarch64/neoverse_n1.S \ + lib/cpus/aarch64/neoverse_e1.S \ + lib/cpus/aarch64/neoverse_zeus.S \ + lib/cpus/aarch64/cortex_hercules.S \ + lib/cpus/aarch64/cortex_hercules_ae.S \ + lib/cpus/aarch64/cortex_a65.S \ + lib/cpus/aarch64/cortex_a65ae.S +# AArch64/AArch32 cores + FPGA_CPU_LIBS += lib/cpus/aarch64/cortex_a55.S \ + lib/cpus/aarch64/cortex_a75.S +endif FPGA_GIC_SOURCES := drivers/arm/gic/v3/gicv3_helpers.c \ drivers/arm/gic/v3/gicdv3_helpers.c \ |