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| author | Alistair Delva <adelva@google.com> | 2021-02-16 21:01:22 +0000 |
|---|---|---|
| committer | Automerger Merge Worker <android-build-automerger-merge-worker@system.gserviceaccount.com> | 2021-02-16 21:01:22 +0000 |
| commit | efb2826bb8160e2d8e0fcec85133a7468484f9fd (patch) | |
| tree | 37a21c69306801ee7cdda5167a30896c8740155b /plat/allwinner/common/sunxi_security.c | |
| parent | b00a71fc312c9781fa6f404dccfb55b062b2ccac (diff) | |
| parent | faa476c0caaa598afa5a6109d17102db5fe35ec6 (diff) | |
| download | platform_external_arm-trusted-firmware-master.tar.gz platform_external_arm-trusted-firmware-master.tar.bz2 platform_external_arm-trusted-firmware-master.zip | |
Merge branch 'aosp/upstream-master' into HEAD am: faa476c0caHEADandroid-s-beta-5android-s-beta-4android-s-beta-3android-s-beta-2android-s-beta-1mastermain-cg-testing-releaseandroid-s-beta-5android-s-beta-4
Original change: https://android-review.googlesource.com/c/platform/external/arm-trusted-firmware/+/1589611
MUST ONLY BE SUBMITTED BY AUTOMERGER
Change-Id: I3a25534ceed4f8e188510641080d8b8ed49b8f62
Diffstat (limited to 'plat/allwinner/common/sunxi_security.c')
| -rw-r--r-- | plat/allwinner/common/sunxi_security.c | 21 |
1 files changed, 7 insertions, 14 deletions
diff --git a/plat/allwinner/common/sunxi_security.c b/plat/allwinner/common/sunxi_security.c index 1f16a0b72..98b91c39f 100644 --- a/plat/allwinner/common/sunxi_security.c +++ b/plat/allwinner/common/sunxi_security.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2017-2020, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -7,16 +7,11 @@ #include <common/debug.h> #include <lib/mmio.h> +#include <sunxi_ccu.h> #include <sunxi_mmap.h> #include <sunxi_private.h> +#include <sunxi_spc.h> -#ifdef SUNXI_SPC_BASE -#define SPC_DECPORT_STA_REG(p) (SUNXI_SPC_BASE + ((p) * 0x0c) + 0x4) -#define SPC_DECPORT_SET_REG(p) (SUNXI_SPC_BASE + ((p) * 0x0c) + 0x8) -#define SPC_DECPORT_CLR_REG(p) (SUNXI_SPC_BASE + ((p) * 0x0c) + 0xc) -#endif - -#define R_PRCM_SEC_SWITCH_REG 0x1d0 #define DMA_SEC_REG 0x20 /* @@ -27,20 +22,18 @@ */ void sunxi_security_setup(void) { -#ifdef SUNXI_SPC_BASE int i; INFO("Configuring SPC Controller\n"); /* SPC setup: set all devices to non-secure */ - for (i = 0; i < 6; i++) - mmio_write_32(SPC_DECPORT_SET_REG(i), 0xff); -#endif + for (i = 0; i < SUNXI_SPC_NUM_PORTS; i++) + mmio_write_32(SUNXI_SPC_DECPORT_SET_REG(i), 0xffffffff); /* set MBUS clocks, bus clocks (AXI/AHB/APB) and PLLs to non-secure */ mmio_write_32(SUNXI_CCU_SEC_SWITCH_REG, 0x7); - /* set R_PRCM clocks to non-secure */ - mmio_write_32(SUNXI_R_PRCM_BASE + R_PRCM_SEC_SWITCH_REG, 0x7); + /* Set R_PRCM bus clocks to non-secure */ + mmio_write_32(SUNXI_R_PRCM_SEC_SWITCH_REG, 0x1); /* Set all DMA channels (16 max.) to non-secure */ mmio_write_32(SUNXI_DMA_BASE + DMA_SEC_REG, 0xffff); |