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| author | Antonio Niño Díaz <antonio.ninodiaz@arm.com> | 2019-02-04 18:14:58 +0000 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2019-02-04 18:14:58 +0000 |
| commit | 6ce303468863f4a9a5bc1204532fcb31eca6cacb (patch) | |
| tree | a830e3c31daf1903e620ee45b23266bc8c0da19c /maintainers.rst | |
| parent | c57abde6f5b018a10162a76c1420f316dee1e50d (diff) | |
| parent | 9d82ef26c657fda9ee21806817c7a16547b0b605 (diff) | |
| download | platform_external_arm-trusted-firmware-6ce303468863f4a9a5bc1204532fcb31eca6cacb.tar.gz platform_external_arm-trusted-firmware-6ce303468863f4a9a5bc1204532fcb31eca6cacb.tar.bz2 platform_external_arm-trusted-firmware-6ce303468863f4a9a5bc1204532fcb31eca6cacb.zip | |
Merge pull request #1783 from thloh85-intel/integration_v2
plat: intel: Add BL2 support for Stratix 10 SoC
Diffstat (limited to 'maintainers.rst')
| -rw-r--r-- | maintainers.rst | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/maintainers.rst b/maintainers.rst index 987b9623d..5bbaf3b04 100644 --- a/maintainers.rst +++ b/maintainers.rst @@ -93,6 +93,12 @@ HiSilicon Poplar platform port :F: docs/plat/poplar.rst :F: plat/hisilicon/poplar/ +Intel SocFPGA platform ports +---------------------------- +:M: Tien Hock Loh <tien.hock.loh@intel.com> +:G: `thloh85-intel` +:F: plat/intel/soc + MediaTek platform ports ----------------------- :M: Yidi Lin (林以廸) <yidi.lin@mediatek.com> |