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authorVarun Wadekar <vwadekar@nvidia.com>2018-06-29 13:34:51 -0700
committerVarun Wadekar <vwadekar@nvidia.com>2020-03-06 08:53:33 -0800
commitd439cea9e8dc500008804f5667b30f332bf4fcbf (patch)
tree4a1efeda598c84bcfdfd48955406e164cce6cee9 /lib
parent03ea84c345e990cc6a188fbed508985461278cbb (diff)
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locks: bakery: add a DMB to the 'read_cache_op' macro
ARM has a weak memory ordering model. This means that without explicit barriers, memory accesses can be observed differently than program order. In this case, the cache invalidate instruction can be observed after the subsequent read to address. To solve this, a DMB instruction is required between the cache invalidate and the read. This ensures that the cache invalidate completes before all memory accesses in program order after the DMB. This patch updates the 'read_cache_op' macro to issue a DMB after the cache invalidate instruction to fix this anomaly. Change-Id: Iac9a90d228c57ba8bcdca7e409ea6719546ab441 Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Diffstat (limited to 'lib')
-rw-r--r--lib/locks/bakery/bakery_lock_normal.c3
1 files changed, 3 insertions, 0 deletions
diff --git a/lib/locks/bakery/bakery_lock_normal.c b/lib/locks/bakery/bakery_lock_normal.c
index caced8f46..0605fceb9 100644
--- a/lib/locks/bakery/bakery_lock_normal.c
+++ b/lib/locks/bakery/bakery_lock_normal.c
@@ -1,5 +1,6 @@
/*
* Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2020, NVIDIA Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -77,6 +78,8 @@ static inline void read_cache_op(uintptr_t addr, bool cached)
{
if (cached)
dccivac(addr);
+
+ dmbish();
}
/* Helper function to check if the lock is acquired */