Merge pull request #1399 from danielboulby-arm/db/MISRA

MISRA 5.1, 5.3 & 5.7 compliance changes

5 files changed, 57 insertions, 57 deletions

diff --git a/lib/cpus/aarch64/cpuamu.c b/lib/cpus/aarch64/cpuamu.c
index b9bad8604..5ad5bf839 100644
--- a/lib/cpus/aarch64/cpuamu.c
+++ b/lib/cpus/aarch64/cpuamu.c
@@ -10,12 +10,12 @@
 
 #define CPUAMU_NR_COUNTERS	5U
 
-struct amu_ctx {
+struct cpuamu_ctx {
 	uint64_t cnts[CPUAMU_NR_COUNTERS];
 	unsigned int mask;
 };
 
-static struct amu_ctx amu_ctxs[PLATFORM_CORE_COUNT];
+static struct cpuamu_ctx cpuamu_ctxs[PLATFORM_CORE_COUNT];
 
 int midr_match(unsigned int cpu_midr)
 {
@@ -29,7 +29,7 @@ int midr_match(unsigned int cpu_midr)
 
 void cpuamu_context_save(unsigned int nr_counters)
 {
-	struct amu_ctx *ctx = &amu_ctxs[plat_my_core_pos()];
+	struct cpuamu_ctx *ctx = &cpuamu_ctxs[plat_my_core_pos()];
 	unsigned int i;
 
 	assert(nr_counters <= CPUAMU_NR_COUNTERS);
@@ -48,7 +48,7 @@ void cpuamu_context_save(unsigned int nr_counters)
 
 void cpuamu_context_restore(unsigned int nr_counters)
 {
-	struct amu_ctx *ctx = &amu_ctxs[plat_my_core_pos()];
+	struct cpuamu_ctx *ctx = &cpuamu_ctxs[plat_my_core_pos()];
 	unsigned int i;
 
 	assert(nr_counters <= CPUAMU_NR_COUNTERS);
diff --git a/lib/locks/bakery/bakery_lock_coherent.c b/lib/locks/bakery/bakery_lock_coherent.c
index a857e0355..788ba9818 100644
--- a/lib/locks/bakery/bakery_lock_coherent.c
+++ b/lib/locks/bakery/bakery_lock_coherent.c
@@ -34,9 +34,9 @@
  * accesses regardless of status of address translation.
  */
 
-#define assert_bakery_entry_valid(entry, bakery) do {	\
-	assert(bakery);					\
-	assert(entry < BAKERY_LOCK_MAX_CPUS);		\
+#define assert_bakery_entry_valid(_entry, _bakery) do {	\
+	assert(_bakery);					\
+	assert(_entry < BAKERY_LOCK_MAX_CPUS);		\
 } while (0)
 
 /* Obtain a ticket for a given CPU */
diff --git a/lib/locks/bakery/bakery_lock_normal.c b/lib/locks/bakery/bakery_lock_normal.c
index 37697f521..630226ae2 100644
--- a/lib/locks/bakery/bakery_lock_normal.c
+++ b/lib/locks/bakery/bakery_lock_normal.c
@@ -53,18 +53,18 @@ CASSERT((PLAT_PERCPU_BAKERY_LOCK_SIZE & (CACHE_WRITEBACK_GRANULE - 1)) == 0, \
 IMPORT_SYM(uintptr_t, __PERCPU_BAKERY_LOCK_SIZE__, PERCPU_BAKERY_LOCK_SIZE);
 #endif
 
-#define get_bakery_info(cpu_ix, lock)	\
-	(bakery_info_t *)((uintptr_t)lock + cpu_ix * PERCPU_BAKERY_LOCK_SIZE)
+#define get_bakery_info(_cpu_ix, _lock)	\
+	(bakery_info_t *)((uintptr_t)_lock + _cpu_ix * PERCPU_BAKERY_LOCK_SIZE)
 
-#define write_cache_op(addr, cached)	\
+#define write_cache_op(_addr, _cached)	\
 				do {	\
-					(cached ? dccvac((uintptr_t)addr) :\
-						dcivac((uintptr_t)addr));\
+					(_cached ? dccvac((uintptr_t)_addr) :\
+						dcivac((uintptr_t)_addr));\
 						dsbish();\
 				} while (0)
 
-#define read_cache_op(addr, cached)	if (cached) \
-					    dccivac((uintptr_t)addr)
+#define read_cache_op(_addr, _cached)	if (_cached) \
+					    dccivac((uintptr_t)_addr)
 
 /* Helper function to check if the lock is acquired */
 static inline int is_lock_acquired(const bakery_info_t *my_bakery_info,
diff --git a/lib/optee/optee_utils.c b/lib/optee/optee_utils.c
index ac51265ed..ecf7cc057 100644
--- a/lib/optee/optee_utils.c
+++ b/lib/optee/optee_utils.c
@@ -43,7 +43,7 @@ typedef struct optee_header {
 	uint8_t arch;
 	uint16_t flags;
 	uint32_t nb_images;
-	optee_image_t optee_image[];
+	optee_image_t optee_image_list[];
 } optee_header_t;
 
 /*******************************************************************************
@@ -51,11 +51,11 @@ typedef struct optee_header {
  * Return 1 if valid
  * Return 0 if invalid
  ******************************************************************************/
-static inline int tee_validate_header(optee_header_t *optee_header)
+static inline int tee_validate_header(optee_header_t *header)
 {
-	if ((optee_header->magic == TEE_MAGIC_NUM_OPTEE) &&
-		(optee_header->version == 2) &&
-		(optee_header->nb_images <= OPTEE_MAX_IMAGE_NUM)) {
+	if ((header->magic == TEE_MAGIC_NUM_OPTEE) &&
+		(header->version == 2) &&
+		(header->nb_images <= OPTEE_MAX_IMAGE_NUM)) {
 		return 1;
 	}
 
@@ -68,14 +68,14 @@ static inline int tee_validate_header(optee_header_t *optee_header)
  * Return 0 on success or a negative error code otherwise.
  ******************************************************************************/
 static int parse_optee_image(image_info_t *image_info,
-		optee_image_t *optee_image)
+		optee_image_t *image)
 {
 	uintptr_t init_load_addr, free_end, requested_end;
 	size_t init_size;
 
-	init_load_addr = ((uint64_t)optee_image->load_addr_hi << 32) |
-					optee_image->load_addr_lo;
-	init_size = optee_image->size;
+	init_load_addr = ((uint64_t)image->load_addr_hi << 32) |
+					image->load_addr_lo;
+	init_size = image->size;
 
 	/*
 	 * -1 indicates loader decided address; take our pre-mapped area
@@ -133,21 +133,21 @@ int parse_optee_header(entry_point_info_t *header_ep,
 		image_info_t *paged_image_info)
 
 {
-	optee_header_t *optee_header;
+	optee_header_t *header;
 	int num, ret;
 
 	assert(header_ep);
-	optee_header = (optee_header_t *)header_ep->pc;
-	assert(optee_header);
+	header = (optee_header_t *)header_ep->pc;
+	assert(header);
 
 	/* Print the OPTEE header information */
 	INFO("OPTEE ep=0x%x\n", (unsigned int)header_ep->pc);
 	INFO("OPTEE header info:\n");
-	INFO("      magic=0x%x\n", optee_header->magic);
-	INFO("      version=0x%x\n", optee_header->version);
-	INFO("      arch=0x%x\n", optee_header->arch);
-	INFO("      flags=0x%x\n", optee_header->flags);
-	INFO("      nb_images=0x%x\n", optee_header->nb_images);
+	INFO("      magic=0x%x\n", header->magic);
+	INFO("      version=0x%x\n", header->version);
+	INFO("      arch=0x%x\n", header->arch);
+	INFO("      flags=0x%x\n", header->flags);
+	INFO("      nb_images=0x%x\n", header->nb_images);
 
 	/*
 	 * OPTEE image has 3 types:
@@ -166,7 +166,7 @@ int parse_optee_header(entry_point_info_t *header_ep,
 	 *	pager and pageable. Remove skip attr for BL32_EXTRA1_IMAGE_ID
 	 *	and BL32_EXTRA2_IMAGE_ID to load pager and paged bin.
 	 */
-	if (!tee_validate_header(optee_header)) {
+	if (!tee_validate_header(header)) {
 		INFO("Invalid OPTEE header, set legacy mode.\n");
 #ifdef AARCH64
 		header_ep->args.arg0 = MODE_RW_64;
@@ -177,15 +177,15 @@ int parse_optee_header(entry_point_info_t *header_ep,
 	}
 
 	/* Parse OPTEE image */
-	for (num = 0; num < optee_header->nb_images; num++) {
-		if (optee_header->optee_image[num].image_id ==
+	for (num = 0; num < header->nb_images; num++) {
+		if (header->optee_image_list[num].image_id ==
 				OPTEE_PAGER_IMAGE_ID) {
 			ret = parse_optee_image(pager_image_info,
-				&optee_header->optee_image[num]);
-		} else if (optee_header->optee_image[num].image_id ==
+				&header->optee_image_list[num]);
+		} else if (header->optee_image_list[num].image_id ==
 				OPTEE_PAGED_IMAGE_ID) {
 			ret = parse_optee_image(paged_image_info,
-				&optee_header->optee_image[num]);
+				&header->optee_image_list[num]);
 		} else {
 			ERROR("Parse optee image failed.\n");
 			return -1;
@@ -211,7 +211,7 @@ int parse_optee_header(entry_point_info_t *header_ep,
 	header_ep->args.arg2 = paged_image_info->image_size;
 
 	/* Set OPTEE runtime arch - aarch32/aarch64 */
-	if (optee_header->arch == 0) {
+	if (header->arch == 0) {
 		header_ep->args.arg0 = MODE_RW_32;
 	} else {
 #ifdef AARCH64
diff --git a/lib/psci/psci_private.h b/lib/psci/psci_private.h
index c58f32969..d452e2ae0 100644
--- a/lib/psci/psci_private.h
+++ b/lib/psci/psci_private.h
@@ -65,8 +65,8 @@
 
 #endif
 
-#define psci_lock_init(non_cpu_pd_node, idx)			\
-	((non_cpu_pd_node)[(idx)].lock_index = (idx))
+#define psci_lock_init(_non_cpu_pd_node, _idx)			\
+	((_non_cpu_pd_node)[(_idx)].lock_index = (_idx))
 
 /*
  * The PSCI capability which are provided by the generic code but does not
@@ -96,35 +96,35 @@
 /*
  * Helper macros to get/set the fields of PSCI per-cpu data.
  */
-#define psci_set_aff_info_state(aff_state) \
-		set_cpu_data(psci_svc_cpu_data.aff_info_state, aff_state)
+#define psci_set_aff_info_state(_aff_state) \
+		set_cpu_data(psci_svc_cpu_data.aff_info_state, _aff_state)
 #define psci_get_aff_info_state() \
 		get_cpu_data(psci_svc_cpu_data.aff_info_state)
-#define psci_get_aff_info_state_by_idx(idx) \
-		get_cpu_data_by_index(idx, psci_svc_cpu_data.aff_info_state)
-#define psci_set_aff_info_state_by_idx(idx, aff_state) \
-		set_cpu_data_by_index(idx, psci_svc_cpu_data.aff_info_state,\
-					aff_state)
+#define psci_get_aff_info_state_by_idx(_idx) \
+		get_cpu_data_by_index(_idx, psci_svc_cpu_data.aff_info_state)
+#define psci_set_aff_info_state_by_idx(_idx, _aff_state) \
+		set_cpu_data_by_index(_idx, psci_svc_cpu_data.aff_info_state,\
+					_aff_state)
 #define psci_get_suspend_pwrlvl() \
 		get_cpu_data(psci_svc_cpu_data.target_pwrlvl)
-#define psci_set_suspend_pwrlvl(target_lvl) \
-		set_cpu_data(psci_svc_cpu_data.target_pwrlvl, target_lvl)
-#define psci_set_cpu_local_state(state) \
-		set_cpu_data(psci_svc_cpu_data.local_state, state)
+#define psci_set_suspend_pwrlvl(_target_lvl) \
+		set_cpu_data(psci_svc_cpu_data.target_pwrlvl, _target_lvl)
+#define psci_set_cpu_local_state(_state) \
+		set_cpu_data(psci_svc_cpu_data.local_state, _state)
 #define psci_get_cpu_local_state() \
 		get_cpu_data(psci_svc_cpu_data.local_state)
-#define psci_get_cpu_local_state_by_idx(idx) \
-		get_cpu_data_by_index(idx, psci_svc_cpu_data.local_state)
+#define psci_get_cpu_local_state_by_idx(_idx) \
+		get_cpu_data_by_index(_idx, psci_svc_cpu_data.local_state)
 
 /*
  * Helper macros for the CPU level spinlocks
  */
-#define psci_spin_lock_cpu(idx)	spin_lock(&psci_cpu_pd_nodes[idx].cpu_lock)
-#define psci_spin_unlock_cpu(idx) spin_unlock(&psci_cpu_pd_nodes[idx].cpu_lock)
+#define psci_spin_lock_cpu(_idx) spin_lock(&psci_cpu_pd_nodes[_idx].cpu_lock)
+#define psci_spin_unlock_cpu(_idx) spin_unlock(&psci_cpu_pd_nodes[_idx].cpu_lock)
 
 /* Helper macro to identify a CPU standby request in PSCI Suspend call */
-#define is_cpu_standby_req(is_power_down_state, retn_lvl) \
-		(((!(is_power_down_state)) && ((retn_lvl) == 0)) ? 1 : 0)
+#define is_cpu_standby_req(_is_power_down_state, _retn_lvl) \
+		(((!(_is_power_down_state)) && ((_retn_lvl) == 0)) ? 1 : 0)
 
 /*******************************************************************************
  * The following two data structures implement the power domain tree. The tree