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| author | Soby Mathew <soby.mathew@arm.com> | 2014-09-22 14:13:34 +0100 |
|---|---|---|
| committer | Soby Mathew <soby.mathew@arm.com> | 2014-10-29 17:39:59 +0000 |
| commit | 5541bb3f61ae97b49203939f940931455b2f3037 (patch) | |
| tree | 13a011a9857ba598ccb96563b4b33919bb491b96 /lib | |
| parent | b1a9631d8110a2bcd458ec5809b50d5263a200ef (diff) | |
| download | platform_external_arm-trusted-firmware-5541bb3f61ae97b49203939f940931455b2f3037.tar.gz platform_external_arm-trusted-firmware-5541bb3f61ae97b49203939f940931455b2f3037.tar.bz2 platform_external_arm-trusted-firmware-5541bb3f61ae97b49203939f940931455b2f3037.zip | |
Optimize Cortex-A57 cluster power down sequence on Juno
This patch optimizes the Cortex-A57 cluster power down sequence by not
flushing the Level1 data cache. The L1 data cache and the L2 unified
cache are inclusive. A flush of the L2 by set/way flushes any dirty
lines from the L1 as well. This is a known safe deviation from the
Cortex-A57 TRM defined power down sequence. This optimization can be
enabled by the platform through the 'SKIP_A57_L1_FLUSH_PWR_DWN' build
flag. Each Cortex-A57 based platform must make its own decision on
whether to use the optimization.
This patch also renames the cpu-errata-workarounds.md to
cpu-specific-build-macros.md as this facilitates documentation
of both CPU Specific errata and CPU Specific Optimization
build macros.
Change-Id: I299b9fe79e9a7e08e8a0dffb7d345f9a00a71480
Diffstat (limited to 'lib')
| -rw-r--r-- | lib/cpus/aarch64/cortex_a57.S | 3 | ||||
| -rw-r--r-- | lib/cpus/cpu-ops.mk (renamed from lib/cpus/cpu-errata.mk) | 9 |
2 files changed, 11 insertions, 1 deletions
diff --git a/lib/cpus/aarch64/cortex_a57.S b/lib/cpus/aarch64/cortex_a57.S index c2e11bd93..dab16d7e0 100644 --- a/lib/cpus/aarch64/cortex_a57.S +++ b/lib/cpus/aarch64/cortex_a57.S @@ -222,13 +222,14 @@ func cortex_a57_cluster_pwr_dwn */ bl cortex_a57_disable_l2_prefetch +#if !SKIP_A57_L1_FLUSH_PWR_DWN /* ------------------------------------------------- * Flush the L1 caches. * ------------------------------------------------- */ mov x0, #DCCISW bl dcsw_op_level1 - +#endif /* --------------------------------------------- * Disable the optional ACP. * --------------------------------------------- diff --git a/lib/cpus/cpu-errata.mk b/lib/cpus/cpu-ops.mk index 79f0156db..1c5512e9c 100644 --- a/lib/cpus/cpu-errata.mk +++ b/lib/cpus/cpu-ops.mk @@ -28,6 +28,15 @@ # POSSIBILITY OF SUCH DAMAGE. # +# Cortex A57 specific optimisation to skip L1 cache flush when +# cluster is powered down. +SKIP_A57_L1_FLUSH_PWR_DWN ?=0 + +# Process SKIP_A57_L1_FLUSH_PWR_DWN flag +$(eval $(call assert_boolean,SKIP_A57_L1_FLUSH_PWR_DWN)) +$(eval $(call add_define,SKIP_A57_L1_FLUSH_PWR_DWN)) + + # CPU Errata Build flags. These should be enabled by the # platform if the errata needs to be applied. |