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| author | Eleanor Bonnici <Eleanor.bonnici@arm.com> | 2017-08-02 16:35:04 +0100 |
|---|---|---|
| committer | Jeenu Viswambharan <jeenu.viswambharan@arm.com> | 2017-09-07 14:22:02 +0100 |
| commit | 45b52c202f7173d7610e2ca667907a6e646e90fa (patch) | |
| tree | ec9cb3dd2a6b57635391be589dd433e1ee45e30e /lib | |
| parent | 5457874575a67b08606a35682e1dd9a5ebb984e8 (diff) | |
| download | platform_external_arm-trusted-firmware-45b52c202f7173d7610e2ca667907a6e646e90fa.tar.gz platform_external_arm-trusted-firmware-45b52c202f7173d7610e2ca667907a6e646e90fa.tar.bz2 platform_external_arm-trusted-firmware-45b52c202f7173d7610e2ca667907a6e646e90fa.zip | |
Cortex-A57: Implement workaround for erratum 859972
Erratum 855972 applies to revision r1p3 or earlier Cortex-A57 CPUs. The
recommended workaround is to disable instruction prefetch.
Change-Id: I56eeac0b753eb1432bd940083372ad6f7e93b16a
Signed-off-by: Eleanor Bonnici <Eleanor.bonnici@arm.com>
Signed-off-by: Jeenu Viswambharan <jeenu.viswambharan@arm.com>
Diffstat (limited to 'lib')
| -rw-r--r-- | lib/cpus/aarch32/cortex_a57.S | 32 | ||||
| -rw-r--r-- | lib/cpus/aarch64/cortex_a57.S | 31 | ||||
| -rw-r--r-- | lib/cpus/cpu-ops.mk | 8 |
3 files changed, 71 insertions, 0 deletions
diff --git a/lib/cpus/aarch32/cortex_a57.S b/lib/cpus/aarch32/cortex_a57.S index e4aad7909..b5189e77f 100644 --- a/lib/cpus/aarch32/cortex_a57.S +++ b/lib/cpus/aarch32/cortex_a57.S @@ -306,6 +306,32 @@ func check_errata_833471 b cpu_rev_var_ls endfunc check_errata_833471 + /* --------------------------------------------------- + * Errata Workaround for Cortex A57 Errata #859972. + * This applies only to revision <= r1p3 of Cortex A57. + * Inputs: + * r0: variant[4:7] and revision[0:3] of current cpu. + * Shall clobber: r0-r3 + * --------------------------------------------------- + */ +func errata_a57_859972_wa + mov r2, lr + bl check_errata_859972 + mov lr, r2 + cmp r0, #ERRATA_NOT_APPLIES + beq 1f + ldcopr16 r0, r1, CORTEX_A57_CPUACTLR + orr64_imm r1, r1, CORTEX_A57_CPUACTLR_DIS_INSTR_PREFETCH + stcopr16 r0, r1, CORTEX_A57_CPUACTLR +1: + bx lr +endfunc errata_a57_859972_wa + +func check_errata_859972 + mov r1, #0x13 + b cpu_rev_var_ls +endfunc check_errata_859972 + /* ------------------------------------------------- * The CPU Ops reset function for Cortex-A57. * Shall clobber: r0-r6 @@ -356,6 +382,11 @@ func cortex_a57_reset_func bl errata_a57_833471_wa #endif +#if ERRATA_A57_859972 + mov r0, r4 + bl errata_a57_859972_wa +#endif + /* --------------------------------------------- * Enable the SMP bit. * --------------------------------------------- @@ -487,6 +518,7 @@ func cortex_a57_errata_report report_errata ERRATA_A57_828024, cortex_a57, 828024 report_errata ERRATA_A57_829520, cortex_a57, 829520 report_errata ERRATA_A57_833471, cortex_a57, 833471 + report_errata ERRATA_A57_859972, cortex_a57, 859972 pop {r12, lr} bx lr diff --git a/lib/cpus/aarch64/cortex_a57.S b/lib/cpus/aarch64/cortex_a57.S index 289d0d4e4..a720e984a 100644 --- a/lib/cpus/aarch64/cortex_a57.S +++ b/lib/cpus/aarch64/cortex_a57.S @@ -304,6 +304,30 @@ func check_errata_833471 b cpu_rev_var_ls endfunc check_errata_833471 + /* -------------------------------------------------- + * Errata Workaround for Cortex A57 Errata #859972. + * This applies only to revision <= r1p3 of Cortex A57. + * Inputs: + * x0: variant[4:7] and revision[0:3] of current cpu. + * Shall clobber: + * -------------------------------------------------- + */ +func errata_a57_859972_wa + mov x17, x30 + bl check_errata_859972 + cbz x0, 1f + mrs x1, CORTEX_A57_CPUACTLR_EL1 + orr x1, x1, #CORTEX_A57_CPUACTLR_EL1_DIS_INSTR_PREFETCH + msr CORTEX_A57_CPUACTLR_EL1, x1 +1: + ret x17 +endfunc errata_a57_859972_wa + +func check_errata_859972 + mov x1, #0x13 + b cpu_rev_var_ls +endfunc check_errata_859972 + /* ------------------------------------------------- * The CPU Ops reset function for Cortex-A57. * Shall clobber: x0-x19 @@ -354,6 +378,11 @@ func cortex_a57_reset_func bl errata_a57_833471_wa #endif +#if ERRATA_A57_859972 + mov x0, x18 + bl errata_a57_859972_wa +#endif + /* --------------------------------------------- * Enable the SMP bit. * --------------------------------------------- @@ -483,6 +512,8 @@ func cortex_a57_errata_report report_errata ERRATA_A57_828024, cortex_a57, 828024 report_errata ERRATA_A57_829520, cortex_a57, 829520 report_errata ERRATA_A57_833471, cortex_a57, 833471 + report_errata ERRATA_A57_859972, cortex_a57, 859972 + ldp x8, x30, [sp], #16 ret diff --git a/lib/cpus/cpu-ops.mk b/lib/cpus/cpu-ops.mk index ad3297196..198a32e3c 100644 --- a/lib/cpus/cpu-ops.mk +++ b/lib/cpus/cpu-ops.mk @@ -91,6 +91,10 @@ ERRATA_A57_829520 ?=0 # only to revision <= r1p2 of the Cortex A57 cpu. ERRATA_A57_833471 ?=0 +# Flag to apply erratum 855972 workaround during reset. This erratum applies +# only to revision <= r1p3 of the Cortex A57 cpu. +ERRATA_A57_859972 ?=0 + # Process ERRATA_A53_826319 flag $(eval $(call assert_boolean,ERRATA_A53_826319)) $(eval $(call add_define,ERRATA_A53_826319)) @@ -143,6 +147,10 @@ $(eval $(call add_define,ERRATA_A57_829520)) $(eval $(call assert_boolean,ERRATA_A57_833471)) $(eval $(call add_define,ERRATA_A57_833471)) +# Process ERRATA_A57_859972 flag +$(eval $(call assert_boolean,ERRATA_A57_859972)) +$(eval $(call add_define,ERRATA_A57_859972)) + # Errata build flags ifneq (${ERRATA_A53_843419},0) TF_LDFLAGS_aarch64 += --fix-cortex-a53-843419 |