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| author | Jimmy Brisson <jimmy.brisson@arm.com> | 2020-04-16 10:48:02 -0500 |
|---|---|---|
| committer | Jimmy Brisson <jimmy.brisson@arm.com> | 2020-06-02 09:18:58 -0500 |
| commit | 29d0ee542dc171d3b75db82c7f7f2dae0ffab64f (patch) | |
| tree | 4a41a98b1d3f8e998889ed2db2b3f62d855622f3 /lib | |
| parent | 110ee4330af41a83afff102c8852c1dc161b7501 (diff) | |
| download | platform_external_arm-trusted-firmware-29d0ee542dc171d3b75db82c7f7f2dae0ffab64f.tar.gz platform_external_arm-trusted-firmware-29d0ee542dc171d3b75db82c7f7f2dae0ffab64f.tar.bz2 platform_external_arm-trusted-firmware-29d0ee542dc171d3b75db82c7f7f2dae0ffab64f.zip | |
Enable ARMv8.6-ECV Self-Synch when booting to EL2
Enhanced Counter Virtualization, ECV, is an architecture extension introduced
in ARMv8.6. This extension allows the hypervisor, at EL2, to setup
self-synchronizing views of the timers for it's EL1 Guests. This patch pokes the
control register to enable this extension when booting a hypervisor at EL2.
Change-Id: I4e929ecdf400cea17eff1de5cf8704aa7e40973d
Signed-off-by: Jimmy Brisson <jimmy.brisson@arm.com>
Diffstat (limited to 'lib')
| -rw-r--r-- | lib/el3_runtime/aarch64/context_mgmt.c | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/lib/el3_runtime/aarch64/context_mgmt.c b/lib/el3_runtime/aarch64/context_mgmt.c index 1c5ba3608..53b4ea3e3 100644 --- a/lib/el3_runtime/aarch64/context_mgmt.c +++ b/lib/el3_runtime/aarch64/context_mgmt.c @@ -176,6 +176,9 @@ void cm_setup_context(cpu_context_t *ctx, const entry_point_info_t *ep) * SCR_EL3.FGTEn: Enable Fine Grained Virtualization Traps under the * same conditions as HVC instructions and when the processor supports * ARMv8.6-FGT. + * SCR_EL3.ECVEn: Enable Enhanced Counter Virtualization (ECV) + * CNTPOFF_EL2 register under the same conditions as HVC instructions + * and when the processor supports ECV. */ if (((GET_RW(ep->spsr) == MODE_RW_64) && (GET_EL(ep->spsr) == MODE_EL2)) || ((GET_RW(ep->spsr) != MODE_RW_64) @@ -185,6 +188,11 @@ void cm_setup_context(cpu_context_t *ctx, const entry_point_info_t *ep) if (is_armv8_6_fgt_present()) { scr_el3 |= SCR_FGTEN_BIT; } + + if (get_armv8_6_ecv_support() + == ID_AA64MMFR0_EL1_ECV_SELF_SYNCH) { + scr_el3 |= SCR_ECVEN_BIT; + } } /* Enable S-EL2 if the next EL is EL2 and security state is secure */ |