diff options
author | Samuel Holland <samuel@sholland.org> | 2018-10-17 21:40:18 -0500 |
---|---|---|
committer | Samuel Holland <samuel@sholland.org> | 2019-12-29 12:00:40 -0600 |
commit | f8578e641b38694a6a2dee84ef7a7b3b0b50bd0f (patch) | |
tree | 8dba3d725b4d35aac1662ecc1e762834830f8426 /lib/psci/psci_private.h | |
parent | caa0c85d2f8ae61c6ff630ca0cd5ef77ea91f1fc (diff) | |
download | platform_external_arm-trusted-firmware-f8578e641b38694a6a2dee84ef7a7b3b0b50bd0f.tar.gz platform_external_arm-trusted-firmware-f8578e641b38694a6a2dee84ef7a7b3b0b50bd0f.tar.bz2 platform_external_arm-trusted-firmware-f8578e641b38694a6a2dee84ef7a7b3b0b50bd0f.zip |
bl31: Split into two separate memory regions
Some platforms are extremely memory constrained and must split BL31
between multiple non-contiguous areas in SRAM. Allow the NOBITS
sections (.bss, stacks, page tables, and coherent memory) to be placed
in a separate region of RAM from the loaded firmware image.
Because the NOBITS region may be at a lower address than the rest of
BL31, __RW_{START,END}__ and __BL31_{START,END}__ cannot include this
region, or el3_entrypoint_common would attempt to invalidate the dcache
for the entire address space. New symbols __NOBITS_{START,END}__ are
added when SEPARATE_NOBITS_REGION is enabled, and the dcached for the
NOBITS region is invalidated separately.
Signed-off-by: Samuel Holland <samuel@sholland.org>
Change-Id: Idedfec5e4dbee77e94f2fdd356e6ae6f4dc79d37
Diffstat (limited to 'lib/psci/psci_private.h')
0 files changed, 0 insertions, 0 deletions