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| author | Petre-Ionut Tudor <petre-ionut.tudor@arm.com> | 2019-11-07 15:18:03 +0000 |
|---|---|---|
| committer | Petre-Ionut Tudor <petre-ionut.tudor@arm.com> | 2020-02-24 16:52:56 +0000 |
| commit | 60e8f3cfd5910c59c9a573ce05bd61091336b09a (patch) | |
| tree | 9e9c5b42ad746d56aaede8634501f2c71c9e68b9 /lib/aarch64 | |
| parent | 2f39c55c085ae92b6eead06172096410e5aab81c (diff) | |
| download | platform_external_arm-trusted-firmware-60e8f3cfd5910c59c9a573ce05bd61091336b09a.tar.gz platform_external_arm-trusted-firmware-60e8f3cfd5910c59c9a573ce05bd61091336b09a.tar.bz2 platform_external_arm-trusted-firmware-60e8f3cfd5910c59c9a573ce05bd61091336b09a.zip | |
Read-only xlat tables for BL31 memory
This patch introduces a build flag which allows the xlat tables
to be mapped in a read-only region within BL31 memory. It makes it
much harder for someone who has acquired the ability to write to
arbitrary secure memory addresses to gain control of the
translation tables.
The memory attributes of the descriptors describing the tables
themselves are changed to read-only secure data. This change
happens at the end of BL31 runtime setup. Until this point, the
tables have read-write permissions. This gives a window of
opportunity for changes to be made to the tables with the MMU on
(e.g. reclaiming init code). No changes can be made to the tables
with the MMU turned on from this point onwards. This change is also
enabled for sp_min and tspd.
To make all this possible, the base table was moved to .rodata. The
penalty we pay is that now .rodata must be aligned to the size of
the base table (512B alignment). Still, this is better than putting
the base table with the higher level tables in the xlat_table
section, as that would cost us a full 4KB page.
Changing the tables from read-write to read-only cannot be done with
the MMU on, as the break-before-make sequence would invalidate the
descriptor which resolves the level 3 page table where that very
descriptor is located. This would make the translation required for
writing the changes impossible, generating an MMU fault.
The caches are also flushed.
Signed-off-by: Petre-Ionut Tudor <petre-ionut.tudor@arm.com>
Change-Id: Ibe5de307e6dc94c67d6186139ac3973516430466
Diffstat (limited to 'lib/aarch64')
| -rw-r--r-- | lib/aarch64/cache_helpers.S | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/lib/aarch64/cache_helpers.S b/lib/aarch64/cache_helpers.S index 9ef8ca79b..de9c8e4f0 100644 --- a/lib/aarch64/cache_helpers.S +++ b/lib/aarch64/cache_helpers.S @@ -1,5 +1,5 @@ /* - * Copyright (c) 2013-2019, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2013-2020, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -30,7 +30,7 @@ loop_\op: dc \op, x0 add x0, x0, x2 cmp x0, x1 - b.lo loop_\op + b.lo loop_\op dsb sy exit_loop_\op: ret @@ -140,7 +140,7 @@ loop3_\_op: level_done: add x10, x10, #2 // increment cache number cmp x3, x10 - b.hi loop1 + b.hi loop1 msr csselr_el1, xzr // select cache level 0 in csselr dsb sy // barrier to complete final cache operation isb |