diff options
| author | Jimmy Brisson <jimmy.brisson@arm.com> | 2020-08-04 16:18:52 -0500 |
|---|---|---|
| committer | laurenw-arm <lauren.wehrmeister@arm.com> | 2020-10-12 10:55:03 -0500 |
| commit | d7b5f40823d449cc79e6440174390997cf11a9d9 (patch) | |
| tree | 631affeb74091069edf06596f83fbe37864942c3 /lib/aarch64/misc_helpers.S | |
| parent | 7ad39818b184850d263008e7d36ba16adf72a669 (diff) | |
| download | platform_external_arm-trusted-firmware-d7b5f40823d449cc79e6440174390997cf11a9d9.tar.gz platform_external_arm-trusted-firmware-d7b5f40823d449cc79e6440174390997cf11a9d9.tar.bz2 platform_external_arm-trusted-firmware-d7b5f40823d449cc79e6440174390997cf11a9d9.zip | |
Increase type widths to satisfy width requirements
Usually, C has no problem up-converting types to larger bit sizes. MISRA
rule 10.7 requires that you not do this, or be very explicit about this.
This resolves the following required rule:
bl1/aarch64/bl1_context_mgmt.c:81:[MISRA C-2012 Rule 10.7 (required)]<None>
The width of the composite expression "0U | ((mode & 3U) << 2U) | 1U |
0x3c0U" (32 bits) is less that the right hand operand
"18446744073709547519ULL" (64 bits).
This also resolves MISRA defects such as:
bl2/aarch64/bl2arch_setup.c:18:[MISRA C-2012 Rule 12.2 (required)]
In the expression "3U << 20", shifting more than 7 bits, the number
of bits in the essential type of the left expression, "3U", is
not allowed.
Further, MISRA requires that all shifts don't overflow. The definition of
PAGE_SIZE was (1U << 12), and 1U is 8 bits. This caused about 50 issues.
This fixes the violation by changing the definition to 1UL << 12. Since
this uses 32bits, it should not create any issues for aarch32.
This patch also contains a fix for a build failure in the sun50i_a64
platform. Specifically, these misra fixes removed a single and
instruction,
92407e73 and x19, x19, #0xffffffff
from the cm_setup_context function caused a relocation in
psci_cpus_on_start to require a linker-generated stub. This increased the
size of the .text section and caused an alignment later on to go over a
page boundary and round up to the end of RAM before placing the .data
section. This sectionn is of non-zero size and therefore causes a link
error.
The fix included in this reorders the functions during link time
without changing their ording with respect to alignment.
Change-Id: I76b4b662c3d262296728a8b9aab7a33b02087f16
Signed-off-by: Jimmy Brisson <jimmy.brisson@arm.com>
Diffstat (limited to 'lib/aarch64/misc_helpers.S')
| -rw-r--r-- | lib/aarch64/misc_helpers.S | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/lib/aarch64/misc_helpers.S b/lib/aarch64/misc_helpers.S index d298f2b66..052891683 100644 --- a/lib/aarch64/misc_helpers.S +++ b/lib/aarch64/misc_helpers.S @@ -1,5 +1,5 @@ /* - * Copyright (c) 2013-2019, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2013-2020, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -496,7 +496,7 @@ func fixup_gdt_reloc /* Test if the limits are 4K aligned */ #if ENABLE_ASSERTIONS orr x0, x0, x1 - tst x0, #(PAGE_SIZE - 1) + tst x0, #(PAGE_SIZE_MASK) ASM_ASSERT(eq) #endif /* @@ -504,7 +504,7 @@ func fixup_gdt_reloc * Assume that this function is called within a page at the start of * fixup region. */ - and x2, x30, #~(PAGE_SIZE - 1) + and x2, x30, #~(PAGE_SIZE_MASK) sub x0, x2, x6 /* Diff(S) = Current Address - Compiled Address */ adrp x1, __GOT_START__ |