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| author | Antonio Niño Díaz <antonio.ninodiaz@arm.com> | 2019-04-03 11:20:47 +0100 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2019-04-03 11:20:47 +0100 |
| commit | fc3e159134e2c2be4e48feea483f483c42de69ae (patch) | |
| tree | 3b1f8b61ac5f663eea24360eddb11820e0c5b2da /include | |
| parent | 18d4d113ec23899c23eb663cbdfafa8b837624d7 (diff) | |
| parent | 75f364b3e09c16e67dfca27318bc0fec668d688f (diff) | |
| download | platform_external_arm-trusted-firmware-fc3e159134e2c2be4e48feea483f483c42de69ae.tar.gz platform_external_arm-trusted-firmware-fc3e159134e2c2be4e48feea483f483c42de69ae.tar.bz2 platform_external_arm-trusted-firmware-fc3e159134e2c2be4e48feea483f483c42de69ae.zip | |
Merge pull request #1916 from antonio-nino-diaz-arm/an/spm-xlat
SPM: Some improvements to xlat handling code
Diffstat (limited to 'include')
| -rw-r--r-- | include/arch/aarch64/arch.h | 23 |
1 files changed, 23 insertions, 0 deletions
diff --git a/include/arch/aarch64/arch.h b/include/arch/aarch64/arch.h index d3c5beaad..d15851d81 100644 --- a/include/arch/aarch64/arch.h +++ b/include/arch/aarch64/arch.h @@ -433,6 +433,9 @@ #define TCR_TxSZ_MAX ULL(39) #define TCR_TxSZ_MAX_TTST ULL(48) +#define TCR_T0SZ_SHIFT U(0) +#define TCR_T1SZ_SHIFT U(16) + /* (internal) physical address size bits in EL3/EL1 */ #define TCR_PS_BITS_4GB ULL(0x0) #define TCR_PS_BITS_64GB ULL(0x1) @@ -462,12 +465,32 @@ #define TCR_SH_OUTER_SHAREABLE (ULL(0x2) << 12) #define TCR_SH_INNER_SHAREABLE (ULL(0x3) << 12) +#define TCR_RGN1_INNER_NC (ULL(0x0) << 24) +#define TCR_RGN1_INNER_WBA (ULL(0x1) << 24) +#define TCR_RGN1_INNER_WT (ULL(0x2) << 24) +#define TCR_RGN1_INNER_WBNA (ULL(0x3) << 24) + +#define TCR_RGN1_OUTER_NC (ULL(0x0) << 26) +#define TCR_RGN1_OUTER_WBA (ULL(0x1) << 26) +#define TCR_RGN1_OUTER_WT (ULL(0x2) << 26) +#define TCR_RGN1_OUTER_WBNA (ULL(0x3) << 26) + +#define TCR_SH1_NON_SHAREABLE (ULL(0x0) << 28) +#define TCR_SH1_OUTER_SHAREABLE (ULL(0x2) << 28) +#define TCR_SH1_INNER_SHAREABLE (ULL(0x3) << 28) + #define TCR_TG0_SHIFT U(14) #define TCR_TG0_MASK ULL(3) #define TCR_TG0_4K (ULL(0) << TCR_TG0_SHIFT) #define TCR_TG0_64K (ULL(1) << TCR_TG0_SHIFT) #define TCR_TG0_16K (ULL(2) << TCR_TG0_SHIFT) +#define TCR_TG1_SHIFT U(30) +#define TCR_TG1_MASK ULL(3) +#define TCR_TG1_16K (ULL(1) << TCR_TG1_SHIFT) +#define TCR_TG1_4K (ULL(2) << TCR_TG1_SHIFT) +#define TCR_TG1_64K (ULL(3) << TCR_TG1_SHIFT) + #define TCR_EPD0_BIT (ULL(1) << 7) #define TCR_EPD1_BIT (ULL(1) << 23) |