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| author | Dimitris Papastamos <dimitris.papastamos@arm.com> | 2018-05-17 14:41:13 +0100 |
|---|---|---|
| committer | Dimitris Papastamos <dimitris.papastamos@arm.com> | 2018-05-23 12:45:48 +0100 |
| commit | e0865708155826a70e2199a54cab8e90e8d07a32 (patch) | |
| tree | 3baf965553aa43adaf62c8e72e7b99d35e596015 /include | |
| parent | b8a25bbb0bab4e4afdbfb04bee98f0bf28141c4b (diff) | |
| download | platform_external_arm-trusted-firmware-e0865708155826a70e2199a54cab8e90e8d07a32.tar.gz platform_external_arm-trusted-firmware-e0865708155826a70e2199a54cab8e90e8d07a32.tar.bz2 platform_external_arm-trusted-firmware-e0865708155826a70e2199a54cab8e90e8d07a32.zip | |
aarch32: Implement static workaround for CVE-2018-3639
Implement static mitigation for CVE-2018-3639 on
Cortex A57 and A72.
Change-Id: I83409a16238729b84142b19e258c23737cc1ddc3
Signed-off-by: Dimitris Papastamos <dimitris.papastamos@arm.com>
Diffstat (limited to 'include')
| -rw-r--r-- | include/lib/cpus/aarch32/cortex_a57.h | 1 | ||||
| -rw-r--r-- | include/lib/cpus/aarch32/cortex_a72.h | 1 |
2 files changed, 2 insertions, 0 deletions
diff --git a/include/lib/cpus/aarch32/cortex_a57.h b/include/lib/cpus/aarch32/cortex_a57.h index 3fac9c7be..18cabe11b 100644 --- a/include/lib/cpus/aarch32/cortex_a57.h +++ b/include/lib/cpus/aarch32/cortex_a57.h @@ -44,6 +44,7 @@ #define CORTEX_A57_CPUACTLR p15, 0, c15 #define CORTEX_A57_CPUACTLR_DIS_LOAD_PASS_DMB (ULL(1) << 59) +#define CORTEX_A57_CPUACTLR_DIS_LOAD_PASS_STORE (ULL(1) << 55) #define CORTEX_A57_CPUACTLR_GRE_NGRE_AS_NGNRE (ULL(1) << 54) #define CORTEX_A57_CPUACTLR_DIS_OVERREAD (ULL(1) << 52) #define CORTEX_A57_CPUACTLR_NO_ALLOC_WBWA (ULL(1) << 49) diff --git a/include/lib/cpus/aarch32/cortex_a72.h b/include/lib/cpus/aarch32/cortex_a72.h index f7da1f013..0331ace7c 100644 --- a/include/lib/cpus/aarch32/cortex_a72.h +++ b/include/lib/cpus/aarch32/cortex_a72.h @@ -32,6 +32,7 @@ #define CORTEX_A72_CPUACTLR p15, 0, c15 #define CORTEX_A72_CPUACTLR_DISABLE_L1_DCACHE_HW_PFTCH (ULL(1) << 56) +#define CORTEX_A72_CPUACTLR_DIS_LOAD_PASS_STORE (ULL(1) << 55) #define CORTEX_A72_CPUACTLR_NO_ALLOC_WBWA (ULL(1) << 49) #define CORTEX_A72_CPUACTLR_DCC_AS_DCCI (ULL(1) << 44) #define CORTEX_A72_CPUACTLR_DIS_INSTR_PREFETCH (ULL(1) << 32) |