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| author | Manoj Kumar <manoj.kumar3@arm.com> | 2019-06-21 17:07:13 +0100 |
|---|---|---|
| committer | Manoj Kumar <manoj.kumar3@arm.com> | 2019-06-26 14:07:51 +0100 |
| commit | de8bc83ee9401acdab20fd8ae1f9cb9bf7ef7829 (patch) | |
| tree | 3e370e9e15019876c55e35f7e5f2e1b615e74aa6 /include | |
| parent | b73d296d747663ecd31caf30ddcebf4a99f39abf (diff) | |
| download | platform_external_arm-trusted-firmware-de8bc83ee9401acdab20fd8ae1f9cb9bf7ef7829.tar.gz platform_external_arm-trusted-firmware-de8bc83ee9401acdab20fd8ae1f9cb9bf7ef7829.tar.bz2 platform_external_arm-trusted-firmware-de8bc83ee9401acdab20fd8ae1f9cb9bf7ef7829.zip | |
n1sdp: add code for DDR ECC enablement and BL33 copy to DDR
N1SDP platform supports RDIMMs with ECC capability. To use the ECC
capability, the entire DDR memory space has to be zeroed out before
enabling the ECC bits in DMC620. Zeroing out several gigabytes of
memory from SCP is quite time consuming so functions are added that
zeros out the DDR memory from application processor which is
much faster compared to SCP. BL33 binary cannot be copied to DDR memory
before enabling ECC so this is also done by TF-A from IOFPGA-DDR3
memory to main DDR4 memory after ECC is enabled.
Original PLAT_PHY_ADDR_SPACE_SIZE was limited to 36-bits with which
the entire DDR space cannot be accessed as DRAM2 starts in base
0x8080000000. So these macros are redefined for all ARM platforms.
Change-Id: If09524fb65b421b7a368b1b9fc52c49f2ddb7846
Signed-off-by: Manoj Kumar <manoj.kumar3@arm.com>
Diffstat (limited to 'include')
| -rw-r--r-- | include/plat/arm/common/arm_def.h | 13 |
1 files changed, 0 insertions, 13 deletions
diff --git a/include/plat/arm/common/arm_def.h b/include/plat/arm/common/arm_def.h index 69a9959ad..ead1a8b35 100644 --- a/include/plat/arm/common/arm_def.h +++ b/include/plat/arm/common/arm_def.h @@ -312,19 +312,6 @@ *****************************************************************************/ /* - * We need to access DRAM2 from BL2 for PSCI_MEM_PROTECT for - * AArch64 builds - */ -#ifdef AARCH64 -#define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 36) -#define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 36) -#else -#define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 32) -#define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 32) -#endif - - -/* * This macro defines the deepest retention state possible. A higher state * id will represent an invalid or a power down state. */ |