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| author | Varun Wadekar <vwadekar@nvidia.com> | 2018-06-18 16:15:51 -0700 |
|---|---|---|
| committer | Varun Wadekar <vwadekar@nvidia.com> | 2020-02-20 09:25:45 -0800 |
| commit | dd4f0885a0aad2af6d873c00ac5b49e166c5e339 (patch) | |
| tree | a0a3763e95d99946be6d3909fc169b1bfb2ae5dc /include | |
| parent | d4b29105f4d4d11f4bd0f64a7ff9a49c897d804e (diff) | |
| download | platform_external_arm-trusted-firmware-dd4f0885a0aad2af6d873c00ac5b49e166c5e339.tar.gz platform_external_arm-trusted-firmware-dd4f0885a0aad2af6d873c00ac5b49e166c5e339.tar.bz2 platform_external_arm-trusted-firmware-dd4f0885a0aad2af6d873c00ac5b49e166c5e339.zip | |
Tegra: delay_timer: support for physical secure timer
This patch modifies the delay timer driver to switch to the ARM
secure physical timer instead of using Tegra's on-chip uS timer.
The secure timer is not accessible to the NS world and so eliminates
an important attack vector, where the Tegra timer source gets switched
off from the NS world leading to a DoS attack for the trusted world.
This timer is shared with the S-EL1 layer for now, but later patches
will mark it as exclusive to the EL3 exception mode.
Change-Id: I2c00f8cb4c48b25578971c626c314603906ad7cc
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Diffstat (limited to 'include')
| -rw-r--r-- | include/arch/aarch64/arch.h | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/include/arch/aarch64/arch.h b/include/arch/aarch64/arch.h index 1fcd0f9ba..1faddbedc 100644 --- a/include/arch/aarch64/arch.h +++ b/include/arch/aarch64/arch.h @@ -1,5 +1,6 @@ /* * Copyright (c) 2013-2019, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2020, NVIDIA Corporation. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -597,6 +598,10 @@ #define CNTP_CTL_IMASK_MASK U(1) #define CNTP_CTL_ISTATUS_MASK U(1) +/* Physical timer control macros */ +#define CNTP_CTL_ENABLE_BIT (U(1) << CNTP_CTL_ENABLE_SHIFT) +#define CNTP_CTL_IMASK_BIT (U(1) << CNTP_CTL_IMASK_SHIFT) + /* Exception Syndrome register bits and bobs */ #define ESR_EC_SHIFT U(26) #define ESR_EC_MASK U(0x3f) |