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| author | Grzegorz Jaszczyk <jaz@semihalf.com> | 2018-12-20 17:13:19 +0100 |
|---|---|---|
| committer | Marcin Wojtas <mw@semihalf.com> | 2020-06-07 00:06:03 +0200 |
| commit | dc402531eff62ca54c3f9f360be50c1c113d16f9 (patch) | |
| tree | 614e1bf401628018f9a16eb6589bcba6b5600e8c /include | |
| parent | 613bbde09e48874658af5a00612fe2a0b0388523 (diff) | |
| download | platform_external_arm-trusted-firmware-dc402531eff62ca54c3f9f360be50c1c113d16f9.tar.gz platform_external_arm-trusted-firmware-dc402531eff62ca54c3f9f360be50c1c113d16f9.tar.bz2 platform_external_arm-trusted-firmware-dc402531eff62ca54c3f9f360be50c1c113d16f9.zip | |
plat: marvell: add support for PLL 2.2GHz mode
Change-Id: Icb8fe14417665d6aadd5a5ee2b77547b4ef78773
Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com>
Diffstat (limited to 'include')
| -rw-r--r-- | include/drivers/marvell/aro.h | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/include/drivers/marvell/aro.h b/include/drivers/marvell/aro.h index c16f62538..c9dd36e4f 100644 --- a/include/drivers/marvell/aro.h +++ b/include/drivers/marvell/aro.h @@ -21,11 +21,17 @@ enum hws_freq { DDR_FREQ_SAR }; +#include <mvebu_def.h> + enum cpu_clock_freq_mode { CPU_2000_DDR_1200_RCLK_1200 = 0x0, CPU_2000_DDR_1050_RCLK_1050 = 0x1, CPU_1600_DDR_800_RCLK_800 = 0x4, +#ifdef MVEBU_SOC_AP807 + CPU_2200_DDR_1200_RCLK_1200 = 0x6, +#else CPU_1800_DDR_1200_RCLK_1200 = 0x6, +#endif CPU_1800_DDR_1050_RCLK_1050 = 0x7, CPU_1600_DDR_900_RCLK_900 = 0x0B, CPU_1600_DDR_1050_RCLK_1050 = 0x0D, |