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| author | johpow01 <john.powell@arm.com> | 2020-05-29 14:17:38 -0500 |
|---|---|---|
| committer | johpow01 <john.powell@arm.com> | 2020-06-22 16:58:24 -0500 |
| commit | d7b08e69044611c13f2691011a0dc02383106474 (patch) | |
| tree | 48bac5a436147056175a22b9c24ee099b8bee63b /include | |
| parent | 9935047b2086faa3bf3ccf0b95a76510eb5a160b (diff) | |
| download | platform_external_arm-trusted-firmware-d7b08e69044611c13f2691011a0dc02383106474.tar.gz platform_external_arm-trusted-firmware-d7b08e69044611c13f2691011a0dc02383106474.tar.bz2 platform_external_arm-trusted-firmware-d7b08e69044611c13f2691011a0dc02383106474.zip | |
Workaround for Cortex A76 erratum 1791580
Cortex A76 erratum 1791580 is a Cat B erratum present in earlier
revisions of the Cortex A76. The workaround is to set a bit in the
implementation defined CPUACTLR2 register, which forces atomic store
operations to write-back memory to be performed in the L1 data cache.
This errata is explained in this SDEN:
https://static.docs.arm.com/sden885749/g/Arm_Cortex_A76_MP052_Software_Developer_Errata_Notice_v20.pdf
Signed-off-by: John Powell <john.powell@arm.com>
Change-Id: Iefd58159b3f2e2286138993317b98e57dc361925
Diffstat (limited to 'include')
| -rw-r--r-- | include/lib/cpus/aarch64/cortex_a76.h | 4 |
1 files changed, 3 insertions, 1 deletions
diff --git a/include/lib/cpus/aarch64/cortex_a76.h b/include/lib/cpus/aarch64/cortex_a76.h index 7dc7e068a..a61825f1b 100644 --- a/include/lib/cpus/aarch64/cortex_a76.h +++ b/include/lib/cpus/aarch64/cortex_a76.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2017-2020, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -32,6 +32,8 @@ #define CORTEX_A76_CPUACTLR2_EL1 S3_0_C15_C1_1 +#define CORTEX_A76_CPUACTLR2_EL1_BIT_2 (ULL(1) << 2) + #define CORTEX_A76_CPUACTLR2_EL1_DISABLE_LOAD_PASS_STORE (ULL(1) << 16) #define CORTEX_A76_CPUACTLR3_EL1 S3_0_C15_C1_2 |