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| author | Varun Wadekar <vwadekar@nvidia.com> | 2018-06-12 16:49:12 -0700 |
|---|---|---|
| committer | Varun Wadekar <vwadekar@nvidia.com> | 2020-02-20 09:25:45 -0800 |
| commit | cd0ea1842f7ef5f3c8ccc3205cc0f3840f573f64 (patch) | |
| tree | d16fbe9ae43976a60290fef60aaf78e51108fcdb /include | |
| parent | eda880ff8ec77ee429f5249f08571c41232b27db (diff) | |
| download | platform_external_arm-trusted-firmware-cd0ea1842f7ef5f3c8ccc3205cc0f3840f573f64.tar.gz platform_external_arm-trusted-firmware-cd0ea1842f7ef5f3c8ccc3205cc0f3840f573f64.tar.bz2 platform_external_arm-trusted-firmware-cd0ea1842f7ef5f3c8ccc3205cc0f3840f573f64.zip | |
cpus: higher performance non-cacheable load forwarding
The CPUACTLR_EL1 register on Cortex-A57 CPUs supports a bit to enable
non-cacheable streaming enhancement. Platforms can set this bit only
if their memory system meets the requirement that cache line fill
requests from the Cortex-A57 processor are atomic.
This patch adds support to enable higher performance non-cacheable load
forwarding for such platforms. Platforms must enable this support by
setting the 'A57_ENABLE_NONCACHEABLE_LOAD_FWD' flag from their
makefiles. This flag is disabled by default.
Change-Id: Ib27e55dd68d11a50962c0bbc5b89072208b4bac5
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Diffstat (limited to 'include')
| -rw-r--r-- | include/lib/cpus/aarch64/cortex_a57.h | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/include/lib/cpus/aarch64/cortex_a57.h b/include/lib/cpus/aarch64/cortex_a57.h index 102ff60c3..dc40e31ad 100644 --- a/include/lib/cpus/aarch64/cortex_a57.h +++ b/include/lib/cpus/aarch64/cortex_a57.h @@ -1,5 +1,6 @@ /* * Copyright (c) 2014-2019, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2020, NVIDIA Corporation. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -54,6 +55,7 @@ #define CORTEX_A57_CPUACTLR_EL1_FORCE_FPSCR_FLUSH (ULL(1) << 38) #define CORTEX_A57_CPUACTLR_EL1_DIS_INSTR_PREFETCH (ULL(1) << 32) #define CORTEX_A57_CPUACTLR_EL1_DIS_STREAMING (ULL(3) << 27) +#define CORTEX_A57_CPUACTLR_EL1_EN_NC_LOAD_FWD (ULL(1) << 24) #define CORTEX_A57_CPUACTLR_EL1_DIS_L1_STREAMING (ULL(3) << 25) #define CORTEX_A57_CPUACTLR_EL1_DIS_INDIRECT_PREDICTOR (ULL(1) << 4) |