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| author | Andrew F. Davis <afd@ti.com> | 2019-01-22 12:39:31 -0600 |
|---|---|---|
| committer | Andrew F. Davis <afd@ti.com> | 2019-01-22 13:11:09 -0600 |
| commit | b5443284f4ea00c67cc3541f21ba1bcb05fea746 (patch) | |
| tree | 57e4bf920387e2054067f141444e16df2cf26cf1 /include | |
| parent | a0d894397d5729aa72840dc49120f4d198174e22 (diff) | |
| download | platform_external_arm-trusted-firmware-b5443284f4ea00c67cc3541f21ba1bcb05fea746.tar.gz platform_external_arm-trusted-firmware-b5443284f4ea00c67cc3541f21ba1bcb05fea746.tar.bz2 platform_external_arm-trusted-firmware-b5443284f4ea00c67cc3541f21ba1bcb05fea746.zip | |
ti: k3: common: Add support for runtime detection of GICR base address
Valid addresses for GICR base are always a set calculable distance from
the GICD and is based on the number of cores a given instance of GICv3 IP
can support. The formula for the number of address bits is given by the
ARM GIC-500 TRM section 3.2 as 2^(18+log2(cores)) with the MSB set to
one for GICR instances. Holes in the GIC address space are also
guaranteed to safely return 0 on reads. This allows us to support runtime
detection of the GICR base address by starting from GIC base address plus
BIT(18) and walking until the GICR ID register (IIDR) is detected. We
stop searching after BIT(20) to prevent searching out into space if
something goes wrong. This can be extended out if we ever have a device
with 16 or more cores.
Signed-off-by: Andrew F. Davis <afd@ti.com>
Diffstat (limited to 'include')
| -rw-r--r-- | include/drivers/arm/gicv3.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/include/drivers/arm/gicv3.h b/include/drivers/arm/gicv3.h index 238269774..72221acb0 100644 --- a/include/drivers/arm/gicv3.h +++ b/include/drivers/arm/gicv3.h @@ -84,6 +84,7 @@ #define GICR_PCPUBASE_SHIFT 0x11 #define GICR_SGIBASE_OFFSET U(65536) /* 64 KB */ #define GICR_CTLR U(0x0) +#define GICR_IIDR U(0x04) #define GICR_TYPER U(0x08) #define GICR_WAKER U(0x14) #define GICR_PROPBASER U(0x70) |