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| author | Isla Mitchell <isla.mitchell@arm.com> | 2017-08-03 16:04:46 +0100 |
|---|---|---|
| committer | Dimitris Papastamos <dimitris.papastamos@arm.com> | 2018-06-08 11:46:31 +0100 |
| commit | abbffe98ed6a2fff519cc5590b947c9751cdd235 (patch) | |
| tree | cd1ae3e842ec710aea062db755cbf7e58776bab0 /include | |
| parent | 83685de911a7a5372a01d656d4cf434c27313426 (diff) | |
| download | platform_external_arm-trusted-firmware-abbffe98ed6a2fff519cc5590b947c9751cdd235.tar.gz platform_external_arm-trusted-firmware-abbffe98ed6a2fff519cc5590b947c9751cdd235.tar.bz2 platform_external_arm-trusted-firmware-abbffe98ed6a2fff519cc5590b947c9751cdd235.zip | |
Add support for Cortex-Ares and Cortex-A76 CPUs
Both Cortex-Ares and Cortex-A76 CPUs use the ARM DynamIQ Shared Unit
(DSU). The power-down and power-up sequences are therefore mostly
managed in hardware, and required software operations are simple.
Change-Id: I3a9447b5bdbdbc5ed845b20f6564d086516fa161
Signed-off-by: Isla Mitchell <isla.mitchell@arm.com>
Diffstat (limited to 'include')
| -rw-r--r-- | include/lib/cpus/aarch64/cortex_a76.h | 22 | ||||
| -rw-r--r-- | include/lib/cpus/aarch64/cortex_ares.h | 22 |
2 files changed, 44 insertions, 0 deletions
diff --git a/include/lib/cpus/aarch64/cortex_a76.h b/include/lib/cpus/aarch64/cortex_a76.h new file mode 100644 index 000000000..de6288d8f --- /dev/null +++ b/include/lib/cpus/aarch64/cortex_a76.h @@ -0,0 +1,22 @@ +/* + * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef __CORTEX_A76_H__ +#define __CORTEX_A76_H__ + +/* Cortex-A76 MIDR for revision 0 */ +#define CORTEX_A76_MIDR 0x410fd0b0 + +/******************************************************************************* + * CPU Extended Control register specific definitions. + ******************************************************************************/ +#define CORTEX_A76_CPUPWRCTLR_EL1 S3_0_C15_C2_7 +#define CORTEX_A76_CPUECTLR_EL1 S3_0_C15_C1_4 + +/* Definitions of register field mask in CORTEX_A76_CPUPWRCTLR_EL1 */ +#define CORTEX_A76_CORE_PWRDN_EN_MASK 0x1 + +#endif /* __CORTEX_A76_H__ */ diff --git a/include/lib/cpus/aarch64/cortex_ares.h b/include/lib/cpus/aarch64/cortex_ares.h new file mode 100644 index 000000000..680811cf2 --- /dev/null +++ b/include/lib/cpus/aarch64/cortex_ares.h @@ -0,0 +1,22 @@ +/* + * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef __CORTEX_ARES_H__ +#define __CORTEX_ARES_H__ + +/* Cortex-ARES MIDR for revision 0 */ +#define CORTEX_ARES_MIDR 0x410fd0c0 + +/******************************************************************************* + * CPU Extended Control register specific definitions. + ******************************************************************************/ +#define CORTEX_ARES_CPUPWRCTLR_EL1 S3_0_C15_C2_7 +#define CORTEX_ARES_CPUECTLR_EL1 S3_0_C15_C1_4 + +/* Definitions of register field mask in CORTEX_ARES_CPUPWRCTLR_EL1 */ +#define CORTEX_ARES_CORE_PWRDN_EN_MASK 0x1 + +#endif /* __CORTEX_ARES_H__ */ |