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| author | Soby Mathew <soby.mathew@arm.com> | 2019-10-03 13:43:51 +0000 |
|---|---|---|
| committer | TrustedFirmware Code Review <review@review.trustedfirmware.org> | 2019-10-03 13:43:51 +0000 |
| commit | 8326aad7be972a66e6fbcc4b1128929fec0cb242 (patch) | |
| tree | 424d6a1b5bcd1320b0b6971b3f52253fc0975277 /include | |
| parent | 2d35bc1386ee80904be0df7dd5b3eb958dc685e2 (diff) | |
| parent | 78f02ae2968dd0a78e0e686f8cf0886fa296f4eb (diff) | |
| download | platform_external_arm-trusted-firmware-8326aad7be972a66e6fbcc4b1128929fec0cb242.tar.gz platform_external_arm-trusted-firmware-8326aad7be972a66e6fbcc4b1128929fec0cb242.tar.bz2 platform_external_arm-trusted-firmware-8326aad7be972a66e6fbcc4b1128929fec0cb242.zip | |
Merge "Introducing support for Cortex-A65AE" into integration
Diffstat (limited to 'include')
| -rw-r--r-- | include/lib/cpus/aarch64/cortex_a65ae.h | 31 |
1 files changed, 31 insertions, 0 deletions
diff --git a/include/lib/cpus/aarch64/cortex_a65ae.h b/include/lib/cpus/aarch64/cortex_a65ae.h new file mode 100644 index 000000000..bd4a881a3 --- /dev/null +++ b/include/lib/cpus/aarch64/cortex_a65ae.h @@ -0,0 +1,31 @@ +/* + * Copyright (c) 2019, Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef CORTEX_A65AE_H +#define CORTEX_A65AE_H + +#include <lib/utils_def.h> + +#define CORTEX_A65AE_MIDR U(0x410FD430) + +/******************************************************************************* + * CPU Extended Control register specific definitions + ******************************************************************************/ +#define CORTEX_A65AE_ECTLR_EL1 S3_0_C15_C1_4 + +/******************************************************************************* + * CPU Auxiliary Control register specific definitions + ******************************************************************************/ +#define CORTEX_A65AE_CPUACTLR_EL1 S3_0_C15_C1_0 + +/******************************************************************************* + * CPU Power Control register specific definitions + ******************************************************************************/ + +#define CORTEX_A65AE_CPUPWRCTLR_EL1 S3_0_C15_C2_7 +#define CORTEX_A65AE_CPUPWRCTLR_EL1_CORE_PWRDN_BIT (U(1) << 0) + +#endif /* CORTEX_A65AE_H */ |