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| author | Ambroise Vincent <ambroise.vincent@arm.com> | 2019-03-05 09:54:21 +0000 |
|---|---|---|
| committer | Ambroise Vincent <ambroise.vincent@arm.com> | 2019-03-13 14:05:47 +0000 |
| commit | 5f2c690d0ea92e31cbe9d450f36fc7cbb39a9b23 (patch) | |
| tree | d5918159a05a43b97db0777f4267c4248082a000 /include | |
| parent | 75a1ada95efa78e4133bdd947c64944005a8e5c2 (diff) | |
| download | platform_external_arm-trusted-firmware-5f2c690d0ea92e31cbe9d450f36fc7cbb39a9b23.tar.gz platform_external_arm-trusted-firmware-5f2c690d0ea92e31cbe9d450f36fc7cbb39a9b23.tar.bz2 platform_external_arm-trusted-firmware-5f2c690d0ea92e31cbe9d450f36fc7cbb39a9b23.zip | |
Cortex-A15: Implement workaround for errata 827671
This erratum can only be worked around on revisions >= r3p0 because the
register that needs to be accessed only exists in those revisions[1].
[1] http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0438g/CIHEAAAD.html
Change-Id: I5d773547d7a09b5bd01dabcd19ceeaf53c186faa
Signed-off-by: Ambroise Vincent <ambroise.vincent@arm.com>
Diffstat (limited to 'include')
| -rw-r--r-- | include/lib/cpus/aarch32/cortex_a15.h | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/include/lib/cpus/aarch32/cortex_a15.h b/include/lib/cpus/aarch32/cortex_a15.h index 957afbdb4..9526a9cef 100644 --- a/include/lib/cpus/aarch32/cortex_a15.h +++ b/include/lib/cpus/aarch32/cortex_a15.h @@ -10,6 +10,13 @@ #include <lib/utils_def.h> /******************************************************************************* + * Auxiliary Control Register 2 specific definitions. + ******************************************************************************/ +#define CORTEX_A15_ACTLR2 p15, 1, c15, c0, 4 + +#define CORTEX_A15_ACTLR2_INV_DCC_BIT (U(1) << 0) + +/******************************************************************************* * Cortex-A15 midr with version/revision set to 0 ******************************************************************************/ #define CORTEX_A15_MIDR U(0x410FC0F0) |