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| author | Louis Mayencourt <louis.mayencourt@arm.com> | 2019-04-09 14:11:06 +0100 |
|---|---|---|
| committer | Louis Mayencourt <louis.mayencourt@arm.com> | 2019-04-17 13:46:43 +0100 |
| commit | 2c3b76ce7b9e36e5c8be3c454110e070a20332ca (patch) | |
| tree | 040ca3fdf334a631e7d085a20e87c334c18473b9 /include | |
| parent | cba71b70ef7070bcd38a8d202f30e58f79e36c6b (diff) | |
| download | platform_external_arm-trusted-firmware-2c3b76ce7b9e36e5c8be3c454110e070a20332ca.tar.gz platform_external_arm-trusted-firmware-2c3b76ce7b9e36e5c8be3c454110e070a20332ca.tar.bz2 platform_external_arm-trusted-firmware-2c3b76ce7b9e36e5c8be3c454110e070a20332ca.zip | |
DSU: Small fix and reformat on errata framework
Change-Id: I50708f6ccc33059fbfe6d36fd66351f0b894311f
Signed-off-by: Louis Mayencourt <louis.mayencourt@arm.com>
Diffstat (limited to 'include')
| -rw-r--r-- | include/lib/cpus/aarch64/dsu_def.h | 18 |
1 files changed, 12 insertions, 6 deletions
diff --git a/include/lib/cpus/aarch64/dsu_def.h b/include/lib/cpus/aarch64/dsu_def.h index b7ba28a4a..4ec64eee3 100644 --- a/include/lib/cpus/aarch64/dsu_def.h +++ b/include/lib/cpus/aarch64/dsu_def.h @@ -10,23 +10,29 @@ #include <lib/utils_def.h> /******************************************************************** - * DSU control registers definitions * + * DSU Cluster Configuration registers definitions ********************************************************************/ #define CLUSTERCFR_EL1 S3_0_C15_C3_0 -#define CLUSTERIDR_EL1 S3_0_C15_C3_1 -#define CLUSTERACTLR_EL1 S3_0_C15_C3_3 + +#define CLUSTERCFR_ACP_SHIFT U(11) /******************************************************************** - * DSU control registers bit fields * + * DSU Cluster Main Revision ID registers definitions ********************************************************************/ +#define CLUSTERIDR_EL1 S3_0_C15_C3_1 + #define CLUSTERIDR_REV_SHIFT U(0) #define CLUSTERIDR_REV_BITS U(4) #define CLUSTERIDR_VAR_SHIFT U(4) #define CLUSTERIDR_VAR_BITS U(4) -#define CLUSTERCFR_ACP_SHIFT U(11) /******************************************************************** - * Masks applied for DSU errata workarounds * + * DSU Cluster Auxiliary Control registers definitions + ********************************************************************/ +#define CLUSTERACTLR_EL1 S3_0_C15_C3_3 + +/******************************************************************** + * Masks applied for DSU errata workarounds ********************************************************************/ #define DSU_ERRATA_936184_MASK (U(0x3) << 15) |