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| author | Pramod Kumar <pramod.kumar@broadcom.com> | 2020-02-19 10:39:10 +0530 |
|---|---|---|
| committer | Pramod Kumar <pramod.kumar@broadcom.com> | 2020-04-03 17:31:24 +0530 |
| commit | 06aca857f4a8ceae4f2ec126b8a9892b82077415 (patch) | |
| tree | 8b2ecfa0c75ec49fbb116851706adb46d5f9ec35 /include | |
| parent | 33f1dd9c199fc739a5a9aaa669eb9c5c7c913f09 (diff) | |
| download | platform_external_arm-trusted-firmware-06aca857f4a8ceae4f2ec126b8a9892b82077415.tar.gz platform_external_arm-trusted-firmware-06aca857f4a8ceae4f2ec126b8a9892b82077415.tar.bz2 platform_external_arm-trusted-firmware-06aca857f4a8ceae4f2ec126b8a9892b82077415.zip | |
xlat lib v2: Add support to pass shareability attribute for normal memory region
Present framework restricts platform to pass desired shareability attribute
for normal memory region mapped in MMU. it defaults to inner shareability.
There are platforms where memories (like SRAM) are not placed at snoopable
region in advaned interconnect like CCN/CMN hence snoopable transaction is
not possible to these memory. Though These memories could be mapped in MMU
as MT_NON_CACHEABLE, data caches benefits won't be available.
If these memories are mapped as cacheable with non-shareable attribute,
when only one core is running like at boot time, MMU data cached could be
used for faster execution. Hence adding support to pass the shareability
attribute for memory regions.
Signed-off-by: Pramod Kumar <pramod.kumar@broadcom.com>
Change-Id: I678cb50120a28dae4aa9d1896e8faf1dd5cf1754
Diffstat (limited to 'include')
| -rw-r--r-- | include/lib/xlat_tables/xlat_tables_v2.h | 17 |
1 files changed, 17 insertions, 0 deletions
diff --git a/include/lib/xlat_tables/xlat_tables_v2.h b/include/lib/xlat_tables/xlat_tables_v2.h index 9fe4a6e8a..8eb84a892 100644 --- a/include/lib/xlat_tables/xlat_tables_v2.h +++ b/include/lib/xlat_tables/xlat_tables_v2.h @@ -66,6 +66,11 @@ #define MT_EXECUTE_SHIFT U(5) /* In the EL1&0 translation regime, User (EL0) or Privileged (EL1). */ #define MT_USER_SHIFT U(6) + +/* Shareability attribute for the memory region */ +#define MT_SHAREABILITY_SHIFT U(7) +#define MT_SHAREABILITY_MASK (U(3) << MT_SHAREABILITY_SHIFT) +#define MT_SHAREABILITY(_attr) ((_attr) & MT_SHAREABILITY_MASK) /* All other bits are reserved */ /* @@ -106,6 +111,18 @@ #define MT_USER (U(1) << MT_USER_SHIFT) #define MT_PRIVILEGED (U(0) << MT_USER_SHIFT) +/* + * Shareability defines the visibility of any cache changes to + * all masters belonging to a shareable domain. + * + * MT_SHAREABILITY_ISH: For inner shareable domain + * MT_SHAREABILITY_OSH: For outer shareable domain + * MT_SHAREABILITY_NSH: For non shareable domain + */ +#define MT_SHAREABILITY_ISH (U(1) << MT_SHAREABILITY_SHIFT) +#define MT_SHAREABILITY_OSH (U(2) << MT_SHAREABILITY_SHIFT) +#define MT_SHAREABILITY_NSH (U(3) << MT_SHAREABILITY_SHIFT) + /* Compound attributes for most common usages */ #define MT_CODE (MT_MEMORY | MT_RO | MT_EXECUTE) #define MT_RO_DATA (MT_MEMORY | MT_RO | MT_EXECUTE_NEVER) |