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| author | Alexei Fedorov <Alexei.Fedorov@arm.com> | 2019-08-20 15:22:44 +0100 |
|---|---|---|
| committer | Paul Beesley <paul.beesley@arm.com> | 2019-09-26 15:36:02 +0000 |
| commit | c3e8b0be9bde36d220beea5d0452ecd04dcd94c6 (patch) | |
| tree | 2f5efa0f2fc2f922e19abd9e1eadebc0c8eb8f85 /include/services | |
| parent | 69ef7b7ffe66b64bdffee0a387774e7088022503 (diff) | |
| download | platform_external_arm-trusted-firmware-c3e8b0be9bde36d220beea5d0452ecd04dcd94c6.tar.gz platform_external_arm-trusted-firmware-c3e8b0be9bde36d220beea5d0452ecd04dcd94c6.tar.bz2 platform_external_arm-trusted-firmware-c3e8b0be9bde36d220beea5d0452ecd04dcd94c6.zip | |
AArch32: Disable Secure Cycle Counter
This patch changes implementation for disabling Secure Cycle
Counter. For ARMv8.5 the counter gets disabled by setting
SDCR.SCCD bit on CPU cold/warm boot. For the earlier
architectures PMCR register is saved/restored on secure
world entry/exit from/to Non-secure state, and cycle counting
gets disabled by setting PMCR.DP bit.
In 'include\aarch32\arch.h' header file new
ARMv8.5-PMU related definitions were added.
Change-Id: Ia8845db2ebe8de940d66dff479225a5b879316f8
Signed-off-by: Alexei Fedorov <Alexei.Fedorov@arm.com>
Diffstat (limited to 'include/services')
0 files changed, 0 insertions, 0 deletions