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author | Jimmy Brisson <jimmy.brisson@arm.com> | 2020-08-04 16:18:52 -0500 |
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committer | laurenw-arm <lauren.wehrmeister@arm.com> | 2020-10-12 10:55:03 -0500 |
commit | d7b5f40823d449cc79e6440174390997cf11a9d9 (patch) | |
tree | 631affeb74091069edf06596f83fbe37864942c3 /include/lib | |
parent | 7ad39818b184850d263008e7d36ba16adf72a669 (diff) | |
download | platform_external_arm-trusted-firmware-d7b5f40823d449cc79e6440174390997cf11a9d9.tar.gz platform_external_arm-trusted-firmware-d7b5f40823d449cc79e6440174390997cf11a9d9.tar.bz2 platform_external_arm-trusted-firmware-d7b5f40823d449cc79e6440174390997cf11a9d9.zip |
Increase type widths to satisfy width requirements
Usually, C has no problem up-converting types to larger bit sizes. MISRA
rule 10.7 requires that you not do this, or be very explicit about this.
This resolves the following required rule:
bl1/aarch64/bl1_context_mgmt.c:81:[MISRA C-2012 Rule 10.7 (required)]<None>
The width of the composite expression "0U | ((mode & 3U) << 2U) | 1U |
0x3c0U" (32 bits) is less that the right hand operand
"18446744073709547519ULL" (64 bits).
This also resolves MISRA defects such as:
bl2/aarch64/bl2arch_setup.c:18:[MISRA C-2012 Rule 12.2 (required)]
In the expression "3U << 20", shifting more than 7 bits, the number
of bits in the essential type of the left expression, "3U", is
not allowed.
Further, MISRA requires that all shifts don't overflow. The definition of
PAGE_SIZE was (1U << 12), and 1U is 8 bits. This caused about 50 issues.
This fixes the violation by changing the definition to 1UL << 12. Since
this uses 32bits, it should not create any issues for aarch32.
This patch also contains a fix for a build failure in the sun50i_a64
platform. Specifically, these misra fixes removed a single and
instruction,
92407e73 and x19, x19, #0xffffffff
from the cm_setup_context function caused a relocation in
psci_cpus_on_start to require a linker-generated stub. This increased the
size of the .text section and caused an alignment later on to go over a
page boundary and round up to the end of RAM before placing the .data
section. This sectionn is of non-zero size and therefore causes a link
error.
The fix included in this reorders the functions during link time
without changing their ording with respect to alignment.
Change-Id: I76b4b662c3d262296728a8b9aab7a33b02087f16
Signed-off-by: Jimmy Brisson <jimmy.brisson@arm.com>
Diffstat (limited to 'include/lib')
-rw-r--r-- | include/lib/pmf/pmf.h | 10 | ||||
-rw-r--r-- | include/lib/pmf/pmf_helpers.h | 16 | ||||
-rw-r--r-- | include/lib/smccc.h | 7 | ||||
-rw-r--r-- | include/lib/xlat_tables/xlat_tables_defs.h | 6 |
4 files changed, 21 insertions, 18 deletions
diff --git a/include/lib/pmf/pmf.h b/include/lib/pmf/pmf.h index 3fc8e3863..fa990d2e5 100644 --- a/include/lib/pmf/pmf.h +++ b/include/lib/pmf/pmf.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2016-2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2016-2020, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -14,13 +14,13 @@ /* * Constants used for/by PMF services. */ -#define PMF_ARM_TIF_IMPL_ID U(0x41) +#define PMF_ARM_TIF_IMPL_ID UL(0x41) #define PMF_TID_SHIFT 0 -#define PMF_TID_MASK (U(0xFF) << PMF_TID_SHIFT) +#define PMF_TID_MASK (UL(0xFF) << PMF_TID_SHIFT) #define PMF_SVC_ID_SHIFT 10 -#define PMF_SVC_ID_MASK (U(0x3F) << PMF_SVC_ID_SHIFT) +#define PMF_SVC_ID_MASK (UL(0x3F) << PMF_SVC_ID_SHIFT) #define PMF_IMPL_ID_SHIFT 24 -#define PMF_IMPL_ID_MASK (U(0xFF) << PMF_IMPL_ID_SHIFT) +#define PMF_IMPL_ID_MASK (UL(0xFF) << PMF_IMPL_ID_SHIFT) /* * Flags passed to PMF_REGISTER_SERVICE diff --git a/include/lib/pmf/pmf_helpers.h b/include/lib/pmf/pmf_helpers.h index cfb27f7dc..b49c6da09 100644 --- a/include/lib/pmf/pmf_helpers.h +++ b/include/lib/pmf/pmf_helpers.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2016-2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2016-2020, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -174,24 +174,26 @@ typedef struct pmf_svc_desc { unsigned long long ts) \ { \ CASSERT(_flags != 0, select_proper_config); \ - PMF_VALIDATE_TID(_name, tid); \ + PMF_VALIDATE_TID(_name, (uint64_t)tid); \ uintptr_t base_addr = (uintptr_t) pmf_ts_mem_ ## _name; \ if (((_flags) & PMF_STORE_ENABLE) != 0) \ - __pmf_store_timestamp(base_addr, tid, ts); \ + __pmf_store_timestamp(base_addr, \ + (uint64_t)tid, ts); \ if (((_flags) & PMF_DUMP_ENABLE) != 0) \ - __pmf_dump_timestamp(tid, ts); \ + __pmf_dump_timestamp((uint64_t)tid, ts); \ } \ void pmf_capture_timestamp_with_cache_maint_ ## _name( \ unsigned int tid, \ unsigned long long ts) \ { \ CASSERT(_flags != 0, select_proper_config); \ - PMF_VALIDATE_TID(_name, tid); \ + PMF_VALIDATE_TID(_name, (uint64_t)tid); \ uintptr_t base_addr = (uintptr_t) pmf_ts_mem_ ## _name; \ if (((_flags) & PMF_STORE_ENABLE) != 0) \ - __pmf_store_timestamp_with_cache_maint(base_addr, tid, ts);\ + __pmf_store_timestamp_with_cache_maint( \ + base_addr, (uint64_t)tid, ts); \ if (((_flags) & PMF_DUMP_ENABLE) != 0) \ - __pmf_dump_timestamp(tid, ts); \ + __pmf_dump_timestamp((uint64_t)tid, ts); \ } /* diff --git a/include/lib/smccc.h b/include/lib/smccc.h index 366f0560b..470317dd0 100644 --- a/include/lib/smccc.h +++ b/include/lib/smccc.h @@ -78,8 +78,8 @@ #define SMC_64 U(1) #define SMC_32 U(0) -#define SMC_TYPE_FAST ULL(1) -#define SMC_TYPE_YIELD ULL(0) +#define SMC_TYPE_FAST UL(1) +#define SMC_TYPE_YIELD UL(0) #define SMC_OK ULL(0) #define SMC_UNK -1 @@ -112,7 +112,8 @@ /* The macro below is used to identify a valid Fast SMC call */ #define is_valid_fast_smc(_fid) ((!(((_fid) >> 16) & U(0xff))) && \ - (GET_SMC_TYPE(_fid) == SMC_TYPE_FAST)) + (GET_SMC_TYPE(_fid) \ + == (uint32_t)SMC_TYPE_FAST)) /* * Macro to define UUID for services. Apart from defining and initializing a diff --git a/include/lib/xlat_tables/xlat_tables_defs.h b/include/lib/xlat_tables/xlat_tables_defs.h index 76cfc0b34..579d8d89c 100644 --- a/include/lib/xlat_tables/xlat_tables_defs.h +++ b/include/lib/xlat_tables/xlat_tables_defs.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2017-2020, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -74,8 +74,8 @@ * 64KB. However, only 4KB are supported at the moment. */ #define PAGE_SIZE_SHIFT FOUR_KB_SHIFT -#define PAGE_SIZE (U(1) << PAGE_SIZE_SHIFT) -#define PAGE_SIZE_MASK (PAGE_SIZE - U(1)) +#define PAGE_SIZE (UL(1) << PAGE_SIZE_SHIFT) +#define PAGE_SIZE_MASK (PAGE_SIZE - UL(1)) #define IS_PAGE_ALIGNED(addr) (((addr) & PAGE_SIZE_MASK) == U(0)) #if (ARM_ARCH_MAJOR == 7) && !ARMV7_SUPPORTS_LARGE_PAGE_ADDRESSING |