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| author | Etienne Carriere <etienne.carriere@linaro.org> | 2017-11-05 22:56:41 +0100 |
|---|---|---|
| committer | Etienne Carriere <etienne.carriere@linaro.org> | 2017-11-08 13:49:52 +0100 |
| commit | 778e411dc9b98897aec3ad4989f4fa4e8e0c4fdf (patch) | |
| tree | 6c0a09ac406b9afd4b8baf4cfd70801215c35196 /include/lib | |
| parent | 6ff43c26395bb74a07e0572a61f618868837bc22 (diff) | |
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ARMv7: introduce Cortex-A17
Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
Diffstat (limited to 'include/lib')
| -rw-r--r-- | include/lib/cpus/aarch32/cortex_a17.h | 20 |
1 files changed, 20 insertions, 0 deletions
diff --git a/include/lib/cpus/aarch32/cortex_a17.h b/include/lib/cpus/aarch32/cortex_a17.h new file mode 100644 index 000000000..d2ca91c41 --- /dev/null +++ b/include/lib/cpus/aarch32/cortex_a17.h @@ -0,0 +1,20 @@ +/* + * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef __CORTEX_A17_H__ +#define __CORTEX_A17_H__ + +/******************************************************************************* + * Cortex-A17 midr with version/revision set to 0 + ******************************************************************************/ +#define CORTEX_A17_MIDR 0x410FC0E0 + +/******************************************************************************* + * CPU Auxiliary Control register specific definitions. + ******************************************************************************/ +#define CORTEX_A17_ACTLR_SMP_BIT (1 << 6) + +#endif /* __CORTEX_A17_H__ */ |