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| author | Sathees Balya <sathees.balya@arm.com> | 2018-12-06 13:33:24 +0000 |
|---|---|---|
| committer | Sathees Balya <sathees.balya@arm.com> | 2019-01-03 17:33:09 +0000 |
| commit | 65849aa595fa0fad1e9b9fd13c24d5b756e61aa6 (patch) | |
| tree | 90cb44d6f2694a00718940cede1d8f7fc57efb28 /include/lib | |
| parent | c8765826f4c2d10db0b660defccc84f7bce11af0 (diff) | |
| download | platform_external_arm-trusted-firmware-65849aa595fa0fad1e9b9fd13c24d5b756e61aa6.tar.gz platform_external_arm-trusted-firmware-65849aa595fa0fad1e9b9fd13c24d5b756e61aa6.tar.bz2 platform_external_arm-trusted-firmware-65849aa595fa0fad1e9b9fd13c24d5b756e61aa6.zip | |
Enable DIT if supported
This patch enables the Data Independent Timing
functionality (DIT) in EL3 if supported
by the platform.
Change-Id: Ia527d6aa2ee88a9a9fe1c941220404b9ff5567e5
Signed-off-by: Sathees Balya <sathees.balya@arm.com>
Diffstat (limited to 'include/lib')
| -rw-r--r-- | include/lib/aarch32/arch.h | 9 | ||||
| -rw-r--r-- | include/lib/aarch64/arch.h | 14 |
2 files changed, 20 insertions, 3 deletions
diff --git a/include/lib/aarch32/arch.h b/include/lib/aarch32/arch.h index fa6e5dbdd..8260c5491 100644 --- a/include/lib/aarch32/arch.h +++ b/include/lib/aarch32/arch.h @@ -94,11 +94,17 @@ /* CSSELR definitions */ #define LEVEL_SHIFT U(1) -/* ID_PFR0 definitions */ +/* ID_PFR0 AMU definitions */ #define ID_PFR0_AMU_SHIFT U(20) #define ID_PFR0_AMU_LENGTH U(4) #define ID_PFR0_AMU_MASK U(0xf) +/* ID_PFR0 DIT definitions */ +#define ID_PFR0_DIT_SHIFT U(24) +#define ID_PFR0_DIT_LENGTH U(4) +#define ID_PFR0_DIT_MASK U(0xf) +#define ID_PFR0_DIT_SUPPORTED (U(1) << ID_PFR0_DIT_SHIFT) + /* ID_PFR1 definitions */ #define ID_PFR1_VIRTEXT_SHIFT U(12) #define ID_PFR1_VIRTEXT_MASK U(0xf) @@ -276,6 +282,7 @@ #define DISABLE_ALL_EXCEPTIONS \ (SPSR_FIQ_BIT | SPSR_IRQ_BIT | SPSR_ABT_BIT) +#define CPSR_DIT_BIT (U(1) << 21) /* * TTBCR definitions */ diff --git a/include/lib/aarch64/arch.h b/include/lib/aarch64/arch.h index 6f81e1b41..72a14dcfa 100644 --- a/include/lib/aarch64/arch.h +++ b/include/lib/aarch64/arch.h @@ -135,6 +135,10 @@ #define ID_AA64PFR0_SVE_LENGTH U(4) #define ID_AA64PFR0_MPAM_SHIFT U(40) #define ID_AA64PFR0_MPAM_MASK ULL(0xf) +#define ID_AA64PFR0_DIT_SHIFT U(48) +#define ID_AA64PFR0_DIT_MASK ULL(0xf) +#define ID_AA64PFR0_DIT_LENGTH U(4) +#define ID_AA64PFR0_DIT_SUPPORTED U(1) #define ID_AA64PFR0_CSV2_SHIFT U(56) #define ID_AA64PFR0_CSV2_MASK ULL(0xf) #define ID_AA64PFR0_CSV2_LENGTH U(4) @@ -778,7 +782,7 @@ /******************************************************************************* * RAS system registers - *******************************************************************************/ + ******************************************************************************/ #define DISR_EL1 S3_0_C12_C1_1 #define DISR_A_BIT U(31) @@ -807,7 +811,13 @@ /******************************************************************************* * Armv8.3 Pointer Authentication Registers - *******************************************************************************/ + ******************************************************************************/ #define APGAKeyLo_EL1 S3_0_C2_C3_0 +/******************************************************************************* + * Armv8.4 Data Independent Timing Registers + ******************************************************************************/ +#define DIT S3_3_C4_C2_5 +#define DIT_BIT BIT(24) + #endif /* ARCH_H */ |