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| author | Antonio Niño Díaz <antonio.ninodiaz@arm.com> | 2019-03-01 09:17:27 +0000 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2019-03-01 09:17:27 +0000 |
| commit | 4476838ae8c03087c4172de393a9c7c8b13dc393 (patch) | |
| tree | 798887031ee2d792af9cc5bc3a111eb86e1475bd /include/lib | |
| parent | 82842004f6854d0889840b9886ea75d2e7adb315 (diff) | |
| parent | d6bf24dc49ca86102340264903e34d85dec1df63 (diff) | |
| download | platform_external_arm-trusted-firmware-4476838ae8c03087c4172de393a9c7c8b13dc393.tar.gz platform_external_arm-trusted-firmware-4476838ae8c03087c4172de393a9c7c8b13dc393.tar.bz2 platform_external_arm-trusted-firmware-4476838ae8c03087c4172de393a9c7c8b13dc393.zip | |
Merge pull request #1845 from ambroise-arm/av/errata
Apply workarounds for errata of Cortex-A53, A55 and A57
Diffstat (limited to 'include/lib')
| -rw-r--r-- | include/lib/cpus/aarch32/cortex_a57.h | 1 | ||||
| -rw-r--r-- | include/lib/cpus/aarch64/cortex_a55.h | 18 | ||||
| -rw-r--r-- | include/lib/cpus/aarch64/cortex_a57.h | 1 |
3 files changed, 20 insertions, 0 deletions
diff --git a/include/lib/cpus/aarch32/cortex_a57.h b/include/lib/cpus/aarch32/cortex_a57.h index f7005da3e..ffabd61ac 100644 --- a/include/lib/cpus/aarch32/cortex_a57.h +++ b/include/lib/cpus/aarch32/cortex_a57.h @@ -45,6 +45,7 @@ #define CORTEX_A57_CPUACTLR p15, 0, c15 #define CORTEX_A57_CPUACTLR_DIS_LOAD_PASS_DMB (ULL(1) << 59) +#define CORTEX_A57_CPUACTLR_DIS_DMB_NULLIFICATION (ULL(1) << 58) #define CORTEX_A57_CPUACTLR_DIS_LOAD_PASS_STORE (ULL(1) << 55) #define CORTEX_A57_CPUACTLR_GRE_NGRE_AS_NGNRE (ULL(1) << 54) #define CORTEX_A57_CPUACTLR_DIS_OVERREAD (ULL(1) << 52) diff --git a/include/lib/cpus/aarch64/cortex_a55.h b/include/lib/cpus/aarch64/cortex_a55.h index 8b21e16a1..feac1d2f0 100644 --- a/include/lib/cpus/aarch64/cortex_a55.h +++ b/include/lib/cpus/aarch64/cortex_a55.h @@ -18,6 +18,24 @@ #define CORTEX_A55_CPUPWRCTLR_EL1 S3_0_C15_C2_7 #define CORTEX_A55_CPUECTLR_EL1 S3_0_C15_C1_4 +#define CORTEX_A55_CPUECTLR_EL1_L1WSCTL (ULL(3) << 25) + +/******************************************************************************* + * CPU Auxiliary Control register specific definitions. + ******************************************************************************/ +#define CORTEX_A55_CPUACTLR_EL1 S3_0_C15_C1_0 + +#define CORTEX_A55_CPUACTLR_EL1_DISABLE_WRITE_STREAMING (ULL(1) << 24) +#define CORTEX_A55_CPUACTLR_EL1_DISABLE_DUAL_ISSUE (ULL(1) << 31) +#define CORTEX_A55_CPUACTLR_EL1_DISABLE_L1_PAGEWALKS (ULL(1) << 49) + +/******************************************************************************* + * CPU Identification register specific definitions. + ******************************************************************************/ +#define CORTEX_A55_CLIDR_EL1 S3_1_C0_C0_1 + +#define CORTEX_A55_CLIDR_EL1_CTYPE3 (ULL(7) << 6) + /* Definitions of register field mask in CORTEX_A55_CPUPWRCTLR_EL1 */ #define CORTEX_A55_CORE_PWRDN_EN_MASK U(0x1) diff --git a/include/lib/cpus/aarch64/cortex_a57.h b/include/lib/cpus/aarch64/cortex_a57.h index 1e68f21a4..102ff60c3 100644 --- a/include/lib/cpus/aarch64/cortex_a57.h +++ b/include/lib/cpus/aarch64/cortex_a57.h @@ -45,6 +45,7 @@ #define CORTEX_A57_CPUACTLR_EL1 S3_1_C15_C2_0 #define CORTEX_A57_CPUACTLR_EL1_DIS_LOAD_PASS_DMB (ULL(1) << 59) +#define CORTEX_A57_CPUACTLR_EL1_DIS_DMB_NULLIFICATION (ULL(1) << 58) #define CORTEX_A57_CPUACTLR_EL1_DIS_LOAD_PASS_STORE (ULL(1) << 55) #define CORTEX_A57_CPUACTLR_EL1_GRE_NGRE_AS_NGNRE (ULL(1) << 54) #define CORTEX_A57_CPUACTLR_EL1_DIS_OVERREAD (ULL(1) << 52) |