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| author | Ambroise Vincent <ambroise.vincent@arm.com> | 2019-02-21 16:20:43 +0000 |
|---|---|---|
| committer | Ambroise Vincent <ambroise.vincent@arm.com> | 2019-02-28 09:56:58 +0000 |
| commit | 1afeee92751840e4352201c9b3e99056a6fe5c9d (patch) | |
| tree | ba36576433a40d7f040b2bf33c4c767b4eb2dea9 /include/lib | |
| parent | 1baa28bb2dc79f23c550d67604324afd222221c3 (diff) | |
| download | platform_external_arm-trusted-firmware-1afeee92751840e4352201c9b3e99056a6fe5c9d.tar.gz platform_external_arm-trusted-firmware-1afeee92751840e4352201c9b3e99056a6fe5c9d.tar.bz2 platform_external_arm-trusted-firmware-1afeee92751840e4352201c9b3e99056a6fe5c9d.zip | |
Cortex-A55: Implement workaround for erratum 768277
Change-Id: Iebd45ef5e39ee7080235fb85414ce5b2e776f90c
Signed-off-by: Ambroise Vincent <ambroise.vincent@arm.com>
Diffstat (limited to 'include/lib')
| -rw-r--r-- | include/lib/cpus/aarch64/cortex_a55.h | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/include/lib/cpus/aarch64/cortex_a55.h b/include/lib/cpus/aarch64/cortex_a55.h index 8b21e16a1..5db0f008f 100644 --- a/include/lib/cpus/aarch64/cortex_a55.h +++ b/include/lib/cpus/aarch64/cortex_a55.h @@ -18,6 +18,13 @@ #define CORTEX_A55_CPUPWRCTLR_EL1 S3_0_C15_C2_7 #define CORTEX_A55_CPUECTLR_EL1 S3_0_C15_C1_4 +/******************************************************************************* + * CPU Auxiliary Control register specific definitions. + ******************************************************************************/ +#define CORTEX_A55_CPUACTLR_EL1 S3_0_C15_C1_0 + +#define CORTEX_A55_CPUACTLR_EL1_DISABLE_DUAL_ISSUE (ULL(1) << 31) + /* Definitions of register field mask in CORTEX_A55_CPUPWRCTLR_EL1 */ #define CORTEX_A55_CORE_PWRDN_EN_MASK U(0x1) |