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| author | Yann Gautier <yann.gautier@st.com> | 2019-02-15 17:33:27 +0100 |
|---|---|---|
| committer | Yann Gautier <yann.gautier@st.com> | 2019-02-20 17:34:21 +0100 |
| commit | b053a22e8a538d3ee6114c0ce7f25fa49f0302d8 (patch) | |
| tree | f8818474819c18d8dc75d9c36289deeb386be285 /include/drivers/st | |
| parent | 774b4a8190ccb73d9c9deefba0c0fd3878be55ce (diff) | |
| download | platform_external_arm-trusted-firmware-b053a22e8a538d3ee6114c0ce7f25fa49f0302d8.tar.gz platform_external_arm-trusted-firmware-b053a22e8a538d3ee6114c0ce7f25fa49f0302d8.tar.bz2 platform_external_arm-trusted-firmware-b053a22e8a538d3ee6114c0ce7f25fa49f0302d8.zip | |
stm32mp1: add minimal support for co-processor Cortex-M4
STM32MP1 chip embeds a dual Cortex-A7 and a Cortex-M4.
The support for Cortex-M4 clocks is added when configuring the clock tree.
Some minimal security features to allow communications between A7 and M4
are also added.
Change-Id: I60417e244a476f60a2758f4969700b2684056665
Signed-off-by: Yann Gautier <yann.gautier@st.com>
Diffstat (limited to 'include/drivers/st')
| -rw-r--r-- | include/drivers/st/stm32mp1_clk.h | 1 | ||||
| -rw-r--r-- | include/drivers/st/stm32mp1_rcc.h | 4 |
2 files changed, 5 insertions, 0 deletions
diff --git a/include/drivers/st/stm32mp1_clk.h b/include/drivers/st/stm32mp1_clk.h index 1e0d949ac..7afa5ad84 100644 --- a/include/drivers/st/stm32mp1_clk.h +++ b/include/drivers/st/stm32mp1_clk.h @@ -13,6 +13,7 @@ int stm32mp1_clk_probe(void); int stm32mp1_clk_init(void); bool stm32mp1_rcc_is_secure(void); +bool stm32mp1_rcc_is_mckprot(void); void __stm32mp1_clk_enable(unsigned long id, bool caller_is_secure); void __stm32mp1_clk_disable(unsigned long id, bool caller_is_secure); diff --git a/include/drivers/st/stm32mp1_rcc.h b/include/drivers/st/stm32mp1_rcc.h index 1922c4815..eaa853da3 100644 --- a/include/drivers/st/stm32mp1_rcc.h +++ b/include/drivers/st/stm32mp1_rcc.h @@ -111,6 +111,7 @@ #define RCC_RCK4SELR U(0x824) #define RCC_TIMG1PRER U(0x828) #define RCC_TIMG2PRER U(0x82C) +#define RCC_MCUDIVR U(0x830) #define RCC_APB1DIVR U(0x834) #define RCC_APB2DIVR U(0x838) #define RCC_APB3DIVR U(0x83C) @@ -237,6 +238,7 @@ /* Values for RCC_TZCR register */ #define RCC_TZCR_TZEN BIT(0) +#define RCC_TZCR_MCKPROT BIT(1) /* Used for most of RCC_<x>SELR registers */ #define RCC_SELR_SRC_MASK GENMASK(2, 0) @@ -273,6 +275,7 @@ #define RCC_APBXDIV_MASK GENMASK(2, 0) #define RCC_MPUDIV_MASK GENMASK(2, 0) #define RCC_AXIDIV_MASK GENMASK(2, 0) +#define RCC_MCUDIV_MASK GENMASK(3, 0) /* Used for TIMER Prescaler */ #define RCC_TIMGXPRER_TIMGXPRE BIT(0) @@ -421,6 +424,7 @@ /* Global Reset Register */ #define RCC_MP_GRSTCSETR_MPSYSRST BIT(0) +#define RCC_MP_GRSTCSETR_MCURST BIT(1) #define RCC_MP_GRSTCSETR_MPUP0RST BIT(4) #define RCC_MP_GRSTCSETR_MPUP1RST BIT(5) |