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| author | johpow01 <john.powell@arm.com> | 2020-10-07 15:08:01 -0500 |
|---|---|---|
| committer | johpow01 <john.powell@arm.com> | 2021-01-13 13:54:18 -0600 |
| commit | 3a2710dcab0dc6dc625f0a4956a44bace1788618 (patch) | |
| tree | c027995bd640eda1c72607dd5c2e468164b9a6d2 /include/common | |
| parent | e26c59d2c968eb0122bf1c333d5ceba534d5fe45 (diff) | |
| download | platform_external_arm-trusted-firmware-3a2710dcab0dc6dc625f0a4956a44bace1788618.tar.gz platform_external_arm-trusted-firmware-3a2710dcab0dc6dc625f0a4956a44bace1788618.tar.bz2 platform_external_arm-trusted-firmware-3a2710dcab0dc6dc625f0a4956a44bace1788618.zip | |
Workaround for Cortex A78 erratum 1951500
Cortex A78 erratum 1951500 is a Cat B erratum that applies to revisions
r0p0, r1p0, and r1p1. The workaround is to insert a DMB ST before
acquire atomic instructions without release semantics. This workaround
works on revisions r1p0 and r1p1, in r0p0 there is no workaround.
SDEN can be found here:
https://documentation-service.arm.com/static/5fb66157ca04df4095c1cc2e
Signed-off-by: John Powell <john.powell@arm.com>
Change-Id: I47610cee75af6a127ea65edc4d5cffc7e6a2d0a3
Diffstat (limited to 'include/common')
0 files changed, 0 insertions, 0 deletions