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| author | Madhukar Pappireddy <madhukar.pappireddy@arm.com> | 2019-10-30 14:24:39 -0500 |
|---|---|---|
| committer | Madhukar Pappireddy <madhukar.pappireddy@arm.com> | 2020-04-15 10:10:24 -0500 |
| commit | 9cf7f355ce8984a4cde970d5f57c913d5247ca6d (patch) | |
| tree | ba6e7d81c58f8ca6d70261e267e4e93c2986d689 /include/arch/aarch32/arch.h | |
| parent | 50d8cf26dc57bb453b1a52be646140bfea4aa591 (diff) | |
| download | platform_external_arm-trusted-firmware-9cf7f355ce8984a4cde970d5f57c913d5247ca6d.tar.gz platform_external_arm-trusted-firmware-9cf7f355ce8984a4cde970d5f57c913d5247ca6d.tar.bz2 platform_external_arm-trusted-firmware-9cf7f355ce8984a4cde970d5f57c913d5247ca6d.zip | |
Provide a hint to power controller for DSU cluster power down
By writing 0 to CLUSTERPWRDN DSU register bit 0, we send an
advisory to the power controller that cluster power is not required
when all cores are powered down.
The AArch32 CLUSTERPWRDN register is architecturally mapped to the
AArch64 CLUSTERPWRDN_EL1 register
Change-Id: Ie6e67c1c7d811fa25c51e2e405ca7f59bd20c81b
Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com>
Diffstat (limited to 'include/arch/aarch32/arch.h')
| -rw-r--r-- | include/arch/aarch32/arch.h | 10 |
1 files changed, 10 insertions, 0 deletions
diff --git a/include/arch/aarch32/arch.h b/include/arch/aarch32/arch.h index 8492b3ea4..a11d55e08 100644 --- a/include/arch/aarch32/arch.h +++ b/include/arch/aarch32/arch.h @@ -701,4 +701,14 @@ #define AMEVTYPER1E p15, 0, c13, c15, 6 #define AMEVTYPER1F p15, 0, c13, c15, 7 +/******************************************************************************* + * Definitions for DynamicIQ Shared Unit registers + ******************************************************************************/ +#define CLUSTERPWRDN p15, 0, c15, c3, 6 + +/* CLUSTERPWRDN register definitions */ +#define DSU_CLUSTER_PWR_OFF 0 +#define DSU_CLUSTER_PWR_ON 1 +#define DSU_CLUSTER_PWR_MASK U(1) + #endif /* ARCH_H */ |