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| author | John Powell <john.powell@arm.com> | 2020-03-20 14:21:05 -0500 |
|---|---|---|
| committer | johpow01 <john.powell@arm.com> | 2020-04-03 16:20:59 -0500 |
| commit | 3443a7027d78a9ccebc6940f0a69300ec7c1ed44 (patch) | |
| tree | 079c29b2f19a0009fdf7dbe2aa6727f920009a93 /include/arch/aarch32/arch.h | |
| parent | 0f99bf32df156b7b87454278b049c65221eeeb84 (diff) | |
| download | platform_external_arm-trusted-firmware-3443a7027d78a9ccebc6940f0a69300ec7c1ed44.tar.gz platform_external_arm-trusted-firmware-3443a7027d78a9ccebc6940f0a69300ec7c1ed44.tar.bz2 platform_external_arm-trusted-firmware-3443a7027d78a9ccebc6940f0a69300ec7c1ed44.zip | |
Fix MISRA C issues in BL1/BL2/BL31
Attempts to address MISRA compliance issues in BL1, BL2, and BL31 code.
Mainly issues like not using boolean expressions in conditionals,
conflicting variable names, ignoring return values without (void), adding
explicit casts, etc.
Change-Id: If1fa18ab621b9c374db73fa6eaa6f6e5e55c146a
Signed-off-by: John Powell <john.powell@arm.com>
Diffstat (limited to 'include/arch/aarch32/arch.h')
| -rw-r--r-- | include/arch/aarch32/arch.h | 20 |
1 files changed, 12 insertions, 8 deletions
diff --git a/include/arch/aarch32/arch.h b/include/arch/aarch32/arch.h index 20175481f..8492b3ea4 100644 --- a/include/arch/aarch32/arch.h +++ b/include/arch/aarch32/arch.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2016-2019, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2016-2020, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -388,13 +388,17 @@ #define GET_M32(mode) (((mode) >> MODE32_SHIFT) & MODE32_MASK) -#define SPSR_MODE32(mode, isa, endian, aif) \ - ((MODE_RW_32 << MODE_RW_SHIFT | \ - ((mode) & MODE32_MASK) << MODE32_SHIFT | \ - ((isa) & SPSR_T_MASK) << SPSR_T_SHIFT | \ - ((endian) & SPSR_E_MASK) << SPSR_E_SHIFT | \ - ((aif) & SPSR_AIF_MASK) << SPSR_AIF_SHIFT) & \ - (~(SPSR_SSBS_BIT))) +#define SPSR_MODE32(mode, isa, endian, aif) \ +( \ + ( \ + (MODE_RW_32 << MODE_RW_SHIFT) | \ + (((mode) & MODE32_MASK) << MODE32_SHIFT) | \ + (((isa) & SPSR_T_MASK) << SPSR_T_SHIFT) | \ + (((endian) & SPSR_E_MASK) << SPSR_E_SHIFT) | \ + (((aif) & SPSR_AIF_MASK) << SPSR_AIF_SHIFT) \ + ) & \ + (~(SPSR_SSBS_BIT)) \ +) /* * TTBR definitions |