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| author | Vishnu Banavath <vishnu.banavath@arm.com> | 2019-08-07 10:49:05 +0100 |
|---|---|---|
| committer | Abdellatif El Khlifi <abdellatif.elkhlifi@arm.com> | 2020-02-17 17:04:46 +0000 |
| commit | 6aa138ded5e684894cd146fc1bb85df304529b46 (patch) | |
| tree | 7b91521355b19fccff090ea032b6162aab816210 /fdts | |
| parent | 93cf1f6454b9ba5b1a5946acd3bae9618f1512d6 (diff) | |
| download | platform_external_arm-trusted-firmware-6aa138ded5e684894cd146fc1bb85df304529b46.tar.gz platform_external_arm-trusted-firmware-6aa138ded5e684894cd146fc1bb85df304529b46.tar.bz2 platform_external_arm-trusted-firmware-6aa138ded5e684894cd146fc1bb85df304529b46.zip | |
corstone700: set UART clocks to 32MHz
Adding support for 32MHz UART clock and selecting it as the
default UART clock
Change-Id: I9541eaff70424e85a3b5ee4820ca0e7efb040d2c
Signed-off-by: Vishnu Banavath <vishnu.banavath@arm.com>
Signed-off-by: Abdellatif El Khlifi <abdellatif.elkhlifi@arm.com>
Diffstat (limited to 'fdts')
| -rw-r--r-- | fdts/corstone700.dts | 17 |
1 files changed, 12 insertions, 5 deletions
diff --git a/fdts/corstone700.dts b/fdts/corstone700.dts index 16cf41227..8c3bd0c05 100644 --- a/fdts/corstone700.dts +++ b/fdts/corstone700.dts @@ -1,5 +1,5 @@ /* - * Copyright (c) 2019, Arm Limited and Contributors. All rights reserved. + * Copyright (c) 2019-2020, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -68,14 +68,21 @@ clock-output-names = "smclk"; }; + uartclk: uartclk { + /* UART clock - 32MHz */ + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <32000000>; + clock-output-names = "uartclk"; + }; serial0: uart@1a510000 { compatible = "arm,pl011", "arm,primecell"; reg = <0x1a510000 0x1000>; interrupt-parent = <&gic>; interrupts = <0 19 4>; - clocks = <&refclk100mhz>, <&smbclk>; - clock-names = "apb_pclk", "smclk"; + clocks = <&uartclk>, <&refclk100mhz>; + clock-names = "uartclk", "apb_pclk"; }; serial1: uart@1a520000 { @@ -83,8 +90,8 @@ reg = <0x1a520000 0x1000>; interrupt-parent = <&gic>; interrupts = <0 20 4>; - clocks = <&refclk100mhz>, <&smbclk>; - clock-names = "apb_pclk", "smclk"; + clocks = <&uartclk>, <&refclk100mhz>; + clock-names = "uartclk", "apb_pclk"; }; timer { |