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| author | Yann Gautier <yann.gautier@st.com> | 2019-06-04 17:24:36 +0200 |
|---|---|---|
| committer | Yann Gautier <yann.gautier@st.com> | 2019-06-17 14:03:51 +0200 |
| commit | f237822f0b003dc5bec54d8c4ee961597a11116c (patch) | |
| tree | 48b3bbc84cbfd3be7c5b080e0b54305a17b7a50e /fdts/stm32mp157c.dtsi | |
| parent | 0a016775ad068d53639b97441e884ddd074e220d (diff) | |
| download | platform_external_arm-trusted-firmware-f237822f0b003dc5bec54d8c4ee961597a11116c.tar.gz platform_external_arm-trusted-firmware-f237822f0b003dc5bec54d8c4ee961597a11116c.tar.bz2 platform_external_arm-trusted-firmware-f237822f0b003dc5bec54d8c4ee961597a11116c.zip | |
fdts: stm32mp1: realign device tree files with internal devs
Update DDR parameters to version 1.45.
Remove useless sdmmc1_dir_pins_b node.
Add USART3 and UART7 nodes.
Correct a PMIC value for USB regulator.
Add TIMER12, TIMER15, CRYP, HASH and USBOTG_HS nodes.
Update DTSI file for SDMMC compatible, but overwrite it with the former
name.
Move BSEC board_id node to boards DTS files, as this OTP is specific to
STMicroelectronics boards.
Change-Id: If4d2fe090c6a8368afe8e21e5ac70579911d3939
Signed-off-by: Yann Gautier <yann.gautier@st.com>
Diffstat (limited to 'fdts/stm32mp157c.dtsi')
| -rw-r--r-- | fdts/stm32mp157c.dtsi | 57 |
1 files changed, 54 insertions, 3 deletions
diff --git a/fdts/stm32mp157c.dtsi b/fdts/stm32mp157c.dtsi index 1df76fa75..0942a91c2 100644 --- a/fdts/stm32mp157c.dtsi +++ b/fdts/stm32mp157c.dtsi @@ -70,6 +70,16 @@ interrupt-parent = <&intc>; ranges; + timers12: timer@40006000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "st,stm32-timers"; + reg = <0x40006000 0x400>; + clocks = <&rcc TIM12_K>; + clock-names = "int"; + status = "disabled"; + }; + usart2: serial@4000e000 { compatible = "st,stm32h7-uart"; reg = <0x4000e000 0x400>; @@ -127,8 +137,19 @@ status = "disabled"; }; + timers15: timer@44006000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "st,stm32-timers"; + reg = <0x44006000 0x400>; + clocks = <&rcc TIM15_K>; + clock-names = "int"; + status = "disabled"; + }; + sdmmc3: sdmmc@48004000 { - compatible = "st,stm32-sdmmc2"; + compatible = "arm,pl18x", "arm,primecell"; + arm,primecell-periphid = <0x00253180>; reg = <0x48004000 0x400>, <0x48005000 0x400>; clocks = <&rcc SDMMC3_K>; clock-names = "apb_pclk"; @@ -139,6 +160,16 @@ status = "disabled"; }; + usbotg_hs: usb-otg@49000000 { + compatible = "st,stm32mp1-hsotg", "snps,dwc2"; + reg = <0x49000000 0x10000>; + clocks = <&rcc USBO_K>; + clock-names = "otg"; + resets = <&rcc USBO_R>; + reset-names = "dwc2"; + status = "disabled"; + }; + rcc: rcc@50000000 { compatible = "st,stm32mp1-rcc", "syscon"; reg = <0x50000000 0x1000>; @@ -176,6 +207,24 @@ clocks = <&rcc SYSCFG>; }; + cryp1: cryp@54001000 { + compatible = "st,stm32mp1-cryp"; + reg = <0x54001000 0x400>; + interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&rcc CRYP1>; + resets = <&rcc CRYP1_R>; + status = "disabled"; + }; + + hash1: hash@54002000 { + compatible = "st,stm32f756-hash"; + reg = <0x54002000 0x400>; + interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&rcc HASH1>; + resets = <&rcc HASH1_R>; + status = "disabled"; + }; + rng1: rng@54003000 { compatible = "st,stm32-rng"; reg = <0x54003000 0x400>; @@ -208,7 +257,8 @@ }; sdmmc1: sdmmc@58005000 { - compatible = "st,stm32-sdmmc2"; + compatible = "arm,pl18x", "arm,primecell"; + arm,primecell-periphid = <0x00253180>; reg = <0x58005000 0x1000>, <0x58006000 0x1000>; clocks = <&rcc SDMMC1_K>; clock-names = "apb_pclk"; @@ -220,7 +270,8 @@ }; sdmmc2: sdmmc@58007000 { - compatible = "st,stm32-sdmmc2"; + compatible = "arm,pl18x", "arm,primecell"; + arm,primecell-periphid = <0x00253180>; reg = <0x58007000 0x1000>, <0x58008000 0x1000>; clocks = <&rcc SDMMC2_K>; clock-names = "apb_pclk"; |