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| author | Louis Mayencourt <louis.mayencourt@arm.com> | 2020-01-24 13:30:28 +0000 |
|---|---|---|
| committer | Louis Mayencourt <louis.mayencourt@arm.com> | 2020-01-28 11:10:48 +0000 |
| commit | f1be00da0b0acf90355558e01d5f8e1f79c0d481 (patch) | |
| tree | 17f863ee4f3f43cbeaa35e70e72e514774815642 /drivers | |
| parent | 262c5d30689403112568979dd6154849037fb122 (diff) | |
| download | platform_external_arm-trusted-firmware-f1be00da0b0acf90355558e01d5f8e1f79c0d481.tar.gz platform_external_arm-trusted-firmware-f1be00da0b0acf90355558e01d5f8e1f79c0d481.tar.bz2 platform_external_arm-trusted-firmware-f1be00da0b0acf90355558e01d5f8e1f79c0d481.zip | |
Use correct type when reading SCR register
The Secure Configuration Register is 64-bits in AArch64 and 32-bits in
AArch32. Use u_register_t instead of unsigned int to reflect this.
Change-Id: I51b69467baba36bf0cfaec2595dc8837b1566934
Signed-off-by: Louis Mayencourt <louis.mayencourt@arm.com>
Diffstat (limited to 'drivers')
| -rw-r--r-- | drivers/arm/gic/v3/gicv3_main.c | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/drivers/arm/gic/v3/gicv3_main.c b/drivers/arm/gic/v3/gicv3_main.c index fb49a579d..a672b18f3 100644 --- a/drivers/arm/gic/v3/gicv3_main.c +++ b/drivers/arm/gic/v3/gicv3_main.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2015-2020, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -235,7 +235,7 @@ void gicv3_rdistif_on(unsigned int proc_num) void gicv3_cpuif_enable(unsigned int proc_num) { uintptr_t gicr_base; - unsigned int scr_el3; + u_register_t scr_el3; unsigned int icc_sre_el3; assert(gicv3_driver_data != NULL); @@ -258,7 +258,7 @@ void gicv3_cpuif_enable(unsigned int proc_num) icc_sre_el3 |= (ICC_SRE_EN_BIT | ICC_SRE_SRE_BIT); write_icc_sre_el3(read_icc_sre_el3() | icc_sre_el3); - scr_el3 = (uint32_t) read_scr_el3(); + scr_el3 = read_scr_el3(); /* * Switch to NS state to write Non secure ICC_SRE_EL1 and |