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| author | Icenowy Zheng <icenowy@aosc.io> | 2018-07-22 21:27:30 +0800 |
|---|---|---|
| committer | Icenowy Zheng <icenowy@aosc.io> | 2018-09-07 22:09:45 +0800 |
| commit | 207199141312018cf9560fba32ae421324f041cb (patch) | |
| tree | 08f8a7b638b22b0e2c538aa90f3ee28a70e191ee /drivers | |
| parent | 7c26b6ecea26be4811d040b8c3052b6f5ef1bfb4 (diff) | |
| download | platform_external_arm-trusted-firmware-207199141312018cf9560fba32ae421324f041cb.tar.gz platform_external_arm-trusted-firmware-207199141312018cf9560fba32ae421324f041cb.tar.bz2 platform_external_arm-trusted-firmware-207199141312018cf9560fba32ae421324f041cb.zip | |
drivers: mentor: mi2cv: add inverted interrupt clear flag quirk
The I2C controller on Allwinner SoCs after A31 has a inverted interrupt
clear flag, which needs to be written 1 (rather than 0 on Marvell SoCs
and old Allwinner SoCs) to clear.
Add such a quirk to mi2cv driver common code.
Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
Diffstat (limited to 'drivers')
| -rw-r--r-- | drivers/mentor/i2c/mi2cv.c | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/drivers/mentor/i2c/mi2cv.c b/drivers/mentor/i2c/mi2cv.c index 618836ba5..1b73e6f16 100644 --- a/drivers/mentor/i2c/mi2cv.c +++ b/drivers/mentor/i2c/mi2cv.c @@ -68,7 +68,11 @@ static void mentor_i2c_interrupt_clear(void) uint32_t reg; reg = mmio_read_32((uintptr_t)&base->control); +#ifndef I2C_INTERRUPT_CLEAR_INVERTED reg &= ~(I2C_CONTROL_IFLG); +#else + reg |= I2C_CONTROL_IFLG; +#endif mmio_write_32((uintptr_t)&base->control, reg); /* Wait for 1 us for the clear to take effect */ udelay(1); |