rcar_gen3: drivers: qos: M3W: Drop extra level of nesting

The extra level of nesting is not necessary, drop it.
No functional change.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Change-Id: I086ab1f457866f0e2c3ccd67609c0be35631f893

3 files changed, 35 insertions, 51 deletions

diff --git a/drivers/staging/renesas/rcar/qos/M3/qos_init_m3_v10.c b/drivers/staging/renesas/rcar/qos/M3/qos_init_m3_v10.c
index fb69eaa07..288722887 100644
--- a/drivers/staging/renesas/rcar/qos/M3/qos_init_m3_v10.c
+++ b/drivers/staging/renesas/rcar/qos/M3/qos_init_m3_v10.c
@@ -168,17 +168,15 @@ void qos_init_m3_v10(void)
 	io_write_32(QOSCTRL_REF_ARS, 0x00330000U);
 
 	/* QOSBW SRAM setting */
-	{
-		uint32_t i;
-
-		for (i = 0U; i < ARRAY_SIZE(mstat_fix); i++) {
-			io_write_64(QOSBW_FIX_QOS_BANK0 + i * 8, mstat_fix[i]);
-			io_write_64(QOSBW_FIX_QOS_BANK1 + i * 8, mstat_fix[i]);
-		}
-		for (i = 0U; i < ARRAY_SIZE(mstat_be); i++) {
-			io_write_64(QOSBW_BE_QOS_BANK0 + i * 8, mstat_be[i]);
-			io_write_64(QOSBW_BE_QOS_BANK1 + i * 8, mstat_be[i]);
-		}
+	uint32_t i;
+
+	for (i = 0U; i < ARRAY_SIZE(mstat_fix); i++) {
+		io_write_64(QOSBW_FIX_QOS_BANK0 + i * 8, mstat_fix[i]);
+		io_write_64(QOSBW_FIX_QOS_BANK1 + i * 8, mstat_fix[i]);
+	}
+	for (i = 0U; i < ARRAY_SIZE(mstat_be); i++) {
+		io_write_64(QOSBW_BE_QOS_BANK0 + i * 8, mstat_be[i]);
+		io_write_64(QOSBW_BE_QOS_BANK1 + i * 8, mstat_be[i]);
 	}
 
 	/* 3DG bus Leaf setting */
diff --git a/drivers/staging/renesas/rcar/qos/M3/qos_init_m3_v11.c b/drivers/staging/renesas/rcar/qos/M3/qos_init_m3_v11.c
index 30cbc939f..8e2e18116 100644
--- a/drivers/staging/renesas/rcar/qos/M3/qos_init_m3_v11.c
+++ b/drivers/staging/renesas/rcar/qos/M3/qos_init_m3_v11.c
@@ -175,30 +175,26 @@ void qos_init_m3_v11(void)
 	io_write_32(QOSCTRL_REF_ARS, 0x00330000U);
 #endif /* RCAR_REWT_TRAINING != RCAR_REWT_TRAINING_DISABLE */
 
-	{
-		uint32_t i;
-
-		for (i = 0U; i < ARRAY_SIZE(mstat_fix); i++) {
-			io_write_64(QOSBW_FIX_QOS_BANK0 + i * 8, mstat_fix[i]);
-			io_write_64(QOSBW_FIX_QOS_BANK1 + i * 8, mstat_fix[i]);
-		}
-		for (i = 0U; i < ARRAY_SIZE(mstat_be); i++) {
-			io_write_64(QOSBW_BE_QOS_BANK0 + i * 8, mstat_be[i]);
-			io_write_64(QOSBW_BE_QOS_BANK1 + i * 8, mstat_be[i]);
-		}
+	uint32_t i;
+
+	for (i = 0U; i < ARRAY_SIZE(mstat_fix); i++) {
+		io_write_64(QOSBW_FIX_QOS_BANK0 + i * 8, mstat_fix[i]);
+		io_write_64(QOSBW_FIX_QOS_BANK1 + i * 8, mstat_fix[i]);
+	}
+	for (i = 0U; i < ARRAY_SIZE(mstat_be); i++) {
+		io_write_64(QOSBW_BE_QOS_BANK0 + i * 8, mstat_be[i]);
+		io_write_64(QOSBW_BE_QOS_BANK1 + i * 8, mstat_be[i]);
+	}
 #if RCAR_REWT_TRAINING != RCAR_REWT_TRAINING_DISABLE
-		for (i = 0U; i < ARRAY_SIZE(qoswt_fix); i++) {
-			io_write_64(QOSWT_FIX_WTQOS_BANK0 + i * 8,
-				    qoswt_fix[i]);
-			io_write_64(QOSWT_FIX_WTQOS_BANK1 + i * 8,
-				    qoswt_fix[i]);
-		}
-		for (i = 0U; i < ARRAY_SIZE(qoswt_be); i++) {
-			io_write_64(QOSWT_BE_WTQOS_BANK0 + i * 8, qoswt_be[i]);
-			io_write_64(QOSWT_BE_WTQOS_BANK1 + i * 8, qoswt_be[i]);
-		}
-#endif /* RCAR_REWT_TRAINING != RCAR_REWT_TRAINING_DISABLE */
+	for (i = 0U; i < ARRAY_SIZE(qoswt_fix); i++) {
+		io_write_64(QOSWT_FIX_WTQOS_BANK0 + i * 8, qoswt_fix[i]);
+		io_write_64(QOSWT_FIX_WTQOS_BANK1 + i * 8, qoswt_fix[i]);
+	}
+	for (i = 0U; i < ARRAY_SIZE(qoswt_be); i++) {
+		io_write_64(QOSWT_BE_WTQOS_BANK0 + i * 8, qoswt_be[i]);
+		io_write_64(QOSWT_BE_WTQOS_BANK1 + i * 8, qoswt_be[i]);
 	}
+#endif /* RCAR_REWT_TRAINING != RCAR_REWT_TRAINING_DISABLE */
 
 	/* 3DG bus Leaf setting */
 	io_write_32(GPU_ACT_GRD, 0x00001234U);
diff --git a/drivers/staging/renesas/rcar/qos/M3/qos_init_m3_v30.c b/drivers/staging/renesas/rcar/qos/M3/qos_init_m3_v30.c
index 585e37753..5a8d69fb0 100644
--- a/drivers/staging/renesas/rcar/qos/M3/qos_init_m3_v30.c
+++ b/drivers/staging/renesas/rcar/qos/M3/qos_init_m3_v30.c
@@ -179,36 +179,26 @@ void qos_init_m3_v30(void)
 	io_write_32(QOSCTRL_SL_INIT, SL_INIT_REFFSSLOT | SL_INIT_SLOTSSLOT | SL_INIT_SSLOTCLK_M3_30);
 	io_write_32(QOSCTRL_REF_ARS, ((QOSCTRL_REF_ARS_ARBSTOPCYCLE_M3_30 << 16)));
 
-	{
 	uint32_t i;
 
 	for (i = 0U; i < ARRAY_SIZE(mstat_fix); i++) {
-		io_write_64(QOSBW_FIX_QOS_BANK0 + i*8,
-				mstat_fix[i]);
-		io_write_64(QOSBW_FIX_QOS_BANK1 + i*8,
-				mstat_fix[i]);
+		io_write_64(QOSBW_FIX_QOS_BANK0 + i * 8, mstat_fix[i]);
+		io_write_64(QOSBW_FIX_QOS_BANK1 + i * 8, mstat_fix[i]);
 	}
 	for (i = 0U; i < ARRAY_SIZE(mstat_be); i++) {
-		io_write_64(QOSBW_BE_QOS_BANK0 + i*8,
-				mstat_be[i]);
-		io_write_64(QOSBW_BE_QOS_BANK1 + i*8,
-				mstat_be[i]);
+		io_write_64(QOSBW_BE_QOS_BANK0 + i * 8, mstat_be[i]);
+		io_write_64(QOSBW_BE_QOS_BANK1 + i * 8, mstat_be[i]);
 	}
 #if RCAR_REWT_TRAINING != RCAR_REWT_TRAINING_DISABLE
 	for (i = 0U; i < ARRAY_SIZE(qoswt_fix); i++) {
-		io_write_64(QOSWT_FIX_WTQOS_BANK0 + i*8,
-				qoswt_fix[i]);
-		io_write_64(QOSWT_FIX_WTQOS_BANK1 + i*8,
-				qoswt_fix[i]);
+		io_write_64(QOSWT_FIX_WTQOS_BANK0 + i * 8, qoswt_fix[i]);
+		io_write_64(QOSWT_FIX_WTQOS_BANK1 + i * 8, qoswt_fix[i]);
 	}
 	for (i = 0U; i < ARRAY_SIZE(qoswt_be); i++) {
-		io_write_64(QOSWT_BE_WTQOS_BANK0 + i*8,
-				qoswt_be[i]);
-		io_write_64(QOSWT_BE_WTQOS_BANK1 + i*8,
-				qoswt_be[i]);
+		io_write_64(QOSWT_BE_WTQOS_BANK0 + i * 8, qoswt_be[i]);
+		io_write_64(QOSWT_BE_WTQOS_BANK1 + i * 8, qoswt_be[i]);
 	}
 #endif /* RCAR_REWT_TRAINING != RCAR_REWT_TRAINING_DISABLE */
-	}
 
 	/* RT bus Leaf setting */
 	io_write_32(RT_ACT0, 0x00000000U);