Merge pull request #1914 from marex/arm/master/d3draak-v2.0.1

Arm/master/d3draak v2.0.1

18 files changed, 2544 insertions, 13 deletions

diff --git a/drivers/renesas/rcar/board/board.c b/drivers/renesas/rcar/board/board.c
index f15e06bc0..8c4eec24c 100644
--- a/drivers/renesas/rcar/board/board.c
+++ b/drivers/renesas/rcar/board/board.c
@@ -14,7 +14,9 @@
 #include "board.h"
 
 #ifndef BOARD_DEFAULT
-#if (RCAR_LSI == RCAR_E3)
+#if (RCAR_LSI == RCAR_D3)
+#define BOARD_DEFAULT		(BOARD_DRAAK << BOARD_CODE_SHIFT)
+#elif (RCAR_LSI == RCAR_E3)
 #define BOARD_DEFAULT		(BOARD_EBISU << BOARD_CODE_SHIFT)
 #else
 #define BOARD_DEFAULT		(BOARD_SALVATOR_X << BOARD_CODE_SHIFT)
@@ -32,6 +34,7 @@
 #define SK_ID	{ 0x10U, 0xFFU, 0xFFU, 0xFFU, 0xFFU, 0xFFU, 0xFFU, 0xFFU }
 #define EB4_ID	{ 0x10U, 0xFFU, 0xFFU, 0xFFU, 0xFFU, 0xFFU, 0xFFU, 0xFFU }
 #define EB_ID	{ 0x10U, 0xFFU, 0xFFU, 0xFFU, 0xFFU, 0xFFU, 0xFFU, 0xFFU }
+#define DR_ID	{ 0x10U, 0xFFU, 0xFFU, 0xFFU, 0xFFU, 0xFFU, 0xFFU, 0xFFU }
 #define KK_ID	{ 0x10U, 0xFFU, 0xFFU, 0xFFU, 0xFFU, 0xFFU, 0xFFU, 0xFFU }
 
 const char *g_board_tbl[] = {
@@ -42,6 +45,7 @@ const char *g_board_tbl[] = {
 	[BOARD_EBISU_4D] = "Ebisu-4D",
 	[BOARD_KRIEK] = "Kriek",
 	[BOARD_EBISU] = "Ebisu",
+	[BOARD_DRAAK] = "Draak",
 	[BOARD_UNKNOWN] = "unknown"
 };
 
@@ -55,6 +59,7 @@ int32_t rcar_get_board_type(uint32_t *type, uint32_t *rev)
 		[BOARD_SALVATOR_X] = SX_ID,
 		[BOARD_EBISU_4D] = EB4_ID,
 		[BOARD_EBISU] = EB_ID,
+		[BOARD_DRAAK] = DR_ID,
 		[BOARD_KRIEK] = KK_ID,
 	};
 	static uint8_t board_id = BOARD_ID_UNKNOWN;
diff --git a/drivers/renesas/rcar/board/board.h b/drivers/renesas/rcar/board/board.h
index 7bb2a0626..05c4e8aa1 100644
--- a/drivers/renesas/rcar/board/board.h
+++ b/drivers/renesas/rcar/board/board.h
@@ -15,7 +15,8 @@
 #define BOARD_EBISU			(0x08)
 #define BOARD_STARTER_KIT_PRE		(0x0B)
 #define BOARD_EBISU_4D			(0x0DU)
-#define BOARD_UNKNOWN			(BOARD_EBISU_4D + 1U)
+#define BOARD_DRAAK			(0x0EU)
+#define BOARD_UNKNOWN			(BOARD_DRAAK + 1U)
 
 #define BOARD_REV_UNKNOWN		(0xFF)
 
diff --git a/drivers/renesas/rcar/pwrc/pwrc.c b/drivers/renesas/rcar/pwrc/pwrc.c
index d85e4a51b..8bea1b51d 100644
--- a/drivers/renesas/rcar/pwrc/pwrc.c
+++ b/drivers/renesas/rcar/pwrc/pwrc.c
@@ -737,6 +737,12 @@ uint32_t rcar_pwrc_get_mpidr_cluster(uint64_t mpidr)
 	return c;
 }
 
+#if RCAR_LSI == RCAR_D3
+uint32_t rcar_pwrc_get_cpu_num(uint32_t c)
+{
+	return 1;
+}
+#else
 uint32_t rcar_pwrc_get_cpu_num(uint32_t c)
 {
 	uint32_t reg = mmio_read_32(RCAR_PRR);
@@ -768,6 +774,7 @@ count_ca57:
 done:
 	return count;
 }
+#endif
 
 int32_t rcar_pwrc_cpu_on_check(uint64_t mpidr)
 {
diff --git a/drivers/renesas/rcar/rom/rom_api.c b/drivers/renesas/rcar/rom/rom_api.c
index be38fbff3..6f448a5aa 100644
--- a/drivers/renesas/rcar/rom/rom_api.c
+++ b/drivers/renesas/rcar/rom/rom_api.c
@@ -19,7 +19,7 @@ typedef uint32_t(*rom_get_lcs_api_f) (uint32_t *lcs);
 #define OLD_API_TABLE1	(0U)	/* H3 Ver.1.0/Ver.1.1 */
 #define OLD_API_TABLE2	(1U)	/* H3 Ver.2.0 */
 #define OLD_API_TABLE3	(2U)	/* M3 Ver.1.0 */
-#define NEW_API_TABLE	(3U)	/* H3 Ver.3.0, M3 Ver.1.1 or later, M3N, E3 */
+#define NEW_API_TABLE	(3U)	/* H3 Ver.3.0, M3 Ver.1.1 or later, M3N, E3, D3 */
 #define API_TABLE_MAX	(4U)	/* table max */
 				/* Later than H3 Ver.2.0 */
 
@@ -66,7 +66,7 @@ uint32_t rcar_rom_secure_boot_api(uint32_t *key, uint32_t *cert,
 		0xEB10DD64U,	/* H3 Ver.1.0/Ver.1.1 */
 		0xEB116ED4U,	/* H3 Ver.2.0 */
 		0xEB1102FCU,	/* M3 Ver.1.0 */
-		0xEB100180U	/* H3 Ver.3.0, M3 Ver.1.1 or later, M3N, E3 */
+		0xEB100180U	/* H3 Ver.3.0, M3 Ver.1.1 or later, M3N, E3, D3 */
 	};
 	rom_secure_boot_api_f secure_boot;
 	uint32_t index;
@@ -83,7 +83,7 @@ uint32_t rcar_rom_get_lcs(uint32_t *lcs)
 		0xEB10DFE0U,	/* H3 Ver.1.0/Ver.1.1 */
 		0xEB117150U,	/* H3 Ver.2.0 */
 		0xEB110578U,	/* M3 Ver.1.0 */
-		0xEB10018CU	/* H3 Ver.3.0, M3 Ver.1.1 or later, M3N, E3 */
+		0xEB10018CU	/* H3 Ver.3.0, M3 Ver.1.1 or later, M3N, E3, D3 */
 	};
 	rom_get_lcs_api_f get_lcs;
 	uint32_t index;
diff --git a/drivers/renesas/rcar/scif/scif.S b/drivers/renesas/rcar/scif/scif.S
index 09dc90b8d..19b32e32b 100644
--- a/drivers/renesas/rcar/scif/scif.S
+++ b/drivers/renesas/rcar/scif/scif.S
@@ -17,6 +17,7 @@
 #define	PRR_CUT_MASK		(0x000000FF)
 #define	PRR_PRODUCT_H3_VER_10	(0x00004F00)
 #define	PRR_PRODUCT_E3		(0x00005700)
+#define	PRR_PRODUCT_D3		(0x00005800)
 
 /* module stop */
 #define	CPG_BASE		(0xE6150000)
@@ -60,6 +61,7 @@
 					 SCSMR_STOP_1 +		\
 					 SCSMR_CKS_DIV1)
 #define	SCBRR_115200BPS		(17)
+#define	SCBRR_115200BPSON	(16)
 #define	SCBRR_115200BPS_E3_SSCG	(15)
 #define	SCBRR_230400BPS		(8)
 
@@ -192,22 +194,29 @@ func console_core_init
 	cmp	w1, w2
 	beq	3f
 	and	w1, w1, #PRR_PRODUCT_MASK
+	mov	w2, #PRR_PRODUCT_D3
+	cmp	w1, w2
+	beq	4f
+	and	w1, w1, #PRR_PRODUCT_MASK
 	mov	w2, #PRR_PRODUCT_E3
 	cmp	w1, w2
-	bne	4f
+	bne	5f
 
 	ldr	x1, =RST_MODEMR
 	ldr	w1, [x1]
 	and	w1, w1, #MODEMR_MD12
 	mov	w2, #MODEMR_MD12
 	cmp	w1, w2
-	bne	4f
+	bne	5f
 
 	mov	w1, #SCBRR_115200BPS_E3_SSCG
 	b	2f
-4:
+5:
 	mov	w1, #SCBRR_115200BPS
 	b	2f
+4:
+	mov	w1, #SCBRR_115200BPSON
+	b	2f
 3:
 	mov	w1, #SCBRR_230400BPS
 2:
diff --git a/drivers/renesas/rcar/watchdog/swdt.c b/drivers/renesas/rcar/watchdog/swdt.c
index 7793ae500..8b2943cc6 100644
--- a/drivers/renesas/rcar/watchdog/swdt.c
+++ b/drivers/renesas/rcar/watchdog/swdt.c
@@ -49,7 +49,11 @@ extern void gicd_set_icenabler(uintptr_t base, unsigned int id);
 #define WTCSRA_INIT_DATA		(WTCSRA_UPPER_BYTE + 0x0FU)
 #define WTCSRB_INIT_DATA		(WTCSRB_UPPER_BYTE + 0x21U)
 
+#if RCAR_LSI == RCAR_D3
+#define WTCNT_COUNT_8p13k		(0x10000U - 40760U)
+#else
 #define WTCNT_COUNT_8p13k		(0x10000U - 40687U)
+#endif
 #define WTCNT_COUNT_8p13k_H3VER10	(0x10000U - 20343U)
 #define WTCNT_COUNT_8p22k		(0x10000U - 41115U)
 #define WTCNT_COUNT_7p81k		(0x10000U - 39062U)
diff --git a/drivers/staging/renesas/rcar/ddr/ddr.mk b/drivers/staging/renesas/rcar/ddr/ddr.mk
index ef134132a..a73d227dd 100644
--- a/drivers/staging/renesas/rcar/ddr/ddr.mk
+++ b/drivers/staging/renesas/rcar/ddr/ddr.mk
@@ -6,8 +6,10 @@
 
 ifeq (${RCAR_LSI},${RCAR_E3})
     include drivers/staging/renesas/rcar/ddr/ddr_a/ddr_a.mk
+    BL2_SOURCES += drivers/staging/renesas/rcar/ddr/dram_sub_func.c
+else ifeq (${RCAR_LSI},${RCAR_D3})
+    include drivers/staging/renesas/rcar/ddr/ddr_a/ddr_a.mk
 else
     include drivers/staging/renesas/rcar/ddr/ddr_b/ddr_b.mk
+    BL2_SOURCES += drivers/staging/renesas/rcar/ddr/dram_sub_func.c
 endif
-
-BL2_SOURCES += drivers/staging/renesas/rcar/ddr/dram_sub_func.c
diff --git a/drivers/staging/renesas/rcar/ddr/ddr_a/boot_init_dram_regdef_d3.h b/drivers/staging/renesas/rcar/ddr/ddr_a/boot_init_dram_regdef_d3.h
new file mode 100644
index 000000000..e157ab1ce
--- /dev/null
+++ b/drivers/staging/renesas/rcar/ddr/ddr_a/boot_init_dram_regdef_d3.h
@@ -0,0 +1,208 @@
+/*
+ * Copyright (c) 2015-2017, Renesas Electronics Corporation
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+/*
+ * Revision history
+ *
+ * rev.0.01    2017/05/22    New
+ */
+
+#ifndef BOOT_INIT_DRAM_REGDEF_D3_H_
+#define BOOT_INIT_DRAM_REGDEF_D3_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+#define				BIT0						0x00000001U
+#define				BIT30						0x40000000U
+
+/* DBSC registers */
+
+#define				DBSC_D3_DBSYSCONF1         0xE6790004U
+#define				DBSC_D3_DBPHYCONF0         0xE6790010U
+#define				DBSC_D3_DBKIND             0xE6790020U
+#define				DBSC_D3_DBMEMCONF00        0xE6790030U
+#define				DBSC_D3_DBMEMCONF01        0xE6790034U
+#define				DBSC_D3_DBMEMCONF02        0xE6790038U
+#define				DBSC_D3_DBMEMCONF03        0xE679003CU
+#define				DBSC_D3_DBMEMCONF10        0xE6790040U
+#define				DBSC_D3_DBMEMCONF11        0xE6790044U
+#define				DBSC_D3_DBMEMCONF12        0xE6790048U
+#define				DBSC_D3_DBMEMCONF13        0xE679004CU
+#define				DBSC_D3_DBMEMCONF20        0xE6790050U
+#define				DBSC_D3_DBMEMCONF21        0xE6790054U
+#define				DBSC_D3_DBMEMCONF22        0xE6790058U
+#define				DBSC_D3_DBMEMCONF23        0xE679005CU
+#define				DBSC_D3_DBMEMCONF30        0xE6790060U
+#define				DBSC_D3_DBMEMCONF31        0xE6790064U
+#define				DBSC_D3_DBMEMCONF32        0xE6790068U
+#define				DBSC_D3_DBMEMCONF33        0xE679006CU
+#define				DBSC_D3_DBSYSCNT0          0xE6790100U
+#define				DBSC_D3_DBSVCR1            0xE6790104U
+#define				DBSC_D3_DBSTATE0           0xE6790108U
+#define				DBSC_D3_DBSTATE1           0xE679010CU
+#define				DBSC_D3_DBINTEN            0xE6790180U
+#define				DBSC_D3_DBINTSTAT0         0xE6790184U
+#define				DBSC_D3_DBACEN             0xE6790200U
+#define				DBSC_D3_DBRFEN             0xE6790204U
+#define				DBSC_D3_DBCMD              0xE6790208U
+#define				DBSC_D3_DBWAIT             0xE6790210U
+#define				DBSC_D3_DBSYSCTRL0         0xE6790280U
+#define				DBSC_D3_DBTR0              0xE6790300U
+#define				DBSC_D3_DBTR1              0xE6790304U
+#define				DBSC_D3_DBTR2              0xE6790308U
+#define				DBSC_D3_DBTR3              0xE679030CU
+#define				DBSC_D3_DBTR4              0xE6790310U
+#define				DBSC_D3_DBTR5              0xE6790314U
+#define				DBSC_D3_DBTR6              0xE6790318U
+#define				DBSC_D3_DBTR7              0xE679031CU
+#define				DBSC_D3_DBTR8              0xE6790320U
+#define				DBSC_D3_DBTR9              0xE6790324U
+#define				DBSC_D3_DBTR10             0xE6790328U
+#define				DBSC_D3_DBTR11             0xE679032CU
+#define				DBSC_D3_DBTR12             0xE6790330U
+#define				DBSC_D3_DBTR13             0xE6790334U
+#define				DBSC_D3_DBTR14             0xE6790338U
+#define				DBSC_D3_DBTR15             0xE679033CU
+#define				DBSC_D3_DBTR16             0xE6790340U
+#define				DBSC_D3_DBTR17             0xE6790344U
+#define				DBSC_D3_DBTR18             0xE6790348U
+#define				DBSC_D3_DBTR19             0xE679034CU
+#define				DBSC_D3_DBTR20             0xE6790350U
+#define				DBSC_D3_DBTR21             0xE6790354U
+#define				DBSC_D3_DBTR22             0xE6790358U
+#define				DBSC_D3_DBTR24             0xE6790360U
+#define				DBSC_D3_DBTR25             0xE6790364U
+#define				DBSC_D3_DBBL               0xE6790400U
+#define				DBSC_D3_DBRFCNF1           0xE6790414U
+#define				DBSC_D3_DBRFCNF2           0xE6790418U
+#define				DBSC_D3_DBCALCNF           0xE6790424U
+#define				DBSC_D3_DBRNK2             0xE6790438U
+#define				DBSC_D3_DBRNK3             0xE679043CU
+#define				DBSC_D3_DBRNK4             0xE6790440U
+#define				DBSC_D3_DBRNK5             0xE6790444U
+#define				DBSC_D3_DBPDNCNF           0xE6790450U
+#define				DBSC_D3_DBODT0             0xE6790460U
+#define				DBSC_D3_DBODT1             0xE6790464U
+#define				DBSC_D3_DBODT2             0xE6790468U
+#define				DBSC_D3_DBODT3             0xE679046CU
+#define				DBSC_D3_DBADJ0             0xE6790500U
+#define				DBSC_D3_DBDBICNT           0xE6790518U
+#define				DBSC_D3_DBDFICUPDCNF       0xE679052CU
+#define				DBSC_D3_DBDFICNT0          0xE6790604U
+#define				DBSC_D3_DBPDLK0            0xE6790620U
+#define				DBSC_D3_DBPDRGA0           0xE6790624U
+#define				DBSC_D3_DBPDRGD0           0xE6790628U
+#define				DBSC_D3_DBPDSTAT00         0xE6790630U
+#define				DBSC_D3_DBDFISTAT1         0xE6790640U
+#define				DBSC_D3_DBDFICNT1          0xE6790644U
+#define				DBSC_D3_DBPDLK1            0xE6790660U
+#define				DBSC_D3_DBPDRGA1           0xE6790664U
+#define				DBSC_D3_DBPDRGD1           0xE6790668U
+#define				DBSC_D3_DBDFICNT2          0xE6790684U
+#define				DBSC_D3_DBPDLK2            0xE67906A0U
+#define				DBSC_D3_DBPDRGA2           0xE67906A4U
+#define				DBSC_D3_DBPDRGD2           0xE67906A8U
+#define				DBSC_D3_DBPDSTAT20         0xE67906B0U
+#define				DBSC_D3_DBDFISTAT3         0xE67906C0U
+#define				DBSC_D3_DBDFICNT3          0xE67906C4U
+#define				DBSC_D3_DBPDLK3            0xE67906E0U
+#define				DBSC_D3_DBPDRGA3           0xE67906E4U
+#define				DBSC_D3_DBPDRGD3           0xE67906E8U
+#define				DBSC_D3_DBBUS0CNF1         0xE6790804U
+#define				DBSC_D3_DBCAM0CNF1         0xE6790904U
+#define				DBSC_D3_DBCAM0CNF2         0xE6790908U
+#define				DBSC_D3_DBCAM0STAT0        0xE6790980U
+#define				DBSC_D3_DBCAM1STAT0        0xE6790990U
+#define				DBSC_D3_DBBCAMDIS          0xE67909FCU
+#define				DBSC_D3_DBSCHCNT0          0xE6791000U
+#define				DBSC_D3_DBSCHSZ0           0xE6791010U
+#define				DBSC_D3_DBSCHRW0           0xE6791020U
+#define				DBSC_D3_DBSCHRW1           0xE6791024U
+#define				DBSC_D3_DBSCHQOS00         0xE6791030U
+#define				DBSC_D3_DBSCHQOS01         0xE6791034U
+#define				DBSC_D3_DBSCHQOS02         0xE6791038U
+#define				DBSC_D3_DBSCHQOS03         0xE679103CU
+#define				DBSC_D3_DBSCHQOS10         0xE6791040U
+#define				DBSC_D3_DBSCHQOS11         0xE6791044U
+#define				DBSC_D3_DBSCHQOS12         0xE6791048U
+#define				DBSC_D3_DBSCHQOS13         0xE679104CU
+#define				DBSC_D3_DBSCHQOS20         0xE6791050U
+#define				DBSC_D3_DBSCHQOS21         0xE6791054U
+#define				DBSC_D3_DBSCHQOS22         0xE6791058U
+#define				DBSC_D3_DBSCHQOS23         0xE679105CU
+#define				DBSC_D3_DBSCHQOS30         0xE6791060U
+#define				DBSC_D3_DBSCHQOS31         0xE6791064U
+#define				DBSC_D3_DBSCHQOS32         0xE6791068U
+#define				DBSC_D3_DBSCHQOS33         0xE679106CU
+#define				DBSC_D3_DBSCHQOS40         0xE6791070U
+#define				DBSC_D3_DBSCHQOS41         0xE6791074U
+#define				DBSC_D3_DBSCHQOS42         0xE6791078U
+#define				DBSC_D3_DBSCHQOS43         0xE679107CU
+#define				DBSC_D3_DBSCHQOS50         0xE6791080U
+#define				DBSC_D3_DBSCHQOS51         0xE6791084U
+#define				DBSC_D3_DBSCHQOS52         0xE6791088U
+#define				DBSC_D3_DBSCHQOS53         0xE679108CU
+#define				DBSC_D3_DBSCHQOS60         0xE6791090U
+#define				DBSC_D3_DBSCHQOS61         0xE6791094U
+#define				DBSC_D3_DBSCHQOS62         0xE6791098U
+#define				DBSC_D3_DBSCHQOS63         0xE679109CU
+#define				DBSC_D3_DBSCHQOS70         0xE67910A0U
+#define				DBSC_D3_DBSCHQOS71         0xE67910A4U
+#define				DBSC_D3_DBSCHQOS72         0xE67910A8U
+#define				DBSC_D3_DBSCHQOS73         0xE67910ACU
+#define				DBSC_D3_DBSCHQOS80         0xE67910B0U
+#define				DBSC_D3_DBSCHQOS81         0xE67910B4U
+#define				DBSC_D3_DBSCHQOS82         0xE67910B8U
+#define				DBSC_D3_DBSCHQOS83         0xE67910BCU
+#define				DBSC_D3_DBSCHQOS90         0xE67910C0U
+#define				DBSC_D3_DBSCHQOS91         0xE67910C4U
+#define				DBSC_D3_DBSCHQOS92         0xE67910C8U
+#define				DBSC_D3_DBSCHQOS93         0xE67910CCU
+#define				DBSC_D3_DBSCHQOS100        0xE67910D0U
+#define				DBSC_D3_DBSCHQOS101        0xE67910D4U
+#define				DBSC_D3_DBSCHQOS102        0xE67910D8U
+#define				DBSC_D3_DBSCHQOS103        0xE67910DCU
+#define				DBSC_D3_DBSCHQOS110        0xE67910E0U
+#define				DBSC_D3_DBSCHQOS111        0xE67910E4U
+#define				DBSC_D3_DBSCHQOS112        0xE67910E8U
+#define				DBSC_D3_DBSCHQOS113        0xE67910ECU
+#define				DBSC_D3_DBSCHQOS120        0xE67910F0U
+#define				DBSC_D3_DBSCHQOS121        0xE67910F4U
+#define				DBSC_D3_DBSCHQOS122        0xE67910F8U
+#define				DBSC_D3_DBSCHQOS123        0xE67910FCU
+#define				DBSC_D3_DBSCHQOS130        0xE6791100U
+#define				DBSC_D3_DBSCHQOS131        0xE6791104U
+#define				DBSC_D3_DBSCHQOS132        0xE6791108U
+#define				DBSC_D3_DBSCHQOS133        0xE679110CU
+#define				DBSC_D3_DBSCHQOS140        0xE6791110U
+#define				DBSC_D3_DBSCHQOS141        0xE6791114U
+#define				DBSC_D3_DBSCHQOS142        0xE6791118U
+#define				DBSC_D3_DBSCHQOS143        0xE679111CU
+#define				DBSC_D3_DBSCHQOS150        0xE6791120U
+#define				DBSC_D3_DBSCHQOS151        0xE6791124U
+#define				DBSC_D3_DBSCHQOS152        0xE6791128U
+#define				DBSC_D3_DBSCHQOS153        0xE679112CU
+#define				DBSC_D3_SCFCTST0           0xE6791700U
+#define				DBSC_D3_SCFCTST1           0xE6791708U
+#define				DBSC_D3_SCFCTST2           0xE679170CU
+#define				DBSC_D3_DBMRRDR0           0xE6791800U
+#define				DBSC_D3_DBMRRDR1           0xE6791804U
+#define				DBSC_D3_DBMRRDR2           0xE6791808U
+#define				DBSC_D3_DBMRRDR3           0xE679180CU
+#define				DBSC_D3_DBMRRDR4           0xE6791810U
+#define				DBSC_D3_DBMRRDR5           0xE6791814U
+#define				DBSC_D3_DBMRRDR6           0xE6791818U
+#define				DBSC_D3_DBMRRDR7           0xE679181CU
+
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* BOOT_INIT_DRAM_REGDEF_D3_H_*/
diff --git a/drivers/staging/renesas/rcar/ddr/ddr_a/ddr_a.mk b/drivers/staging/renesas/rcar/ddr/ddr_a/ddr_a.mk
index 2b9389100..5b4feb7b6 100644
--- a/drivers/staging/renesas/rcar/ddr/ddr_a/ddr_a.mk
+++ b/drivers/staging/renesas/rcar/ddr/ddr_a/ddr_a.mk
@@ -4,4 +4,8 @@
 # SPDX-License-Identifier: BSD-3-Clause
 #
 
+ifeq (${RCAR_LSI},${RCAR_E3})
 BL2_SOURCES += drivers/staging/renesas/rcar/ddr/ddr_a/ddr_init_e3.c
+else
+BL2_SOURCES += drivers/staging/renesas/rcar/ddr/ddr_a/ddr_init_d3.c
+endif
diff --git a/drivers/staging/renesas/rcar/ddr/ddr_a/ddr_init_d3.c b/drivers/staging/renesas/rcar/ddr/ddr_a/ddr_init_d3.c
new file mode 100644
index 000000000..588c57de7
--- /dev/null
+++ b/drivers/staging/renesas/rcar/ddr/ddr_a/ddr_init_d3.c
@@ -0,0 +1,691 @@
+/*
+ * Copyright (c) 2015-2017, Renesas Electronics Corporation. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <stdint.h>
+#include <mmio.h>
+#include <common/debug.h>
+
+#include "boot_init_dram_regdef_d3.h"
+
+#define RCAR_DDR_VERSION    "rev.0.01"
+
+#if RCAR_LSI != RCAR_D3
+#error "Don't have DDR initialize routine."
+#endif
+
+static void    WriteReg_32(uint32_t a, uint32_t v)
+{
+	(*(volatile uint32_t*)(uintptr_t)a) = v;
+}
+
+static uint32_t ReadReg_32(uint32_t a)
+{
+	uint32_t w = (*(volatile uint32_t*)(uintptr_t)a);
+	return w;
+}
+
+static void init_ddr_d3_1866(void)
+{
+	uint32_t RegVal_R2, RegVal_R3, RegVal_R5, RegVal_R6, RegVal_R7, RegVal_R12;
+
+   WriteReg_32(DBSC_D3_DBSYSCNT0,0x00001234);
+   WriteReg_32(DBSC_D3_DBKIND,0x00000007);
+   WriteReg_32(DBSC_D3_DBMEMCONF00,0x0f030a01);
+   WriteReg_32(DBSC_D3_DBPHYCONF0,0x00000001);
+   WriteReg_32(DBSC_D3_DBTR0,0x0000000D);
+   WriteReg_32(DBSC_D3_DBTR1,0x00000009);
+   WriteReg_32(DBSC_D3_DBTR2,0x00000000);
+   WriteReg_32(DBSC_D3_DBTR3,0x0000000D);
+   WriteReg_32(DBSC_D3_DBTR4,0x000D000D);
+   WriteReg_32(DBSC_D3_DBTR5,0x0000002D);
+   WriteReg_32(DBSC_D3_DBTR6,0x00000020);
+   WriteReg_32(DBSC_D3_DBTR7,0x00060006);
+   WriteReg_32(DBSC_D3_DBTR8,0x00000021);
+   WriteReg_32(DBSC_D3_DBTR9,0x00000007);
+   WriteReg_32(DBSC_D3_DBTR10,0x0000000E);
+   WriteReg_32(DBSC_D3_DBTR11,0x0000000C);
+   WriteReg_32(DBSC_D3_DBTR12,0x00140014);
+   WriteReg_32(DBSC_D3_DBTR13,0x000000F2);
+   WriteReg_32(DBSC_D3_DBTR14,0x00170006);
+   WriteReg_32(DBSC_D3_DBTR15,0x00060005);
+   WriteReg_32(DBSC_D3_DBTR16,0x09210507);
+   WriteReg_32(DBSC_D3_DBTR17,0x040E0000);
+   WriteReg_32(DBSC_D3_DBTR18,0x00000200);
+   WriteReg_32(DBSC_D3_DBTR19,0x012B004B);
+   WriteReg_32(DBSC_D3_DBTR20,0x020000FB);
+   WriteReg_32(DBSC_D3_DBTR21,0x00040004);
+   WriteReg_32(DBSC_D3_DBBL,0x00000000);
+   WriteReg_32(DBSC_D3_DBODT0,0x00000001);
+   WriteReg_32(DBSC_D3_DBADJ0,0x00000001);
+   WriteReg_32(DBSC_D3_DBSYSCONF1,0x00000002);
+   WriteReg_32(DBSC_D3_DBDFICNT0,0x00000010);
+   WriteReg_32(DBSC_D3_DBBCAMDIS,0x00000001);
+   WriteReg_32(DBSC_D3_DBSCHRW1,0x00000046);
+   WriteReg_32(DBSC_D3_SCFCTST0,0x0D020D04);
+   WriteReg_32(DBSC_D3_SCFCTST1,0x0306040C);
+
+   WriteReg_32(DBSC_D3_DBPDLK0,0x0000A55A);
+   WriteReg_32(DBSC_D3_DBCMD,0x01000001);
+   WriteReg_32(DBSC_D3_DBCMD,0x08000000);
+   WriteReg_32(DBSC_D3_DBPDRGA0,0x00000001);
+   WriteReg_32(DBSC_D3_DBPDRGD0,0x80010000);
+   WriteReg_32(DBSC_D3_DBPDRGA0,0x00000006);
+   while ( (BIT0 & ReadReg_32(DBSC_D3_DBPDRGD0)) == 0 );
+
+   WriteReg_32(DBSC_D3_DBPDRGA0,0x00000008);
+   WriteReg_32(DBSC_D3_DBPDRGD0,0x000B8000);
+   WriteReg_32(DBSC_D3_DBPDRGA0,0x00000090);
+   WriteReg_32(DBSC_D3_DBPDRGD0,0x04058A04);
+   WriteReg_32(DBSC_D3_DBPDRGA0,0x00000091);
+   WriteReg_32(DBSC_D3_DBPDRGD0,0x0007BB6B);
+   WriteReg_32(DBSC_D3_DBPDRGA0,0x00000095);
+   WriteReg_32(DBSC_D3_DBPDRGD0,0x0007BBAD);
+   WriteReg_32(DBSC_D3_DBPDRGA0,0x00000099);
+   WriteReg_32(DBSC_D3_DBPDRGD0,0x0007BB6B);
+   WriteReg_32(DBSC_D3_DBPDRGA0,0x00000090);
+   WriteReg_32(DBSC_D3_DBPDRGD0,0x04058A00);
+   WriteReg_32(DBSC_D3_DBPDRGA0,0x00000021);
+   WriteReg_32(DBSC_D3_DBPDRGD0,0x0024641E);
+   WriteReg_32(DBSC_D3_DBPDRGA0,0x00000001);
+   WriteReg_32(DBSC_D3_DBPDRGD0,0x00010073);
+   WriteReg_32(DBSC_D3_DBPDRGA0,0x00000006);
+   while ( (BIT0 & ReadReg_32(DBSC_D3_DBPDRGD0)) == 0 );
+
+   WriteReg_32(DBSC_D3_DBPDRGA0,0x00000090);
+   WriteReg_32(DBSC_D3_DBPDRGD0,0x0C058A00);
+   WriteReg_32(DBSC_D3_DBPDRGA0,0x00000090);
+   WriteReg_32(DBSC_D3_DBPDRGD0,0x04058A00);
+   WriteReg_32(DBSC_D3_DBPDRGA0,0x00000006);
+   while ( (BIT0 & ReadReg_32(DBSC_D3_DBPDRGD0)) == 0 );
+
+   WriteReg_32(DBSC_D3_DBPDRGA0,0x00000003);
+   WriteReg_32(DBSC_D3_DBPDRGD0,0x0780C700);
+   WriteReg_32(DBSC_D3_DBPDRGA0,0x00000007);
+   while ( (BIT30 & ReadReg_32(DBSC_D3_DBPDRGD0)) == 0 );
+
+   WriteReg_32(DBSC_D3_DBPDRGA0,0x00000004);
+   WriteReg_32(DBSC_D3_DBPDRGD0,0x0A206F89);
+   WriteReg_32(DBSC_D3_DBPDRGA0,0x00000022);
+   WriteReg_32(DBSC_D3_DBPDRGD0,0x1000040B);
+   WriteReg_32(DBSC_D3_DBPDRGA0,0x00000023);
+   WriteReg_32(DBSC_D3_DBPDRGD0,0x35A00D77);
+   WriteReg_32(DBSC_D3_DBPDRGA0,0x00000024);
+   WriteReg_32(DBSC_D3_DBPDRGD0,0x2A8A2C28);
+   WriteReg_32(DBSC_D3_DBPDRGA0,0x00000025);
+   WriteReg_32(DBSC_D3_DBPDRGD0,0x30005E00);
+   WriteReg_32(DBSC_D3_DBPDRGA0,0x00000026);
+   WriteReg_32(DBSC_D3_DBPDRGD0,0x0014CB49);
+   WriteReg_32(DBSC_D3_DBPDRGA0,0x00000027);
+   WriteReg_32(DBSC_D3_DBPDRGD0,0x00000F14);
+   WriteReg_32(DBSC_D3_DBPDRGA0,0x00000028);
+   WriteReg_32(DBSC_D3_DBPDRGD0,0x00000046);
+   WriteReg_32(DBSC_D3_DBPDRGA0,0x00000029);
+   WriteReg_32(DBSC_D3_DBPDRGD0,0x000000A0);
+   WriteReg_32(DBSC_D3_DBPDRGA0,0x0000002C);
+   WriteReg_32(DBSC_D3_DBPDRGD0,0x81003047);
+   WriteReg_32(DBSC_D3_DBPDRGA0,0x00000020);
+   WriteReg_32(DBSC_D3_DBPDRGD0,0x00181884);
+   WriteReg_32(DBSC_D3_DBPDRGA0,0x0000001A);
+   WriteReg_32(DBSC_D3_DBPDRGD0,0x33C03C10);
+   WriteReg_32(DBSC_D3_DBPDRGA0,0x00000006);
+   while ( (BIT0 & ReadReg_32(DBSC_D3_DBPDRGD0)) == 0 );
+
+   WriteReg_32(DBSC_D3_DBPDRGA0,0x000000A7);
+   WriteReg_32(DBSC_D3_DBPDRGD0,0x0D0D0D0D);
+   WriteReg_32(DBSC_D3_DBPDRGA0,0x000000A8);
+   WriteReg_32(DBSC_D3_DBPDRGD0,0x0D0D0D0D);
+   WriteReg_32(DBSC_D3_DBPDRGA0,0x000000A9);
+   WriteReg_32(DBSC_D3_DBPDRGD0,0x000D0D0D);
+   WriteReg_32(DBSC_D3_DBPDRGA0,0x000000C7);
+   WriteReg_32(DBSC_D3_DBPDRGD0,0x0D0D0D0D);
+   WriteReg_32(DBSC_D3_DBPDRGA0,0x000000C8);
+   WriteReg_32(DBSC_D3_DBPDRGD0,0x0D0D0D0D);
+   WriteReg_32(DBSC_D3_DBPDRGA0,0x000000C9);
+   WriteReg_32(DBSC_D3_DBPDRGD0,0x000D0D0D);
+
+   WriteReg_32(DBSC_D3_DBPDRGA0,0x0000000E);
+   RegVal_R2 = ((ReadReg_32(DBSC_D3_DBPDRGD0) & 0x0000FF00) >> 0x8) >> 0x1;
+   RegVal_R3 = (RegVal_R2 << 16) + (RegVal_R2 << 8) + RegVal_R2;
+   RegVal_R6 = (RegVal_R2 << 24) + (RegVal_R2 << 16) + (RegVal_R2 << 8) + RegVal_R2;
+   WriteReg_32(DBSC_D3_DBPDRGA0,0x00000011);
+   WriteReg_32(DBSC_D3_DBPDRGD0,RegVal_R3);
+   WriteReg_32(DBSC_D3_DBPDRGA0,0x00000012);
+   WriteReg_32(DBSC_D3_DBPDRGD0,RegVal_R3);
+   WriteReg_32(DBSC_D3_DBPDRGA0,0x00000016);
+   WriteReg_32(DBSC_D3_DBPDRGD0,RegVal_R6);
+   WriteReg_32(DBSC_D3_DBPDRGA0,0x00000017);
+   WriteReg_32(DBSC_D3_DBPDRGD0,RegVal_R6);
+   WriteReg_32(DBSC_D3_DBPDRGA0,0x00000018);
+   WriteReg_32(DBSC_D3_DBPDRGD0,RegVal_R6);
+   WriteReg_32(DBSC_D3_DBPDRGA0,0x00000019);
+   WriteReg_32(DBSC_D3_DBPDRGD0,RegVal_R6);
+
+   WriteReg_32(DBSC_D3_DBPDRGA0,0x00000001);
+   WriteReg_32(DBSC_D3_DBPDRGD0,0x00010181);
+   WriteReg_32(DBSC_D3_DBCMD,0x08000001);
+   WriteReg_32(DBSC_D3_DBPDRGA0,0x00000006);
+   while ( (BIT0 & ReadReg_32(DBSC_D3_DBPDRGD0)) == 0 );
+
+   WriteReg_32(DBSC_D3_DBPDRGA0,0x00000001);
+   WriteReg_32(DBSC_D3_DBPDRGD0,0x00010601);
+   WriteReg_32(DBSC_D3_DBPDRGA0,0x00000006);
+   while ( (BIT0 & ReadReg_32(DBSC_D3_DBPDRGD0)) == 0 );
+
+   for (uint32_t i = 0; i<2; i++)
+   {
+      WriteReg_32(DBSC_D3_DBPDRGA0,0x000000B1 + i*0x20);
+      RegVal_R5 = (ReadReg_32(DBSC_D3_DBPDRGD0) & 0x0000FF00) >> 0x8;
+      WriteReg_32(DBSC_D3_DBPDRGA0,0x000000B4 + i*0x20);
+      RegVal_R6 = (ReadReg_32(DBSC_D3_DBPDRGD0) & 0x000000FF);
+      WriteReg_32(DBSC_D3_DBPDRGA0,0x000000B3 + i*0x20);
+      RegVal_R7 = (ReadReg_32(DBSC_D3_DBPDRGD0) & 0x00000007);
+      if ( RegVal_R6 > 0 )
+      {
+         WriteReg_32(DBSC_D3_DBPDRGA0,0x000000B2 + i*0x20);
+         RegVal_R2 = (ReadReg_32(DBSC_D3_DBPDRGD0) & 0xFFFFFFF8);
+
+         WriteReg_32(DBSC_D3_DBPDRGA0,0x000000B2 + i*0x20);
+         WriteReg_32(DBSC_D3_DBPDRGD0,RegVal_R2 | ((RegVal_R7 + 0x1) & 0x00000007));
+         WriteReg_32(DBSC_D3_DBPDRGA0,0x000000B0 + i*0x20);
+         RegVal_R2 = (ReadReg_32(DBSC_D3_DBPDRGD0) & 0xFFFFFF00);
+         WriteReg_32(DBSC_D3_DBPDRGA0,0x000000B0 + i*0x20);
+         WriteReg_32(DBSC_D3_DBPDRGD0,RegVal_R2 | RegVal_R6);
+      } else 
+      {
+         WriteReg_32(DBSC_D3_DBPDRGA0,0x000000B2 + i*0x20);
+         RegVal_R2 = (ReadReg_32(DBSC_D3_DBPDRGD0) & 0xFFFFFFF8);
+         WriteReg_32(DBSC_D3_DBPDRGA0,0x000000B2 + i*0x20);
+         WriteReg_32(DBSC_D3_DBPDRGD0,RegVal_R2 | RegVal_R7);
+
+         WriteReg_32(DBSC_D3_DBPDRGA0,0x000000B0 + i*0x20);
+         RegVal_R2 = (ReadReg_32(DBSC_D3_DBPDRGD0) & 0xFFFFFF00);
+         WriteReg_32(DBSC_D3_DBPDRGA0,0x000000B0 + i*0x20);
+         WriteReg_32(DBSC_D3_DBPDRGD0,RegVal_R2 | ((RegVal_R6 + ((RegVal_R5) << 1)) & 0x000000FF));
+      }
+   }
+
+   WriteReg_32(DBSC_D3_DBPDRGA0,0x00000005);
+   WriteReg_32(DBSC_D3_DBPDRGD0,0xC1AA00C0);
+   WriteReg_32(DBSC_D3_DBPDRGA0,0x000000A0);
+   WriteReg_32(DBSC_D3_DBPDRGD0,0x7C0002C5);
+   WriteReg_32(DBSC_D3_DBPDRGA0,0x000000C0);
+   WriteReg_32(DBSC_D3_DBPDRGD0,0x7C0002C5);
+   WriteReg_32(DBSC_D3_DBPDRGA0,0x00000001);
+   WriteReg_32(DBSC_D3_DBPDRGD0,0x00010801);
+   WriteReg_32(DBSC_D3_DBPDRGA0,0x00000006);
+   while ( (BIT0 & ReadReg_32(DBSC_D3_DBPDRGD0)) == 0 );
+
+   WriteReg_32(DBSC_D3_DBPDRGA0,0x00000005);
+   WriteReg_32(DBSC_D3_DBPDRGD0,0xC1AA00D8);
+   WriteReg_32(DBSC_D3_DBPDRGA0,0x00000001);
+   WriteReg_32(DBSC_D3_DBPDRGD0,0x0001F001);
+   WriteReg_32(DBSC_D3_DBPDRGA0,0x00000006);
+   while ( (BIT0 & ReadReg_32(DBSC_D3_DBPDRGD0)) == 0 );
+
+   WriteReg_32(DBSC_D3_DBPDRGA0,0x000000AF);
+   RegVal_R2 = ReadReg_32(DBSC_D3_DBPDRGD0);
+   WriteReg_32(DBSC_D3_DBPDRGD0,(((RegVal_R2 + 0x1) & 0x000000FF) | (RegVal_R2 & 0xFFFFFF00)));
+   WriteReg_32(DBSC_D3_DBPDRGA0,0x000000CF);
+   RegVal_R2 = ReadReg_32(DBSC_D3_DBPDRGD0);
+   WriteReg_32(DBSC_D3_DBPDRGD0,(((RegVal_R2 + 0x1) & 0x000000FF) | (RegVal_R2 & 0xFFFFFF00)));
+
+   WriteReg_32(DBSC_D3_DBPDRGA0,0x000000A0);
+   WriteReg_32(DBSC_D3_DBPDRGD0,0x7C000285);
+   WriteReg_32(DBSC_D3_DBPDRGA0,0x000000C0);
+   WriteReg_32(DBSC_D3_DBPDRGD0,0x7C000285);
+   WriteReg_32(DBSC_D3_DBPDRGA0,0x0000002C);
+   WriteReg_32(DBSC_D3_DBPDRGD0,0x81003087);
+   WriteReg_32(DBSC_D3_DBPDRGA0,0x00000001);
+   WriteReg_32(DBSC_D3_DBPDRGD0,0x00010401);
+   WriteReg_32(DBSC_D3_DBPDRGA0,0x00000006);
+   while ( (BIT0 & ReadReg_32(DBSC_D3_DBPDRGD0)) == 0 );
+
+   for (uint32_t i = 0; i < 2; i++)
+   {
+      WriteReg_32(DBSC_D3_DBPDRGA0,0x000000B1 + i*0x20);
+      RegVal_R5 = ((ReadReg_32(DBSC_D3_DBPDRGD0) & 0x0000FF00) >> 0x8);
+      WriteReg_32(DBSC_D3_DBPDRGA0,0x000000B4 + i*0x20);
+      RegVal_R6 = (ReadReg_32(DBSC_D3_DBPDRGD0) & 0x000000FF);
+
+      WriteReg_32(DBSC_D3_DBPDRGA0,0x000000B3 + i*0x20);
+      RegVal_R7 = (ReadReg_32(DBSC_D3_DBPDRGD0) & 0x00000007);
+      RegVal_R12 = (RegVal_R5 >> 0x2);
+      if ( RegVal_R12 < RegVal_R6 )
+      {
+         WriteReg_32(DBSC_D3_DBPDRGA0,0x000000B2 + i*0x20);
+         RegVal_R2 = (ReadReg_32(DBSC_D3_DBPDRGD0) & 0xFFFFFFF8);
+
+         WriteReg_32(DBSC_D3_DBPDRGA0,0x000000B2 + i*0x20);
+         WriteReg_32(DBSC_D3_DBPDRGD0,RegVal_R2 | ((RegVal_R7 + 0x1) & 0x00000007));
+         WriteReg_32(DBSC_D3_DBPDRGA0,0x000000B0 + i*0x20);
+         RegVal_R2 = (ReadReg_32(DBSC_D3_DBPDRGD0) & 0xFFFFFF00);
+
+         WriteReg_32(DBSC_D3_DBPDRGA0,0x000000B0 + i*0x20);
+         WriteReg_32(DBSC_D3_DBPDRGD0,RegVal_R2 | ((RegVal_R6 - (RegVal_R12)) & 0x000000FF));
+      }
+      else
+      {
+         WriteReg_32(DBSC_D3_DBPDRGA0,0x000000B2 + i*0x20);
+         RegVal_R2 = (ReadReg_32(DBSC_D3_DBPDRGD0) & 0xFFFFFFF8);
+         WriteReg_32(DBSC_D3_DBPDRGA0,0x000000B2 + i*0x20);
+         WriteReg_32(DBSC_D3_DBPDRGD0,RegVal_R2 | (RegVal_R7 & 0x00000007));
+         WriteReg_32(DBSC_D3_DBPDRGA0,0x000000B0 + i*0x20);
+         RegVal_R2 = (ReadReg_32(DBSC_D3_DBPDRGD0) & 0xFFFFFF00);
+         WriteReg_32(DBSC_D3_DBPDRGA0,0x000000B0 + i*0x20);
+         WriteReg_32(DBSC_D3_DBPDRGD0,RegVal_R2 | ((RegVal_R6 + (RegVal_R5) + ((RegVal_R5) >> 1) + (RegVal_R12)) & 0x000000FF));
+      }
+   }
+
+   WriteReg_32(DBSC_D3_DBPDRGA0,0x000000A0);
+   WriteReg_32(DBSC_D3_DBPDRGD0,0x7C0002C5);
+   WriteReg_32(DBSC_D3_DBPDRGA0,0x000000C0);
+   WriteReg_32(DBSC_D3_DBPDRGD0,0x7C0002C5);
+   WriteReg_32(DBSC_D3_DBPDRGA0,0x00000001);
+   WriteReg_32(DBSC_D3_DBPDRGD0,0x00015001);
+   WriteReg_32(DBSC_D3_DBPDRGA0,0x00000006);
+   while ( (BIT0 & ReadReg_32(DBSC_D3_DBPDRGD0)) == 0 );
+
+   WriteReg_32(DBSC_D3_DBPDRGA0,0x00000003);
+   WriteReg_32(DBSC_D3_DBPDRGD0,0x0380C700);
+   WriteReg_32(DBSC_D3_DBPDRGA0,0x00000007);
+   while ( (BIT30 & ReadReg_32(DBSC_D3_DBPDRGD0)) != 0 );
+   WriteReg_32(DBSC_D3_DBPDRGA0,0x00000021);
+   WriteReg_32(DBSC_D3_DBPDRGD0,0x0024643E);
+
+   WriteReg_32(DBSC_D3_DBBUS0CNF1,0x00000010);
+   WriteReg_32(DBSC_D3_DBCALCNF,0x0100401B);
+   WriteReg_32(DBSC_D3_DBRFCNF1,0x00080E23);
+   WriteReg_32(DBSC_D3_DBRFCNF2,0x00010000);
+   WriteReg_32(DBSC_D3_DBDFICUPDCNF,0x40100001);
+   WriteReg_32(DBSC_D3_DBRFEN,0x00000001);
+   WriteReg_32(DBSC_D3_DBACEN,0x00000001);
+   WriteReg_32(DBSC_D3_DBPDLK0,0x00000000);
+   WriteReg_32(DBSC_D3_DBSYSCNT0,0x00000000);
+
+#ifdef ddr_qos_init_setting // only for non qos_init
+   WriteReg_32(DBSC_D3_DBSYSCNT0,0x00001234);
+   WriteReg_32(DBSC_D3_DBCAM0CNF1,0x00043218);
+   WriteReg_32(DBSC_D3_DBCAM0CNF2,0x000000F4);
+   WriteReg_32(DBSC_D3_DBSCHCNT0,0x000f0037);
+   WriteReg_32(DBSC_D3_DBSCHSZ0,0x00000001);
+   WriteReg_32(DBSC_D3_DBSCHRW0,0x22421111);
+   WriteReg_32(DBSC_D3_SCFCTST2,0x012F1123);
+   WriteReg_32(DBSC_D3_DBSCHQOS00,0x00000F00);
+   WriteReg_32(DBSC_D3_DBSCHQOS01,0x00000B00);
+   WriteReg_32(DBSC_D3_DBSCHQOS02,0x00000000);
+   WriteReg_32(DBSC_D3_DBSCHQOS03,0x00000000);
+   WriteReg_32(DBSC_D3_DBSCHQOS40,0x00000300);
+   WriteReg_32(DBSC_D3_DBSCHQOS41,0x000002F0);
+   WriteReg_32(DBSC_D3_DBSCHQOS42,0x00000200);
+   WriteReg_32(DBSC_D3_DBSCHQOS43,0x00000100);
+   WriteReg_32(DBSC_D3_DBSCHQOS90,0x00000300);
+   WriteReg_32(DBSC_D3_DBSCHQOS91,0x000002F0);
+   WriteReg_32(DBSC_D3_DBSCHQOS92,0x00000200);
+   WriteReg_32(DBSC_D3_DBSCHQOS93,0x00000100);
+   WriteReg_32(DBSC_D3_DBSCHQOS130,0x00000100);
+   WriteReg_32(DBSC_D3_DBSCHQOS131,0x000000F0);
+   WriteReg_32(DBSC_D3_DBSCHQOS132,0x000000A0);
+   WriteReg_32(DBSC_D3_DBSCHQOS133,0x00000040);
+   WriteReg_32(DBSC_D3_DBSCHQOS140,0x000000C0);
+   WriteReg_32(DBSC_D3_DBSCHQOS141,0x000000B0);
+   WriteReg_32(DBSC_D3_DBSCHQOS142,0x00000080);
+   WriteReg_32(DBSC_D3_DBSCHQOS143,0x00000040);
+   WriteReg_32(DBSC_D3_DBSCHQOS150,0x00000040);
+   WriteReg_32(DBSC_D3_DBSCHQOS151,0x00000030);
+   WriteReg_32(DBSC_D3_DBSCHQOS152,0x00000020);
+   WriteReg_32(DBSC_D3_DBSCHQOS153,0x00000010);
+   WriteReg_32(0xE67F0018,0x00000001);
+   WriteReg_32(DBSC_D3_DBSYSCNT0,0x00000000);
+#endif
+}
+
+static void init_ddr_d3_1600(void)
+{
+	uint32_t RegVal_R2, RegVal_R3, RegVal_R5, RegVal_R6, RegVal_R7, RegVal_R12;
+
+   WriteReg_32(DBSC_D3_DBSYSCNT0,0x00001234);
+   WriteReg_32(DBSC_D3_DBKIND,0x00000007);
+   WriteReg_32(DBSC_D3_DBMEMCONF00,0x0f030a01);
+   WriteReg_32(DBSC_D3_DBPHYCONF0,0x00000001);
+   WriteReg_32(DBSC_D3_DBTR0,0x0000000B);
+   WriteReg_32(DBSC_D3_DBTR1,0x00000008);
+   WriteReg_32(DBSC_D3_DBTR2,0x00000000);
+   WriteReg_32(DBSC_D3_DBTR3,0x0000000B);
+   WriteReg_32(DBSC_D3_DBTR4,0x000B000B);
+   WriteReg_32(DBSC_D3_DBTR5,0x00000027);
+   WriteReg_32(DBSC_D3_DBTR6,0x0000001C);
+   WriteReg_32(DBSC_D3_DBTR7,0x00060006);
+   WriteReg_32(DBSC_D3_DBTR8,0x00000020);
+   WriteReg_32(DBSC_D3_DBTR9,0x00000006);
+   WriteReg_32(DBSC_D3_DBTR10,0x0000000C);
+   WriteReg_32(DBSC_D3_DBTR11,0x0000000A);
+   WriteReg_32(DBSC_D3_DBTR12,0x00120012);
+   WriteReg_32(DBSC_D3_DBTR13,0x000000D0);
+   WriteReg_32(DBSC_D3_DBTR14,0x00140005);
+   WriteReg_32(DBSC_D3_DBTR15,0x00050004);
+   WriteReg_32(DBSC_D3_DBTR16,0x071F0305);
+   WriteReg_32(DBSC_D3_DBTR17,0x040C0000);
+   WriteReg_32(DBSC_D3_DBTR18,0x00000200);
+   WriteReg_32(DBSC_D3_DBTR19,0x01000040);
+   WriteReg_32(DBSC_D3_DBTR20,0x020000D8);
+   WriteReg_32(DBSC_D3_DBTR21,0x00040004);
+   WriteReg_32(DBSC_D3_DBBL,0x00000000);
+   WriteReg_32(DBSC_D3_DBODT0,0x00000001);
+   WriteReg_32(DBSC_D3_DBADJ0,0x00000001);
+   WriteReg_32(DBSC_D3_DBSYSCONF1,0x00000002);
+   WriteReg_32(DBSC_D3_DBDFICNT0,0x00000010);
+   WriteReg_32(DBSC_D3_DBBCAMDIS,0x00000001);
+   WriteReg_32(DBSC_D3_DBSCHRW1,0x00000046);
+   WriteReg_32(DBSC_D3_SCFCTST0,0x0D020C04);
+   WriteReg_32(DBSC_D3_SCFCTST1,0x0305040C);
+
+   WriteReg_32(DBSC_D3_DBPDLK0,0x0000A55A);
+   WriteReg_32(DBSC_D3_DBCMD,0x01000001);
+   WriteReg_32(DBSC_D3_DBCMD,0x08000000);
+   WriteReg_32(DBSC_D3_DBPDRGA0,0x00000001);
+   WriteReg_32(DBSC_D3_DBPDRGD0,0x80010000);
+   WriteReg_32(DBSC_D3_DBPDRGA0,0x00000006);
+   while ( (BIT0 & ReadReg_32(DBSC_D3_DBPDRGD0)) == 0 );
+
+   WriteReg_32(DBSC_D3_DBPDRGA0,0x00000008);
+   WriteReg_32(DBSC_D3_DBPDRGD0,0x000B8000);
+   WriteReg_32(DBSC_D3_DBPDRGA0,0x00000090);
+   WriteReg_32(DBSC_D3_DBPDRGD0,0x04058904);
+   WriteReg_32(DBSC_D3_DBPDRGA0,0x00000091);
+   WriteReg_32(DBSC_D3_DBPDRGD0,0x0007BB6B);
+   WriteReg_32(DBSC_D3_DBPDRGA0,0x00000095);
+   WriteReg_32(DBSC_D3_DBPDRGD0,0x0007BBAD);
+   WriteReg_32(DBSC_D3_DBPDRGA0,0x00000099);
+   WriteReg_32(DBSC_D3_DBPDRGD0,0x0007BB6B);
+   WriteReg_32(DBSC_D3_DBPDRGA0,0x00000090);
+   WriteReg_32(DBSC_D3_DBPDRGD0,0x04058900);
+   WriteReg_32(DBSC_D3_DBPDRGA0,0x00000021);
+   WriteReg_32(DBSC_D3_DBPDRGD0,0x0024641E);
+   WriteReg_32(DBSC_D3_DBPDRGA0,0x00000001);
+   WriteReg_32(DBSC_D3_DBPDRGD0,0x00010073);
+   WriteReg_32(DBSC_D3_DBPDRGA0,0x00000006);
+   while ( (BIT0 & ReadReg_32(DBSC_D3_DBPDRGD0)) == 0 );
+
+   WriteReg_32(DBSC_D3_DBPDRGA0,0x00000090);
+   WriteReg_32(DBSC_D3_DBPDRGD0,0x0C058900);
+   WriteReg_32(DBSC_D3_DBPDRGA0,0x00000090);
+   WriteReg_32(DBSC_D3_DBPDRGD0,0x04058900);
+   WriteReg_32(DBSC_D3_DBPDRGA0,0x00000006);
+   while ( (BIT0 & ReadReg_32(DBSC_D3_DBPDRGD0)) == 0 );
+
+   WriteReg_32(DBSC_D3_DBPDRGA0,0x00000003);
+   WriteReg_32(DBSC_D3_DBPDRGD0,0x0780C700);
+   WriteReg_32(DBSC_D3_DBPDRGA0,0x00000007);
+   while ( (BIT30 & ReadReg_32(DBSC_D3_DBPDRGD0)) == 0 );
+
+   WriteReg_32(DBSC_D3_DBPDRGA0,0x00000004);
+   WriteReg_32(DBSC_D3_DBPDRGD0,0x08C05FF0);
+   WriteReg_32(DBSC_D3_DBPDRGA0,0x00000022);
+   WriteReg_32(DBSC_D3_DBPDRGD0,0x1000040B);
+   WriteReg_32(DBSC_D3_DBPDRGA0,0x00000023);
+   WriteReg_32(DBSC_D3_DBPDRGD0,0x2D9C0B66);
+   WriteReg_32(DBSC_D3_DBPDRGA0,0x00000024);
+   WriteReg_32(DBSC_D3_DBPDRGD0,0x2A88C400);
+   WriteReg_32(DBSC_D3_DBPDRGA0,0x00000025);
+   WriteReg_32(DBSC_D3_DBPDRGD0,0x30005200);
+   WriteReg_32(DBSC_D3_DBPDRGA0,0x00000026);
+   WriteReg_32(DBSC_D3_DBPDRGD0,0x0014A9C9);
+   WriteReg_32(DBSC_D3_DBPDRGA0,0x00000027);
+   WriteReg_32(DBSC_D3_DBPDRGD0,0x00000D70);
+   WriteReg_32(DBSC_D3_DBPDRGA0,0x00000028);
+   WriteReg_32(DBSC_D3_DBPDRGD0,0x00000046);
+   WriteReg_32(DBSC_D3_DBPDRGA0,0x00000029);
+   WriteReg_32(DBSC_D3_DBPDRGD0,0x00000098);
+   WriteReg_32(DBSC_D3_DBPDRGA0,0x0000002C);
+   WriteReg_32(DBSC_D3_DBPDRGD0,0x81003047);
+   WriteReg_32(DBSC_D3_DBPDRGA0,0x00000020);
+   WriteReg_32(DBSC_D3_DBPDRGD0,0x00181884);
+   WriteReg_32(DBSC_D3_DBPDRGA0,0x0000001A);
+   WriteReg_32(DBSC_D3_DBPDRGD0,0x33C03C10);
+   WriteReg_32(DBSC_D3_DBPDRGA0,0x00000006);
+   while ( (BIT0 & ReadReg_32(DBSC_D3_DBPDRGD0)) == 0 );
+
+   WriteReg_32(DBSC_D3_DBPDRGA0,0x000000A7);
+   WriteReg_32(DBSC_D3_DBPDRGD0,0x0D0D0D0D);
+   WriteReg_32(DBSC_D3_DBPDRGA0,0x000000A8);
+   WriteReg_32(DBSC_D3_DBPDRGD0,0x0D0D0D0D);
+   WriteReg_32(DBSC_D3_DBPDRGA0,0x000000A9);
+   WriteReg_32(DBSC_D3_DBPDRGD0,0x000D0D0D);
+   WriteReg_32(DBSC_D3_DBPDRGA0,0x000000C7);
+   WriteReg_32(DBSC_D3_DBPDRGD0,0x0D0D0D0D);
+   WriteReg_32(DBSC_D3_DBPDRGA0,0x000000C8);
+   WriteReg_32(DBSC_D3_DBPDRGD0,0x0D0D0D0D);
+   WriteReg_32(DBSC_D3_DBPDRGA0,0x000000C9);
+   WriteReg_32(DBSC_D3_DBPDRGD0,0x000D0D0D);
+
+   WriteReg_32(DBSC_D3_DBPDRGA0,0x0000000E);
+   RegVal_R2 = ((ReadReg_32(DBSC_D3_DBPDRGD0) & 0x0000FF00) >> 0x8) >> 0x1;
+   RegVal_R3 = (RegVal_R2 << 16) + (RegVal_R2 << 8) + RegVal_R2;
+   RegVal_R6 = (RegVal_R2 << 24) + (RegVal_R2 << 16) + (RegVal_R2 << 8) + RegVal_R2;
+   WriteReg_32(DBSC_D3_DBPDRGA0,0x00000011);
+   WriteReg_32(DBSC_D3_DBPDRGD0,RegVal_R3);
+   WriteReg_32(DBSC_D3_DBPDRGA0,0x00000012);
+   WriteReg_32(DBSC_D3_DBPDRGD0,RegVal_R3);
+   WriteReg_32(DBSC_D3_DBPDRGA0,0x00000016);
+   WriteReg_32(DBSC_D3_DBPDRGD0,RegVal_R6);
+   WriteReg_32(DBSC_D3_DBPDRGA0,0x00000017);
+   WriteReg_32(DBSC_D3_DBPDRGD0,RegVal_R6);
+   WriteReg_32(DBSC_D3_DBPDRGA0,0x00000018);
+   WriteReg_32(DBSC_D3_DBPDRGD0,RegVal_R6);
+   WriteReg_32(DBSC_D3_DBPDRGA0,0x00000019);
+   WriteReg_32(DBSC_D3_DBPDRGD0,RegVal_R6);
+
+   WriteReg_32(DBSC_D3_DBPDRGA0,0x00000001);
+   WriteReg_32(DBSC_D3_DBPDRGD0,0x00010181);
+   WriteReg_32(DBSC_D3_DBCMD,0x08000001);
+   WriteReg_32(DBSC_D3_DBPDRGA0,0x00000006);
+   while ( (BIT0 & ReadReg_32(DBSC_D3_DBPDRGD0)) == 0 );
+
+   WriteReg_32(DBSC_D3_DBPDRGA0,0x00000001);
+   WriteReg_32(DBSC_D3_DBPDRGD0,0x00010601);
+   WriteReg_32(DBSC_D3_DBPDRGA0,0x00000006);
+   while ( (BIT0 & ReadReg_32(DBSC_D3_DBPDRGD0)) == 0 );
+
+   for (uint32_t i = 0; i<2; i++)
+   {
+      WriteReg_32(DBSC_D3_DBPDRGA0,0x000000B1 + i*0x20);
+      RegVal_R5 = (ReadReg_32(DBSC_D3_DBPDRGD0) & 0x0000FF00) >> 0x8;
+      WriteReg_32(DBSC_D3_DBPDRGA0,0x000000B4 + i*0x20);
+      RegVal_R6 = (ReadReg_32(DBSC_D3_DBPDRGD0) & 0x000000FF);
+      WriteReg_32(DBSC_D3_DBPDRGA0,0x000000B3 + i*0x20);
+      RegVal_R7 = (ReadReg_32(DBSC_D3_DBPDRGD0) & 0x00000007);
+      if ( RegVal_R6 > 0 )
+      {
+         WriteReg_32(DBSC_D3_DBPDRGA0,0x000000B2 + i*0x20);
+         RegVal_R2 = (ReadReg_32(DBSC_D3_DBPDRGD0) & 0xFFFFFFF8);
+
+         WriteReg_32(DBSC_D3_DBPDRGA0,0x000000B2 + i*0x20);
+         WriteReg_32(DBSC_D3_DBPDRGD0,RegVal_R2 | ((RegVal_R7 + 0x1) & 0x00000007));
+         WriteReg_32(DBSC_D3_DBPDRGA0,0x000000B0 + i*0x20);
+         RegVal_R2 = (ReadReg_32(DBSC_D3_DBPDRGD0) & 0xFFFFFF00);
+         WriteReg_32(DBSC_D3_DBPDRGA0,0x000000B0 + i*0x20);
+         WriteReg_32(DBSC_D3_DBPDRGD0,RegVal_R2 | RegVal_R6);
+      } else 
+      {
+         WriteReg_32(DBSC_D3_DBPDRGA0,0x000000B2 + i*0x20);
+         RegVal_R2 = (ReadReg_32(DBSC_D3_DBPDRGD0) & 0xFFFFFFF8);
+         WriteReg_32(DBSC_D3_DBPDRGA0,0x000000B2 + i*0x20);
+         WriteReg_32(DBSC_D3_DBPDRGD0,RegVal_R2 | RegVal_R7);
+
+         WriteReg_32(DBSC_D3_DBPDRGA0,0x000000B0 + i*0x20);
+         RegVal_R2 = (ReadReg_32(DBSC_D3_DBPDRGD0) & 0xFFFFFF00);
+         WriteReg_32(DBSC_D3_DBPDRGA0,0x000000B0 + i*0x20);
+         WriteReg_32(DBSC_D3_DBPDRGD0,RegVal_R2 | ((RegVal_R6 + ((RegVal_R5) << 1)) & 0x000000FF));
+      }
+   }
+
+   WriteReg_32(DBSC_D3_DBPDRGA0,0x00000005);
+   WriteReg_32(DBSC_D3_DBPDRGD0,0xC1AA00C0);
+   WriteReg_32(DBSC_D3_DBPDRGA0,0x000000A0);
+   WriteReg_32(DBSC_D3_DBPDRGD0,0x7C0002C5);
+   WriteReg_32(DBSC_D3_DBPDRGA0,0x000000C0);
+   WriteReg_32(DBSC_D3_DBPDRGD0,0x7C0002C5);
+   WriteReg_32(DBSC_D3_DBPDRGA0,0x00000001);
+   WriteReg_32(DBSC_D3_DBPDRGD0,0x00010801);
+   WriteReg_32(DBSC_D3_DBPDRGA0,0x00000006);
+   while ( (BIT0 & ReadReg_32(DBSC_D3_DBPDRGD0)) == 0 );
+
+   WriteReg_32(DBSC_D3_DBPDRGA0,0x00000005);
+   WriteReg_32(DBSC_D3_DBPDRGD0,0xC1AA00D8);
+   WriteReg_32(DBSC_D3_DBPDRGA0,0x00000001);
+   WriteReg_32(DBSC_D3_DBPDRGD0,0x0001F001);
+   WriteReg_32(DBSC_D3_DBPDRGA0,0x00000006);
+   while ( (BIT0 & ReadReg_32(DBSC_D3_DBPDRGD0)) == 0 );
+
+   WriteReg_32(DBSC_D3_DBPDRGA0,0x000000AF);
+   RegVal_R2 = ReadReg_32(DBSC_D3_DBPDRGD0);
+   WriteReg_32(DBSC_D3_DBPDRGD0,(((RegVal_R2 + 0x1) & 0x000000FF) | (RegVal_R2 & 0xFFFFFF00)));
+   WriteReg_32(DBSC_D3_DBPDRGA0,0x000000CF);
+   RegVal_R2 = ReadReg_32(DBSC_D3_DBPDRGD0);
+   WriteReg_32(DBSC_D3_DBPDRGD0,(((RegVal_R2 + 0x1) & 0x000000FF) | (RegVal_R2 & 0xFFFFFF00)));
+
+   WriteReg_32(DBSC_D3_DBPDRGA0,0x000000A0);
+   WriteReg_32(DBSC_D3_DBPDRGD0,0x7C000285);
+   WriteReg_32(DBSC_D3_DBPDRGA0,0x000000C0);
+   WriteReg_32(DBSC_D3_DBPDRGD0,0x7C000285);
+   WriteReg_32(DBSC_D3_DBPDRGA0,0x0000002C);
+   WriteReg_32(DBSC_D3_DBPDRGD0,0x81003087);
+   WriteReg_32(DBSC_D3_DBPDRGA0,0x00000001);
+   WriteReg_32(DBSC_D3_DBPDRGD0,0x00010401);
+   WriteReg_32(DBSC_D3_DBPDRGA0,0x00000006);
+   while ( (BIT0 & ReadReg_32(DBSC_D3_DBPDRGD0)) == 0 );
+
+   for (uint32_t i = 0; i < 2; i++)
+   {
+      WriteReg_32(DBSC_D3_DBPDRGA0,0x000000B1 + i*0x20);
+      RegVal_R5 = ((ReadReg_32(DBSC_D3_DBPDRGD0) & 0x0000FF00) >> 0x8);
+      WriteReg_32(DBSC_D3_DBPDRGA0,0x000000B4 + i*0x20);
+      RegVal_R6 = (ReadReg_32(DBSC_D3_DBPDRGD0) & 0x000000FF);
+
+      WriteReg_32(DBSC_D3_DBPDRGA0,0x000000B3 + i*0x20);
+      RegVal_R7 = (ReadReg_32(DBSC_D3_DBPDRGD0) & 0x00000007);
+      RegVal_R12 = (RegVal_R5 >> 0x2);
+      if ( RegVal_R12 < RegVal_R6 )
+      {
+         WriteReg_32(DBSC_D3_DBPDRGA0,0x000000B2 + i*0x20);
+         RegVal_R2 = (ReadReg_32(DBSC_D3_DBPDRGD0) & 0xFFFFFFF8);
+
+         WriteReg_32(DBSC_D3_DBPDRGA0,0x000000B2 + i*0x20);
+         WriteReg_32(DBSC_D3_DBPDRGD0,RegVal_R2 | ((RegVal_R7 + 0x1) & 0x00000007));
+         WriteReg_32(DBSC_D3_DBPDRGA0,0x000000B0 + i*0x20);
+         RegVal_R2 = (ReadReg_32(DBSC_D3_DBPDRGD0) & 0xFFFFFF00);
+
+         WriteReg_32(DBSC_D3_DBPDRGA0,0x000000B0 + i*0x20);
+         WriteReg_32(DBSC_D3_DBPDRGD0,RegVal_R2 | ((RegVal_R6 - (RegVal_R12)) & 0x000000FF));
+      }
+      else
+      {
+         WriteReg_32(DBSC_D3_DBPDRGA0,0x000000B2 + i*0x20);
+         RegVal_R2 = (ReadReg_32(DBSC_D3_DBPDRGD0) & 0xFFFFFFF8);
+         WriteReg_32(DBSC_D3_DBPDRGA0,0x000000B2 + i*0x20);
+         WriteReg_32(DBSC_D3_DBPDRGD0,RegVal_R2 | (RegVal_R7 & 0x00000007));
+         WriteReg_32(DBSC_D3_DBPDRGA0,0x000000B0 + i*0x20);
+         RegVal_R2 = (ReadReg_32(DBSC_D3_DBPDRGD0) & 0xFFFFFF00);
+         WriteReg_32(DBSC_D3_DBPDRGA0,0x000000B0 + i*0x20);
+         WriteReg_32(DBSC_D3_DBPDRGD0,RegVal_R2 | ((RegVal_R6 + (RegVal_R5) + ((RegVal_R5) >> 1) + (RegVal_R12)) & 0x000000FF));
+      }
+   }
+   WriteReg_32(DBSC_D3_DBPDRGA0,0x000000A0);
+   WriteReg_32(DBSC_D3_DBPDRGD0,0x7C0002C5);
+   WriteReg_32(DBSC_D3_DBPDRGA0,0x000000C0);
+   WriteReg_32(DBSC_D3_DBPDRGD0,0x7C0002C5);
+   WriteReg_32(DBSC_D3_DBPDRGA0,0x00000001);
+   WriteReg_32(DBSC_D3_DBPDRGD0,0x00015001);
+   WriteReg_32(DBSC_D3_DBPDRGA0,0x00000006);
+   while ( (BIT0 & ReadReg_32(DBSC_D3_DBPDRGD0)) == 0 );
+
+   WriteReg_32(DBSC_D3_DBPDRGA0,0x00000003);
+   WriteReg_32(DBSC_D3_DBPDRGD0,0x0380C700);
+   WriteReg_32(DBSC_D3_DBPDRGA0,0x00000007);
+   while ( (BIT30 & ReadReg_32(DBSC_D3_DBPDRGD0)) != 0 );
+   WriteReg_32(DBSC_D3_DBPDRGA0,0x00000021);
+   WriteReg_32(DBSC_D3_DBPDRGD0,0x0024643E);
+
+   WriteReg_32(DBSC_D3_DBBUS0CNF1,0x00000010);
+   WriteReg_32(DBSC_D3_DBCALCNF,0x0100401B);
+   WriteReg_32(DBSC_D3_DBRFCNF1,0x00080C30);
+   WriteReg_32(DBSC_D3_DBRFCNF2,0x00010000);
+   WriteReg_32(DBSC_D3_DBDFICUPDCNF,0x40100001);
+   WriteReg_32(DBSC_D3_DBRFEN,0x00000001);
+   WriteReg_32(DBSC_D3_DBACEN,0x00000001);
+   WriteReg_32(DBSC_D3_DBPDLK0,0x00000000);
+   WriteReg_32(DBSC_D3_DBSYSCNT0,0x00000000);
+
+#ifdef ddr_qos_init_setting // only for non qos_init
+   WriteReg_32(DBSC_D3_DBSYSCNT0,0x00001234);
+   WriteReg_32(DBSC_D3_DBCAM0CNF1,0x00043218);
+   WriteReg_32(DBSC_D3_DBCAM0CNF2,0x000000F4);
+   WriteReg_32(DBSC_D3_DBSCHCNT0,0x000f0037);
+   WriteReg_32(DBSC_D3_DBSCHSZ0,0x00000001);
+   WriteReg_32(DBSC_D3_DBSCHRW0,0x22421111);
+   WriteReg_32(DBSC_D3_SCFCTST2,0x012F1123);
+   WriteReg_32(DBSC_D3_DBSCHQOS00,0x00000F00);
+   WriteReg_32(DBSC_D3_DBSCHQOS01,0x00000B00);
+   WriteReg_32(DBSC_D3_DBSCHQOS02,0x00000000);
+   WriteReg_32(DBSC_D3_DBSCHQOS03,0x00000000);
+   WriteReg_32(DBSC_D3_DBSCHQOS40,0x00000300);
+   WriteReg_32(DBSC_D3_DBSCHQOS41,0x000002F0);
+   WriteReg_32(DBSC_D3_DBSCHQOS42,0x00000200);
+   WriteReg_32(DBSC_D3_DBSCHQOS43,0x00000100);
+   WriteReg_32(DBSC_D3_DBSCHQOS90,0x00000300);
+   WriteReg_32(DBSC_D3_DBSCHQOS91,0x000002F0);
+   WriteReg_32(DBSC_D3_DBSCHQOS92,0x00000200);
+   WriteReg_32(DBSC_D3_DBSCHQOS93,0x00000100);
+   WriteReg_32(DBSC_D3_DBSCHQOS130,0x00000100);
+   WriteReg_32(DBSC_D3_DBSCHQOS131,0x000000F0);
+   WriteReg_32(DBSC_D3_DBSCHQOS132,0x000000A0);
+   WriteReg_32(DBSC_D3_DBSCHQOS133,0x00000040);
+   WriteReg_32(DBSC_D3_DBSCHQOS140,0x000000C0);
+   WriteReg_32(DBSC_D3_DBSCHQOS141,0x000000B0);
+   WriteReg_32(DBSC_D3_DBSCHQOS142,0x00000080);
+   WriteReg_32(DBSC_D3_DBSCHQOS143,0x00000040);
+   WriteReg_32(DBSC_D3_DBSCHQOS150,0x00000040);
+   WriteReg_32(DBSC_D3_DBSCHQOS151,0x00000030);
+   WriteReg_32(DBSC_D3_DBSCHQOS152,0x00000020);
+   WriteReg_32(DBSC_D3_DBSCHQOS153,0x00000010);
+   WriteReg_32(0xE67F0018,0x00000001);
+   WriteReg_32(DBSC_D3_DBSYSCNT0,0x00000000);
+#endif
+}
+
+#define PRR			(0xFFF00044U)
+#define PRR_PRODUCT_MASK	(0x00007F00U)
+#define PRR_PRODUCT_D3		(0x00005800U)
+
+#define	RST_MODEMR		(0xE6160060)
+#define	MODEMR_MD19		(0x00080000U)
+
+int32_t rcar_dram_init(void)
+{
+	uint32_t reg;
+	uint32_t ddr_mbps;
+
+	reg = mmio_read_32(PRR);
+
+	if (PRR_PRODUCT_D3 != (reg & PRR_PRODUCT_MASK)) {
+		ERROR("LSI Product ID (PRR=0x%x) DDR initialize not supported.\n",
+		      reg);
+		panic();
+	}
+
+	reg = mmio_read_32(RST_MODEMR);
+	if (MODEMR_MD19 == (reg & MODEMR_MD19)) {
+		init_ddr_d3_1866();
+		ddr_mbps = 1866;
+	} else {
+		init_ddr_d3_1600();
+		ddr_mbps = 1600;
+	}
+
+	NOTICE("BL2: DDR%d\n", ddr_mbps);
+
+	return 0;
+}
diff --git a/drivers/staging/renesas/rcar/pfc/D3/pfc_init_d3.c b/drivers/staging/renesas/rcar/pfc/D3/pfc_init_d3.c
new file mode 100644
index 000000000..639f832b5
--- /dev/null
+++ b/drivers/staging/renesas/rcar/pfc/D3/pfc_init_d3.c
@@ -0,0 +1,943 @@
+/*
+ * Copyright (c) 2015-2017, Renesas Electronics Corporation. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <stdint.h>
+#include <mmio.h>
+#include "pfc_init_d3.h"
+#include "rcar_def.h"
+
+
+/* GPIO base address */
+#define	GPIO_BASE		(0xE6050000U)
+
+/* GPIO registers */
+#define	GPIO_IOINTSEL0		(GPIO_BASE + 0x0000U)
+#define	GPIO_INOUTSEL0		(GPIO_BASE + 0x0004U)
+#define	GPIO_OUTDT0		(GPIO_BASE + 0x0008U)
+#define	GPIO_INDT0		(GPIO_BASE + 0x000CU)
+#define	GPIO_INTDT0		(GPIO_BASE + 0x0010U)
+#define	GPIO_INTCLR0		(GPIO_BASE + 0x0014U)
+#define	GPIO_INTMSK0		(GPIO_BASE + 0x0018U)
+#define	GPIO_MSKCLR0		(GPIO_BASE + 0x001CU)
+#define	GPIO_POSNEG0		(GPIO_BASE + 0x0020U)
+#define	GPIO_EDGLEVEL0		(GPIO_BASE + 0x0024U)
+#define	GPIO_FILONOFF0		(GPIO_BASE + 0x0028U)
+#define	GPIO_INTMSKS0		(GPIO_BASE + 0x0038U)
+#define	GPIO_MSKCLRS0		(GPIO_BASE + 0x003CU)
+#define	GPIO_OUTDTSEL0		(GPIO_BASE + 0x0040U)
+#define	GPIO_OUTDTH0		(GPIO_BASE + 0x0044U)
+#define	GPIO_OUTDTL0		(GPIO_BASE + 0x0048U)
+#define	GPIO_BOTHEDGE0		(GPIO_BASE + 0x004CU)
+#define	GPIO_IOINTSEL1		(GPIO_BASE + 0x1000U)
+#define	GPIO_INOUTSEL1		(GPIO_BASE + 0x1004U)
+#define	GPIO_OUTDT1		(GPIO_BASE + 0x1008U)
+#define	GPIO_INDT1		(GPIO_BASE + 0x100CU)
+#define	GPIO_INTDT1		(GPIO_BASE + 0x1010U)
+#define	GPIO_INTCLR1		(GPIO_BASE + 0x1014U)
+#define	GPIO_INTMSK1		(GPIO_BASE + 0x1018U)
+#define	GPIO_MSKCLR1		(GPIO_BASE + 0x101CU)
+#define	GPIO_POSNEG1		(GPIO_BASE + 0x1020U)
+#define	GPIO_EDGLEVEL1		(GPIO_BASE + 0x1024U)
+#define	GPIO_FILONOFF1		(GPIO_BASE + 0x1028U)
+#define	GPIO_INTMSKS1		(GPIO_BASE + 0x1038U)
+#define	GPIO_MSKCLRS1		(GPIO_BASE + 0x103CU)
+#define	GPIO_OUTDTSEL1		(GPIO_BASE + 0x1040U)
+#define	GPIO_OUTDTH1		(GPIO_BASE + 0x1044U)
+#define	GPIO_OUTDTL1		(GPIO_BASE + 0x1048U)
+#define	GPIO_BOTHEDGE1		(GPIO_BASE + 0x104CU)
+#define	GPIO_IOINTSEL2		(GPIO_BASE + 0x2000U)
+#define	GPIO_INOUTSEL2		(GPIO_BASE + 0x2004U)
+#define	GPIO_OUTDT2		(GPIO_BASE + 0x2008U)
+#define	GPIO_INDT2		(GPIO_BASE + 0x200CU)
+#define	GPIO_INTDT2		(GPIO_BASE + 0x2010U)
+#define	GPIO_INTCLR2		(GPIO_BASE + 0x2014U)
+#define	GPIO_INTMSK2		(GPIO_BASE + 0x2018U)
+#define	GPIO_MSKCLR2		(GPIO_BASE + 0x201CU)
+#define	GPIO_POSNEG2		(GPIO_BASE + 0x2020U)
+#define	GPIO_EDGLEVEL2		(GPIO_BASE + 0x2024U)
+#define	GPIO_FILONOFF2		(GPIO_BASE + 0x2028U)
+#define	GPIO_INTMSKS2		(GPIO_BASE + 0x2038U)
+#define	GPIO_MSKCLRS2		(GPIO_BASE + 0x203CU)
+#define	GPIO_OUTDTSEL2		(GPIO_BASE + 0x2040U)
+#define	GPIO_OUTDTH2		(GPIO_BASE + 0x2044U)
+#define	GPIO_OUTDTL2		(GPIO_BASE + 0x2048U)
+#define	GPIO_BOTHEDGE2		(GPIO_BASE + 0x204CU)
+#define	GPIO_IOINTSEL3		(GPIO_BASE + 0x3000U)
+#define	GPIO_INOUTSEL3		(GPIO_BASE + 0x3004U)
+#define	GPIO_OUTDT3		(GPIO_BASE + 0x3008U)
+#define	GPIO_INDT3		(GPIO_BASE + 0x300CU)
+#define	GPIO_INTDT3		(GPIO_BASE + 0x3010U)
+#define	GPIO_INTCLR3		(GPIO_BASE + 0x3014U)
+#define	GPIO_INTMSK3		(GPIO_BASE + 0x3018U)
+#define	GPIO_MSKCLR3		(GPIO_BASE + 0x301CU)
+#define	GPIO_POSNEG3		(GPIO_BASE + 0x3020U)
+#define	GPIO_EDGLEVEL3		(GPIO_BASE + 0x3024U)
+#define	GPIO_FILONOFF3		(GPIO_BASE + 0x3028U)
+#define	GPIO_INTMSKS3		(GPIO_BASE + 0x3038U)
+#define	GPIO_MSKCLRS3		(GPIO_BASE + 0x303CU)
+#define	GPIO_OUTDTSEL3		(GPIO_BASE + 0x3040U)
+#define	GPIO_OUTDTH3		(GPIO_BASE + 0x3044U)
+#define	GPIO_OUTDTL3		(GPIO_BASE + 0x3048U)
+#define	GPIO_BOTHEDGE3		(GPIO_BASE + 0x304CU)
+#define	GPIO_IOINTSEL4		(GPIO_BASE + 0x4000U)
+#define	GPIO_INOUTSEL4		(GPIO_BASE + 0x4004U)
+#define	GPIO_OUTDT4		(GPIO_BASE + 0x4008U)
+#define	GPIO_INDT4		(GPIO_BASE + 0x400CU)
+#define	GPIO_INTDT4		(GPIO_BASE + 0x4010U)
+#define	GPIO_INTCLR4		(GPIO_BASE + 0x4014U)
+#define	GPIO_INTMSK4		(GPIO_BASE + 0x4018U)
+#define	GPIO_MSKCLR4		(GPIO_BASE + 0x401CU)
+#define	GPIO_POSNEG4		(GPIO_BASE + 0x4020U)
+#define	GPIO_EDGLEVEL4		(GPIO_BASE + 0x4024U)
+#define	GPIO_FILONOFF4		(GPIO_BASE + 0x4028U)
+#define	GPIO_INTMSKS4		(GPIO_BASE + 0x4038U)
+#define	GPIO_MSKCLRS4		(GPIO_BASE + 0x403CU)
+#define	GPIO_OUTDTSEL4		(GPIO_BASE + 0x4040U)
+#define	GPIO_OUTDTH4		(GPIO_BASE + 0x4044U)
+#define	GPIO_OUTDTL4		(GPIO_BASE + 0x4048U)
+#define	GPIO_BOTHEDGE4		(GPIO_BASE + 0x404CU)
+#define	GPIO_IOINTSEL5		(GPIO_BASE + 0x5000U)
+#define	GPIO_INOUTSEL5		(GPIO_BASE + 0x5004U)
+#define	GPIO_OUTDT5		(GPIO_BASE + 0x5008U)
+#define	GPIO_INDT5		(GPIO_BASE + 0x500CU)
+#define	GPIO_INTDT5		(GPIO_BASE + 0x5010U)
+#define	GPIO_INTCLR5		(GPIO_BASE + 0x5014U)
+#define	GPIO_INTMSK5		(GPIO_BASE + 0x5018U)
+#define	GPIO_MSKCLR5		(GPIO_BASE + 0x501CU)
+#define	GPIO_POSNEG5		(GPIO_BASE + 0x5020U)
+#define	GPIO_EDGLEVEL5		(GPIO_BASE + 0x5024U)
+#define	GPIO_FILONOFF5		(GPIO_BASE + 0x5028U)
+#define	GPIO_INTMSKS5		(GPIO_BASE + 0x5038U)
+#define	GPIO_MSKCLRS5		(GPIO_BASE + 0x503CU)
+#define	GPIO_OUTDTSEL5		(GPIO_BASE + 0x5040U)
+#define	GPIO_OUTDTH5		(GPIO_BASE + 0x5044U)
+#define	GPIO_OUTDTL5		(GPIO_BASE + 0x5048U)
+#define	GPIO_BOTHEDGE5		(GPIO_BASE + 0x504CU)
+#define	GPIO_IOINTSEL6		(GPIO_BASE + 0x5400U)
+#define	GPIO_INOUTSEL6		(GPIO_BASE + 0x5404U)
+#define	GPIO_OUTDT6		(GPIO_BASE + 0x5408U)
+#define	GPIO_INDT6		(GPIO_BASE + 0x540CU)
+#define	GPIO_INTDT6		(GPIO_BASE + 0x5410U)
+#define	GPIO_INTCLR6		(GPIO_BASE + 0x5414U)
+#define	GPIO_INTMSK6		(GPIO_BASE + 0x5418U)
+#define	GPIO_MSKCLR6		(GPIO_BASE + 0x541CU)
+#define	GPIO_POSNEG6		(GPIO_BASE + 0x5420U)
+#define	GPIO_EDGLEVEL6		(GPIO_BASE + 0x5424U)
+#define	GPIO_FILONOFF6		(GPIO_BASE + 0x5428U)
+#define	GPIO_INTMSKS6		(GPIO_BASE + 0x5438U)
+#define	GPIO_MSKCLRS6		(GPIO_BASE + 0x543CU)
+#define	GPIO_OUTDTSEL6		(GPIO_BASE + 0x5440U)
+#define	GPIO_OUTDTH6		(GPIO_BASE + 0x5444U)
+#define	GPIO_OUTDTL6		(GPIO_BASE + 0x5448U)
+#define	GPIO_BOTHEDGE6		(GPIO_BASE + 0x544CU)
+#define	GPIO_IOINTSEL7		(GPIO_BASE + 0x5800U)
+#define	GPIO_INOUTSEL7		(GPIO_BASE + 0x5804U)
+#define	GPIO_OUTDT7		(GPIO_BASE + 0x5808U)
+#define	GPIO_INDT7		(GPIO_BASE + 0x580CU)
+#define	GPIO_INTDT7		(GPIO_BASE + 0x5810U)
+#define	GPIO_INTCLR7		(GPIO_BASE + 0x5814U)
+#define	GPIO_INTMSK7		(GPIO_BASE + 0x5818U)
+#define	GPIO_MSKCLR7		(GPIO_BASE + 0x581CU)
+#define	GPIO_POSNEG7		(GPIO_BASE + 0x5820U)
+#define	GPIO_EDGLEVEL7		(GPIO_BASE + 0x5824U)
+#define	GPIO_FILONOFF7		(GPIO_BASE + 0x5828U)
+#define	GPIO_INTMSKS7		(GPIO_BASE + 0x5838U)
+#define	GPIO_MSKCLRS7		(GPIO_BASE + 0x583CU)
+#define	GPIO_OUTDTSEL7		(GPIO_BASE + 0x5840U)
+#define	GPIO_OUTDTH7		(GPIO_BASE + 0x5844U)
+#define	GPIO_OUTDTL7		(GPIO_BASE + 0x5848U)
+#define	GPIO_BOTHEDGE7		(GPIO_BASE + 0x584CU)
+
+
+/* Pin functon base address */
+#define	PFC_BASE		(0xE6060000U)
+
+/* Pin functon registers */
+#define	PFC_PMMR		(PFC_BASE + 0x0000U)
+#define PFC_GPSR0		(PFC_BASE + 0x0100U)
+#define PFC_GPSR1		(PFC_BASE + 0x0104U)
+#define PFC_GPSR2		(PFC_BASE + 0x0108U)
+#define PFC_GPSR3		(PFC_BASE + 0x010CU)
+#define PFC_GPSR4		(PFC_BASE + 0x0110U)
+#define	PFC_GPSR5		(PFC_BASE + 0x0114U)
+#define	PFC_GPSR6		(PFC_BASE + 0x0118U)
+#define	PFC_GPSR7		(PFC_BASE + 0x011CU)
+#define	PFC_IPSR0		(PFC_BASE + 0x0200U)
+#define	PFC_IPSR1		(PFC_BASE + 0x0204U)
+#define	PFC_IPSR2		(PFC_BASE + 0x0208U)
+#define	PFC_IPSR3		(PFC_BASE + 0x020CU)
+#define	PFC_IPSR4		(PFC_BASE + 0x0210U)
+#define	PFC_IPSR5		(PFC_BASE + 0x0214U)
+#define	PFC_IPSR6		(PFC_BASE + 0x0218U)
+#define	PFC_IPSR7		(PFC_BASE + 0x021CU)
+#define	PFC_IPSR8		(PFC_BASE + 0x0220U)
+#define	PFC_IPSR9		(PFC_BASE + 0x0224U)
+#define	PFC_IPSR10		(PFC_BASE + 0x0228U)
+#define	PFC_IPSR11		(PFC_BASE + 0x022CU)
+#define	PFC_IPSR12		(PFC_BASE + 0x0230U)
+#define	PFC_IPSR13		(PFC_BASE + 0x0234U)
+#define	PFC_IPSR14		(PFC_BASE + 0x0238U)
+#define	PFC_IPSR15		(PFC_BASE + 0x023CU)
+#define	PFC_IPSR16		(PFC_BASE + 0x0240U)
+#define	PFC_IPSR17		(PFC_BASE + 0x0244U)
+#define	PFC_IPSR18		(PFC_BASE + 0x0248U)
+#define PFC_DRVCTRL0		(PFC_BASE + 0x0300U)
+#define PFC_DRVCTRL1		(PFC_BASE + 0x0304U)
+#define PFC_DRVCTRL2		(PFC_BASE + 0x0308U)
+#define PFC_DRVCTRL3		(PFC_BASE + 0x030CU)
+#define PFC_DRVCTRL4		(PFC_BASE + 0x0310U)
+#define PFC_DRVCTRL5		(PFC_BASE + 0x0314U)
+#define PFC_DRVCTRL6		(PFC_BASE + 0x0318U)
+#define PFC_DRVCTRL7		(PFC_BASE + 0x031CU)
+#define PFC_DRVCTRL8		(PFC_BASE + 0x0320U)
+#define PFC_DRVCTRL9		(PFC_BASE + 0x0324U)
+#define PFC_DRVCTRL10		(PFC_BASE + 0x0328U)
+#define PFC_DRVCTRL11		(PFC_BASE + 0x032CU)
+#define PFC_DRVCTRL12		(PFC_BASE + 0x0330U)
+#define PFC_DRVCTRL13		(PFC_BASE + 0x0334U)
+#define PFC_DRVCTRL14		(PFC_BASE + 0x0338U)
+#define PFC_DRVCTRL15		(PFC_BASE + 0x033CU)
+#define PFC_DRVCTRL16		(PFC_BASE + 0x0340U)
+#define PFC_DRVCTRL17		(PFC_BASE + 0x0344U)
+#define PFC_DRVCTRL18		(PFC_BASE + 0x0348U)
+#define PFC_DRVCTRL19		(PFC_BASE + 0x034CU)
+#define PFC_DRVCTRL20		(PFC_BASE + 0x0350U)
+#define PFC_DRVCTRL21		(PFC_BASE + 0x0354U)
+#define PFC_DRVCTRL22		(PFC_BASE + 0x0358U)
+#define PFC_DRVCTRL23		(PFC_BASE + 0x035CU)
+#define PFC_DRVCTRL24		(PFC_BASE + 0x0360U)
+#define PFC_POCCTRL0		(PFC_BASE + 0x0380U)
+#define PFC_POCCTRL1		(PFC_BASE + 0x0388U)
+#define	PFC_TDSELCTRL0		(PFC_BASE + 0x03C0U)
+#define	PFC_IOCTRL		(PFC_BASE + 0x03E0U)
+#define	PFC_TSREG		(PFC_BASE + 0x03E4U)
+#define	PFC_PUEN0		(PFC_BASE + 0x0400U)
+#define	PFC_PUEN1		(PFC_BASE + 0x0404U)
+#define	PFC_PUEN2		(PFC_BASE + 0x0408U)
+#define	PFC_PUEN3		(PFC_BASE + 0x040CU)
+#define	PFC_PUEN4		(PFC_BASE + 0x0410U)
+#define	PFC_PUEN5		(PFC_BASE + 0x0414U)
+#define	PFC_PUEN6		(PFC_BASE + 0x0418U)
+#define	PFC_PUD0		(PFC_BASE + 0x0440U)
+#define	PFC_PUD1		(PFC_BASE + 0x0444U)
+#define	PFC_PUD2		(PFC_BASE + 0x0448U)
+#define	PFC_PUD3		(PFC_BASE + 0x044CU)
+#define	PFC_PUD4		(PFC_BASE + 0x0450U)
+#define	PFC_PUD5		(PFC_BASE + 0x0454U)
+#define	PFC_PUD6		(PFC_BASE + 0x0458U)
+#define	PFC_MOD_SEL0		(PFC_BASE + 0x0500U)
+#define	PFC_MOD_SEL1		(PFC_BASE + 0x0504U)
+#define	PFC_MOD_SEL2		(PFC_BASE + 0x0508U)
+
+#define	GPSR0_D15		((uint32_t)1U << 15U)
+#define	GPSR0_D14		((uint32_t)1U << 14U)
+#define	GPSR0_D13		((uint32_t)1U << 13U)
+#define	GPSR0_D12		((uint32_t)1U << 12U)
+#define	GPSR0_D11		((uint32_t)1U << 11U)
+#define	GPSR0_D10		((uint32_t)1U << 10U)
+#define	GPSR0_D9		((uint32_t)1U << 9U)
+#define	GPSR0_D8		((uint32_t)1U << 8U)
+#define	GPSR0_D7		((uint32_t)1U << 7U)
+#define	GPSR0_D6		((uint32_t)1U << 6U)
+#define	GPSR0_D5		((uint32_t)1U << 5U)
+#define	GPSR0_D4		((uint32_t)1U << 4U)
+#define	GPSR0_D3		((uint32_t)1U << 3U)
+#define	GPSR0_D2		((uint32_t)1U << 2U)
+#define	GPSR0_D1		((uint32_t)1U << 1U)
+#define	GPSR0_D0		((uint32_t)1U << 0U)
+#define	GPSR1_CLKOUT		((uint32_t)1U << 28U)
+#define	GPSR1_EX_WAIT0_A	((uint32_t)1U << 27U)
+#define	GPSR1_WE1		((uint32_t)1U << 26U)
+#define	GPSR1_WE0		((uint32_t)1U << 25U)
+#define	GPSR1_RD_WR		((uint32_t)1U << 24U)
+#define	GPSR1_RD		((uint32_t)1U << 23U)
+#define	GPSR1_BS		((uint32_t)1U << 22U)
+#define	GPSR1_CS1_A26		((uint32_t)1U << 21U)
+#define	GPSR1_CS0		((uint32_t)1U << 20U)
+#define	GPSR1_A19		((uint32_t)1U << 19U)
+#define	GPSR1_A18		((uint32_t)1U << 18U)
+#define	GPSR1_A17		((uint32_t)1U << 17U)
+#define	GPSR1_A16		((uint32_t)1U << 16U)
+#define	GPSR1_A15		((uint32_t)1U << 15U)
+#define	GPSR1_A14		((uint32_t)1U << 14U)
+#define	GPSR1_A13		((uint32_t)1U << 13U)
+#define	GPSR1_A12		((uint32_t)1U << 12U)
+#define	GPSR1_A11		((uint32_t)1U << 11U)
+#define	GPSR1_A10		((uint32_t)1U << 10U)
+#define	GPSR1_A9		((uint32_t)1U << 9U)
+#define	GPSR1_A8		((uint32_t)1U << 8U)
+#define	GPSR1_A7		((uint32_t)1U << 7U)
+#define	GPSR1_A6		((uint32_t)1U << 6U)
+#define	GPSR1_A5		((uint32_t)1U << 5U)
+#define	GPSR1_A4		((uint32_t)1U << 4U)
+#define	GPSR1_A3		((uint32_t)1U << 3U)
+#define	GPSR1_A2		((uint32_t)1U << 2U)
+#define	GPSR1_A1		((uint32_t)1U << 1U)
+#define	GPSR1_A0		((uint32_t)1U << 0U)
+#define	GPSR2_AVB_AVTP_CAPTURE_A	((uint32_t)1U << 14U)
+#define	GPSR2_AVB_AVTP_MATCH_A	((uint32_t)1U << 13U)
+#define	GPSR2_AVB_LINK		((uint32_t)1U << 12U)
+#define	GPSR2_AVB_PHY_INT	((uint32_t)1U << 11U)
+#define	GPSR2_AVB_MAGIC		((uint32_t)1U << 10U)
+#define	GPSR2_AVB_MDC		((uint32_t)1U << 9U)
+#define	GPSR2_PWM2_A		((uint32_t)1U << 8U)
+#define	GPSR2_PWM1_A		((uint32_t)1U << 7U)
+#define	GPSR2_PWM0		((uint32_t)1U << 6U)
+#define	GPSR2_IRQ5		((uint32_t)1U << 5U)
+#define	GPSR2_IRQ4		((uint32_t)1U << 4U)
+#define	GPSR2_IRQ3		((uint32_t)1U << 3U)
+#define	GPSR2_IRQ2		((uint32_t)1U << 2U)
+#define	GPSR2_IRQ1		((uint32_t)1U << 1U)
+#define	GPSR2_IRQ0		((uint32_t)1U << 0U)
+#define	GPSR3_SD1_WP		((uint32_t)1U << 15U)
+#define	GPSR3_SD1_CD		((uint32_t)1U << 14U)
+#define	GPSR3_SD0_WP		((uint32_t)1U << 13U)
+#define	GPSR3_SD0_CD		((uint32_t)1U << 12U)
+#define	GPSR3_SD1_DAT3		((uint32_t)1U << 11U)
+#define	GPSR3_SD1_DAT2		((uint32_t)1U << 10U)
+#define	GPSR3_SD1_DAT1		((uint32_t)1U << 9U)
+#define	GPSR3_SD1_DAT0		((uint32_t)1U << 8U)
+#define	GPSR3_SD1_CMD		((uint32_t)1U << 7U)
+#define	GPSR3_SD1_CLK		((uint32_t)1U << 6U)
+#define	GPSR3_SD0_DAT3		((uint32_t)1U << 5U)
+#define	GPSR3_SD0_DAT2		((uint32_t)1U << 4U)
+#define	GPSR3_SD0_DAT1		((uint32_t)1U << 3U)
+#define	GPSR3_SD0_DAT0		((uint32_t)1U << 2U)
+#define	GPSR3_SD0_CMD		((uint32_t)1U << 1U)
+#define	GPSR3_SD0_CLK		((uint32_t)1U << 0U)
+#define	GPSR4_SD3_DS		((uint32_t)1U << 17U)
+#define	GPSR4_SD3_DAT7		((uint32_t)1U << 16U)
+#define	GPSR4_SD3_DAT6		((uint32_t)1U << 15U)
+#define	GPSR4_SD3_DAT5		((uint32_t)1U << 14U)
+#define	GPSR4_SD3_DAT4		((uint32_t)1U << 13U)
+#define	GPSR4_SD3_DAT3		((uint32_t)1U << 12U)
+#define	GPSR4_SD3_DAT2		((uint32_t)1U << 11U)
+#define	GPSR4_SD3_DAT1		((uint32_t)1U << 10U)
+#define	GPSR4_SD3_DAT0		((uint32_t)1U << 9U)
+#define	GPSR4_SD3_CMD		((uint32_t)1U << 8U)
+#define	GPSR4_SD3_CLK		((uint32_t)1U << 7U)
+#define	GPSR4_SD2_DS		((uint32_t)1U << 6U)
+#define	GPSR4_SD2_DAT3		((uint32_t)1U << 5U)
+#define	GPSR4_SD2_DAT2		((uint32_t)1U << 4U)
+#define	GPSR4_SD2_DAT1		((uint32_t)1U << 3U)
+#define	GPSR4_SD2_DAT0		((uint32_t)1U << 2U)
+#define	GPSR4_SD2_CMD		((uint32_t)1U << 1U)
+#define	GPSR4_SD2_CLK		((uint32_t)1U << 0U)
+#define	GPSR5_MLB_DAT		((uint32_t)1U << 25U)
+#define	GPSR5_MLB_SIG		((uint32_t)1U << 24U)
+#define	GPSR5_MLB_CLK		((uint32_t)1U << 23U)
+#define	GPSR5_MSIOF0_RXD	((uint32_t)1U << 22U)
+#define	GPSR5_MSIOF0_SS2	((uint32_t)1U << 21U)
+#define	GPSR5_MSIOF0_TXD	((uint32_t)1U << 20U)
+#define	GPSR5_MSIOF0_SS1	((uint32_t)1U << 19U)
+#define	GPSR5_MSIOF0_SYNC	((uint32_t)1U << 18U)
+#define	GPSR5_MSIOF0_SCK	((uint32_t)1U << 17U)
+#define	GPSR5_HRTS0		((uint32_t)1U << 16U)
+#define	GPSR5_HCTS0		((uint32_t)1U << 15U)
+#define	GPSR5_HTX0		((uint32_t)1U << 14U)
+#define	GPSR5_HRX0		((uint32_t)1U << 13U)
+#define	GPSR5_HSCK0		((uint32_t)1U << 12U)
+#define	GPSR5_RX2_A		((uint32_t)1U << 11U)
+#define	GPSR5_TX2_A		((uint32_t)1U << 10U)
+#define	GPSR5_SCK2		((uint32_t)1U << 9U)
+#define	GPSR5_RTS1_TANS		((uint32_t)1U << 8U)
+#define	GPSR5_CTS1		((uint32_t)1U << 7U)
+#define	GPSR5_TX1_A		((uint32_t)1U << 6U)
+#define	GPSR5_RX1_A		((uint32_t)1U << 5U)
+#define	GPSR5_RTS0_TANS		((uint32_t)1U << 4U)
+#define	GPSR5_CTS0		((uint32_t)1U << 3U)
+#define	GPSR5_TX0		((uint32_t)1U << 2U)
+#define	GPSR5_RX0		((uint32_t)1U << 1U)
+#define	GPSR5_SCK0		((uint32_t)1U << 0U)
+#define	GPSR6_USB31_OVC		((uint32_t)1U << 31U)
+#define	GPSR6_USB31_PWEN	((uint32_t)1U << 30U)
+#define	GPSR6_USB30_OVC		((uint32_t)1U << 29U)
+#define	GPSR6_USB30_PWEN	((uint32_t)1U << 28U)
+#define	GPSR6_USB1_OVC		((uint32_t)1U << 27U)
+#define	GPSR6_USB1_PWEN		((uint32_t)1U << 26U)
+#define	GPSR6_USB0_OVC		((uint32_t)1U << 25U)
+#define	GPSR6_USB0_PWEN		((uint32_t)1U << 24U)
+#define	GPSR6_AUDIO_CLKB_B	((uint32_t)1U << 23U)
+#define	GPSR6_AUDIO_CLKA_A	((uint32_t)1U << 22U)
+#define	GPSR6_SSI_SDATA9_A	((uint32_t)1U << 21U)
+#define	GPSR6_SSI_SDATA8	((uint32_t)1U << 20U)
+#define	GPSR6_SSI_SDATA7	((uint32_t)1U << 19U)
+#define	GPSR6_SSI_WS78		((uint32_t)1U << 18U)
+#define	GPSR6_SSI_SCK78		((uint32_t)1U << 17U)
+#define	GPSR6_SSI_SDATA6	((uint32_t)1U << 16U)
+#define	GPSR6_SSI_WS6		((uint32_t)1U << 15U)
+#define	GPSR6_SSI_SCK6		((uint32_t)1U << 14U)
+#define	GPSR6_SSI_SDATA5	((uint32_t)1U << 13U)
+#define	GPSR6_SSI_WS5		((uint32_t)1U << 12U)
+#define	GPSR6_SSI_SCK5		((uint32_t)1U << 11U)
+#define	GPSR6_SSI_SDATA4	((uint32_t)1U << 10U)
+#define	GPSR6_SSI_WS4		((uint32_t)1U << 9U)
+#define	GPSR6_SSI_SCK4		((uint32_t)1U << 8U)
+#define	GPSR6_SSI_SDATA3	((uint32_t)1U << 7U)
+#define	GPSR6_SSI_WS34		((uint32_t)1U << 6U)
+#define	GPSR6_SSI_SCK34		((uint32_t)1U << 5U)
+#define	GPSR6_SSI_SDATA2_A	((uint32_t)1U << 4U)
+#define	GPSR6_SSI_SDATA1_A	((uint32_t)1U << 3U)
+#define	GPSR6_SSI_SDATA0	((uint32_t)1U << 2U)
+#define	GPSR6_SSI_WS0129	((uint32_t)1U << 1U)
+#define	GPSR6_SSI_SCK0129	((uint32_t)1U << 0U)
+#define	GPSR7_HDMI1_CEC		((uint32_t)1U << 3U)
+#define	GPSR7_HDMI0_CEC		((uint32_t)1U << 2U)
+#define	GPSR7_AVS2		((uint32_t)1U << 1U)
+#define	GPSR7_AVS1		((uint32_t)1U << 0U)
+
+#define	IPSR_28_FUNC(x)		((uint32_t)(x) << 28U)
+#define	IPSR_24_FUNC(x)		((uint32_t)(x) << 24U)
+#define	IPSR_20_FUNC(x)		((uint32_t)(x) << 20U)
+#define	IPSR_16_FUNC(x)		((uint32_t)(x) << 16U)
+#define	IPSR_12_FUNC(x)		((uint32_t)(x) << 12U)
+#define	IPSR_8_FUNC(x)		((uint32_t)(x) << 8U)
+#define	IPSR_4_FUNC(x)		((uint32_t)(x) << 4U)
+#define	IPSR_0_FUNC(x)		((uint32_t)(x) << 0U)
+
+#define	POC_SD3_DS_33V		((uint32_t)1U << 29U)
+#define	POC_SD3_DAT7_33V	((uint32_t)1U << 28U)
+#define	POC_SD3_DAT6_33V	((uint32_t)1U << 27U)
+#define	POC_SD3_DAT5_33V	((uint32_t)1U << 26U)
+#define	POC_SD3_DAT4_33V	((uint32_t)1U << 25U)
+#define	POC_SD3_DAT3_33V	((uint32_t)1U << 24U)
+#define	POC_SD3_DAT2_33V	((uint32_t)1U << 23U)
+#define	POC_SD3_DAT1_33V	((uint32_t)1U << 22U)
+#define	POC_SD3_DAT0_33V	((uint32_t)1U << 21U)
+#define	POC_SD3_CMD_33V		((uint32_t)1U << 20U)
+#define	POC_SD3_CLK_33V		((uint32_t)1U << 19U)
+#define	POC_SD2_DS_33V		((uint32_t)1U << 18U)
+#define	POC_SD2_DAT3_33V	((uint32_t)1U << 17U)
+#define	POC_SD2_DAT2_33V	((uint32_t)1U << 16U)
+#define	POC_SD2_DAT1_33V	((uint32_t)1U << 15U)
+#define	POC_SD2_DAT0_33V	((uint32_t)1U << 14U)
+#define	POC_SD2_CMD_33V		((uint32_t)1U << 13U)
+#define	POC_SD2_CLK_33V		((uint32_t)1U << 12U)
+#define	POC_SD1_DAT3_33V	((uint32_t)1U << 11U)
+#define	POC_SD1_DAT2_33V	((uint32_t)1U << 10U)
+#define	POC_SD1_DAT1_33V	((uint32_t)1U << 9U)
+#define	POC_SD1_DAT0_33V	((uint32_t)1U << 8U)
+#define	POC_SD1_CMD_33V		((uint32_t)1U << 7U)
+#define	POC_SD1_CLK_33V		((uint32_t)1U << 6U)
+#define	POC_SD0_DAT3_33V	((uint32_t)1U << 5U)
+#define	POC_SD0_DAT2_33V	((uint32_t)1U << 4U)
+#define	POC_SD0_DAT1_33V	((uint32_t)1U << 3U)
+#define	POC_SD0_DAT0_33V	((uint32_t)1U << 2U)
+#define	POC_SD0_CMD_33V		((uint32_t)1U << 1U)
+#define	POC_SD0_CLK_33V		((uint32_t)1U << 0U)
+
+#define	DRVCTRL0_MASK		(0xCCCCCCCCU)
+#define	DRVCTRL1_MASK		(0xCCCCCCC8U)
+#define	DRVCTRL2_MASK		(0x88888888U)
+#define	DRVCTRL3_MASK		(0x88888888U)
+#define	DRVCTRL4_MASK		(0x88888888U)
+#define	DRVCTRL5_MASK		(0x88888888U)
+#define	DRVCTRL6_MASK		(0x88888888U)
+#define	DRVCTRL7_MASK		(0x88888888U)
+#define	DRVCTRL8_MASK		(0x88888888U)
+#define	DRVCTRL9_MASK		(0x88888888U)
+#define	DRVCTRL10_MASK		(0x88888888U)
+#define	DRVCTRL11_MASK		(0x888888CCU)
+#define	DRVCTRL12_MASK		(0xCCCFFFCFU)
+#define	DRVCTRL13_MASK		(0xCC888888U)
+#define	DRVCTRL14_MASK		(0x88888888U)
+#define	DRVCTRL15_MASK		(0x88888888U)
+#define	DRVCTRL16_MASK		(0x88888888U)
+#define	DRVCTRL17_MASK		(0x88888888U)
+#define	DRVCTRL18_MASK		(0x88888888U)
+#define	DRVCTRL19_MASK		(0x88888888U)
+#define	DRVCTRL20_MASK		(0x88888888U)
+#define	DRVCTRL21_MASK		(0x88888888U)
+#define	DRVCTRL22_MASK		(0x88888888U)
+#define	DRVCTRL23_MASK		(0x88888888U)
+#define	DRVCTRL24_MASK		(0x8888888FU)
+
+#define	DRVCTRL0_QSPI0_SPCLK(x)	((uint32_t)(x) << 28U)
+#define	DRVCTRL0_QSPI0_MOSI_IO0(x)	((uint32_t)(x) << 24U)
+#define	DRVCTRL0_QSPI0_MISO_IO1(x)	((uint32_t)(x) << 20U)
+#define	DRVCTRL0_QSPI0_IO2(x)	((uint32_t)(x) << 16U)
+#define	DRVCTRL0_QSPI0_IO3(x)	((uint32_t)(x) << 12U)
+#define	DRVCTRL0_QSPI0_SSL(x)	((uint32_t)(x) << 8U)
+#define	DRVCTRL0_QSPI1_SPCLK(x)	((uint32_t)(x) << 4U)
+#define	DRVCTRL0_QSPI1_MOSI_IO0(x)	((uint32_t)(x) << 0U)
+#define	DRVCTRL1_QSPI1_MISO_IO1(x)	((uint32_t)(x) << 28U)
+#define	DRVCTRL1_QSPI1_IO2(x)	((uint32_t)(x) << 24U)
+#define	DRVCTRL1_QSPI1_IO3(x)	((uint32_t)(x) << 20U)
+#define	DRVCTRL1_QSPI1_SS(x)	((uint32_t)(x) << 16U)
+#define	DRVCTRL1_RPC_INT(x)	((uint32_t)(x) << 12U)
+#define	DRVCTRL1_RPC_WP(x)	((uint32_t)(x) << 8U)
+#define	DRVCTRL1_RPC_RESET(x)	((uint32_t)(x) << 4U)
+#define	DRVCTRL1_AVB_RX_CTL(x)	((uint32_t)(x) << 0U)
+#define	DRVCTRL2_AVB_RXC(x)	((uint32_t)(x) << 28U)
+#define	DRVCTRL2_AVB_RD0(x)	((uint32_t)(x) << 24U)
+#define	DRVCTRL2_AVB_RD1(x)	((uint32_t)(x) << 20U)
+#define	DRVCTRL2_AVB_RD2(x)	((uint32_t)(x) << 16U)
+#define	DRVCTRL2_AVB_RD3(x)	((uint32_t)(x) << 12U)
+#define	DRVCTRL2_AVB_TX_CTL(x)	((uint32_t)(x) << 8U)
+#define	DRVCTRL2_AVB_TXC(x)	((uint32_t)(x) << 4U)
+#define	DRVCTRL2_AVB_TD0(x)	((uint32_t)(x) << 0U)
+#define	DRVCTRL3_AVB_TD1(x)	((uint32_t)(x) << 28U)
+#define	DRVCTRL3_AVB_TD2(x)	((uint32_t)(x) << 24U)
+#define	DRVCTRL3_AVB_TD3(x)	((uint32_t)(x) << 20U)
+#define	DRVCTRL3_AVB_TXCREFCLK(x)	((uint32_t)(x) << 16U)
+#define	DRVCTRL3_AVB_MDIO(x)	((uint32_t)(x) << 12U)
+#define	DRVCTRL3_AVB_MDC(x)	((uint32_t)(x) << 8U)
+#define	DRVCTRL3_AVB_MAGIC(x)	((uint32_t)(x) << 4U)
+#define	DRVCTRL3_AVB_PHY_INT(x)	((uint32_t)(x) << 0U)
+#define	DRVCTRL4_AVB_LINK(x)	((uint32_t)(x) << 28U)
+#define	DRVCTRL4_AVB_AVTP_MATCH(x)	((uint32_t)(x) << 24U)
+#define	DRVCTRL4_AVB_AVTP_CAPTURE(x)	((uint32_t)(x) << 20U)
+#define	DRVCTRL4_IRQ0(x)	((uint32_t)(x) << 16U)
+#define	DRVCTRL4_IRQ1(x)	((uint32_t)(x) << 12U)
+#define	DRVCTRL4_IRQ2(x)	((uint32_t)(x) << 8U)
+#define	DRVCTRL4_IRQ3(x)	((uint32_t)(x) << 4U)
+#define	DRVCTRL4_IRQ4(x)	((uint32_t)(x) << 0U)
+#define	DRVCTRL5_IRQ5(x)	((uint32_t)(x) << 28U)
+#define	DRVCTRL5_PWM0(x)	((uint32_t)(x) << 24U)
+#define	DRVCTRL5_PWM1(x)	((uint32_t)(x) << 20U)
+#define	DRVCTRL5_PWM2(x)	((uint32_t)(x) << 16U)
+#define	DRVCTRL5_A0(x)		((uint32_t)(x) << 12U)
+#define	DRVCTRL5_A1(x)		((uint32_t)(x) << 8U)
+#define	DRVCTRL5_A2(x)		((uint32_t)(x) << 4U)
+#define	DRVCTRL5_A3(x)		((uint32_t)(x) << 0U)
+#define	DRVCTRL6_A4(x)		((uint32_t)(x) << 28U)
+#define	DRVCTRL6_A5(x)		((uint32_t)(x) << 24U)
+#define	DRVCTRL6_A6(x)		((uint32_t)(x) << 20U)
+#define	DRVCTRL6_A7(x)		((uint32_t)(x) << 16U)
+#define	DRVCTRL6_A8(x)		((uint32_t)(x) << 12U)
+#define	DRVCTRL6_A9(x)		((uint32_t)(x) << 8U)
+#define	DRVCTRL6_A10(x)		((uint32_t)(x) << 4U)
+#define	DRVCTRL6_A11(x)		((uint32_t)(x) << 0U)
+#define	DRVCTRL7_A12(x)		((uint32_t)(x) << 28U)
+#define	DRVCTRL7_A13(x)		((uint32_t)(x) << 24U)
+#define	DRVCTRL7_A14(x)		((uint32_t)(x) << 20U)
+#define	DRVCTRL7_A15(x)		((uint32_t)(x) << 16U)
+#define	DRVCTRL7_A16(x)		((uint32_t)(x) << 12U)
+#define	DRVCTRL7_A17(x)		((uint32_t)(x) << 8U)
+#define	DRVCTRL7_A18(x)		((uint32_t)(x) << 4U)
+#define	DRVCTRL7_A19(x)		((uint32_t)(x) << 0U)
+#define	DRVCTRL8_CLKOUT(x)	((uint32_t)(x) << 28U)
+#define	DRVCTRL8_CS0(x)		((uint32_t)(x) << 24U)
+#define	DRVCTRL8_CS1_A2(x)	((uint32_t)(x) << 20U)
+#define	DRVCTRL8_BS(x)		((uint32_t)(x) << 16U)
+#define	DRVCTRL8_RD(x)		((uint32_t)(x) << 12U)
+#define	DRVCTRL8_RD_W(x)	((uint32_t)(x) << 8U)
+#define	DRVCTRL8_WE0(x)		((uint32_t)(x) << 4U)
+#define	DRVCTRL8_WE1(x)		((uint32_t)(x) << 0U)
+#define	DRVCTRL9_EX_WAIT0(x)	((uint32_t)(x) << 28U)
+#define	DRVCTRL9_PRESETOU(x)	((uint32_t)(x) << 24U)
+#define	DRVCTRL9_D0(x)		((uint32_t)(x) << 20U)
+#define	DRVCTRL9_D1(x)		((uint32_t)(x) << 16U)
+#define	DRVCTRL9_D2(x)		((uint32_t)(x) << 12U)
+#define	DRVCTRL9_D3(x)		((uint32_t)(x) << 8U)
+#define	DRVCTRL9_D4(x)		((uint32_t)(x) << 4U)
+#define	DRVCTRL9_D5(x)		((uint32_t)(x) << 0U)
+#define	DRVCTRL10_D6(x)		((uint32_t)(x) << 28U)
+#define	DRVCTRL10_D7(x)		((uint32_t)(x) << 24U)
+#define	DRVCTRL10_D8(x)		((uint32_t)(x) << 20U)
+#define	DRVCTRL10_D9(x)		((uint32_t)(x) << 16U)
+#define	DRVCTRL10_D10(x)	((uint32_t)(x) << 12U)
+#define	DRVCTRL10_D11(x)	((uint32_t)(x) << 8U)
+#define	DRVCTRL10_D12(x)	((uint32_t)(x) << 4U)
+#define	DRVCTRL10_D13(x)	((uint32_t)(x) << 0U)
+#define	DRVCTRL11_D14(x)	((uint32_t)(x) << 28U)
+#define	DRVCTRL11_D15(x)	((uint32_t)(x) << 24U)
+#define	DRVCTRL11_AVS1(x)	((uint32_t)(x) << 20U)
+#define	DRVCTRL11_AVS2(x)	((uint32_t)(x) << 16U)
+#define	DRVCTRL11_HDMI0_CEC(x)	((uint32_t)(x) << 12U)
+#define	DRVCTRL11_HDMI1_CEC(x)	((uint32_t)(x) << 8U)
+#define	DRVCTRL11_DU_DOTCLKIN0(x)	((uint32_t)(x) << 4U)
+#define	DRVCTRL11_DU_DOTCLKIN1(x)	((uint32_t)(x) << 0U)
+#define	DRVCTRL12_DU_DOTCLKIN2(x)	((uint32_t)(x) << 28U)
+#define	DRVCTRL12_DU_DOTCLKIN3(x)	((uint32_t)(x) << 24U)
+#define	DRVCTRL12_DU_FSCLKST(x)	((uint32_t)(x) << 20U)
+#define	DRVCTRL12_DU_TMS(x)	((uint32_t)(x) << 4U)
+#define	DRVCTRL13_TDO(x)	((uint32_t)(x) << 28U)
+#define	DRVCTRL13_ASEBRK(x)	((uint32_t)(x) << 24U)
+#define	DRVCTRL13_SD0_CLK(x)	((uint32_t)(x) << 20U)
+#define	DRVCTRL13_SD0_CMD(x)	((uint32_t)(x) << 16U)
+#define	DRVCTRL13_SD0_DAT0(x)	((uint32_t)(x) << 12U)
+#define	DRVCTRL13_SD0_DAT1(x)	((uint32_t)(x) << 8U)
+#define	DRVCTRL13_SD0_DAT2(x)	((uint32_t)(x) << 4U)
+#define	DRVCTRL13_SD0_DAT3(x)	((uint32_t)(x) << 0U)
+#define	DRVCTRL14_SD1_CLK(x)	((uint32_t)(x) << 28U)
+#define	DRVCTRL14_SD1_CMD(x)	((uint32_t)(x) << 24U)
+#define	DRVCTRL14_SD1_DAT0(x)	((uint32_t)(x) << 20U)
+#define	DRVCTRL14_SD1_DAT1(x)	((uint32_t)(x) << 16U)
+#define	DRVCTRL14_SD1_DAT2(x)	((uint32_t)(x) << 12U)
+#define	DRVCTRL14_SD1_DAT3(x)	((uint32_t)(x) << 8U)
+#define	DRVCTRL14_SD2_CLK(x)	((uint32_t)(x) << 4U)
+#define	DRVCTRL14_SD2_CMD(x)	((uint32_t)(x) << 0U)
+#define	DRVCTRL15_SD2_DAT0(x)	((uint32_t)(x) << 28U)
+#define	DRVCTRL15_SD2_DAT1(x)	((uint32_t)(x) << 24U)
+#define	DRVCTRL15_SD2_DAT2(x)	((uint32_t)(x) << 20U)
+#define	DRVCTRL15_SD2_DAT3(x)	((uint32_t)(x) << 16U)
+#define	DRVCTRL15_SD2_DS(x)	((uint32_t)(x) << 12U)
+#define	DRVCTRL15_SD3_CLK(x)	((uint32_t)(x) << 8U)
+#define	DRVCTRL15_SD3_CMD(x)	((uint32_t)(x) << 4U)
+#define	DRVCTRL15_SD3_DAT0(x)	((uint32_t)(x) << 0U)
+#define	DRVCTRL16_SD3_DAT1(x)	((uint32_t)(x) << 28U)
+#define	DRVCTRL16_SD3_DAT2(x)	((uint32_t)(x) << 24U)
+#define	DRVCTRL16_SD3_DAT3(x)	((uint32_t)(x) << 20U)
+#define	DRVCTRL16_SD3_DAT4(x)	((uint32_t)(x) << 16U)
+#define	DRVCTRL16_SD3_DAT5(x)	((uint32_t)(x) << 12U)
+#define	DRVCTRL16_SD3_DAT6(x)	((uint32_t)(x) << 8U)
+#define	DRVCTRL16_SD3_DAT7(x)	((uint32_t)(x) << 4U)
+#define	DRVCTRL16_SD3_DS(x)	((uint32_t)(x) << 0U)
+#define	DRVCTRL17_SD0_CD(x)	((uint32_t)(x) << 28U)
+#define	DRVCTRL17_SD0_WP(x)	((uint32_t)(x) << 24U)
+#define	DRVCTRL17_SD1_CD(x)	((uint32_t)(x) << 20U)
+#define	DRVCTRL17_SD1_WP(x)	((uint32_t)(x) << 16U)
+#define	DRVCTRL17_SCK0(x)	((uint32_t)(x) << 12U)
+#define	DRVCTRL17_RX0(x)	((uint32_t)(x) << 8U)
+#define	DRVCTRL17_TX0(x)	((uint32_t)(x) << 4U)
+#define	DRVCTRL17_CTS0(x)	((uint32_t)(x) << 0U)
+#define	DRVCTRL18_RTS0_TANS(x)	((uint32_t)(x) << 28U)
+#define	DRVCTRL18_RX1(x)	((uint32_t)(x) << 24U)
+#define	DRVCTRL18_TX1(x)	((uint32_t)(x) << 20U)
+#define	DRVCTRL18_CTS1(x)	((uint32_t)(x) << 16U)
+#define	DRVCTRL18_RTS1_TANS(x)	((uint32_t)(x) << 12U)
+#define	DRVCTRL18_SCK2(x)	((uint32_t)(x) << 8U)
+#define	DRVCTRL18_TX2(x)	((uint32_t)(x) << 4U)
+#define	DRVCTRL18_RX2(x)	((uint32_t)(x) << 0U)
+#define	DRVCTRL19_HSCK0(x)	((uint32_t)(x) << 28U)
+#define	DRVCTRL19_HRX0(x)	((uint32_t)(x) << 24U)
+#define	DRVCTRL19_HTX0(x)	((uint32_t)(x) << 20U)
+#define	DRVCTRL19_HCTS0(x)	((uint32_t)(x) << 16U)
+#define	DRVCTRL19_HRTS0(x)	((uint32_t)(x) << 12U)
+#define	DRVCTRL19_MSIOF0_SCK(x)	((uint32_t)(x) << 8U)
+#define	DRVCTRL19_MSIOF0_SYNC(x)	((uint32_t)(x) << 4U)
+#define	DRVCTRL19_MSIOF0_SS1(x)	((uint32_t)(x) << 0U)
+#define	DRVCTRL20_MSIOF0_TXD(x)	((uint32_t)(x) << 28U)
+#define	DRVCTRL20_MSIOF0_SS2(x)	((uint32_t)(x) << 24U)
+#define	DRVCTRL20_MSIOF0_RXD(x)	((uint32_t)(x) << 20U)
+#define	DRVCTRL20_MLB_CLK(x)	((uint32_t)(x) << 16U)
+#define	DRVCTRL20_MLB_SIG(x)	((uint32_t)(x) << 12U)
+#define	DRVCTRL20_MLB_DAT(x)	((uint32_t)(x) << 8U)
+#define	DRVCTRL20_MLB_REF(x)	((uint32_t)(x) << 4U)
+#define	DRVCTRL20_SSI_SCK0129(x)	((uint32_t)(x) << 0U)
+#define	DRVCTRL21_SSI_WS0129(x)	((uint32_t)(x) << 28U)
+#define	DRVCTRL21_SSI_SDATA0(x)	((uint32_t)(x) << 24U)
+#define	DRVCTRL21_SSI_SDATA1(x)	((uint32_t)(x) << 20U)
+#define	DRVCTRL21_SSI_SDATA2(x)	((uint32_t)(x) << 16U)
+#define	DRVCTRL21_SSI_SCK34(x)	((uint32_t)(x) << 12U)
+#define	DRVCTRL21_SSI_WS34(x)	((uint32_t)(x) << 8U)
+#define	DRVCTRL21_SSI_SDATA3(x)	((uint32_t)(x) << 4U)
+#define	DRVCTRL21_SSI_SCK4(x)	((uint32_t)(x) << 0U)
+#define	DRVCTRL22_SSI_WS4(x)	((uint32_t)(x) << 28U)
+#define	DRVCTRL22_SSI_SDATA4(x)	((uint32_t)(x) << 24U)
+#define	DRVCTRL22_SSI_SCK5(x)	((uint32_t)(x) << 20U)
+#define	DRVCTRL22_SSI_WS5(x)	((uint32_t)(x) << 16U)
+#define	DRVCTRL22_SSI_SDATA5(x)	((uint32_t)(x) << 12U)
+#define	DRVCTRL22_SSI_SCK6(x)	((uint32_t)(x) << 8U)
+#define	DRVCTRL22_SSI_WS6(x)	((uint32_t)(x) << 4U)
+#define	DRVCTRL22_SSI_SDATA6(x)	((uint32_t)(x) << 0U)
+#define	DRVCTRL23_SSI_SCK78(x)	((uint32_t)(x) << 28U)
+#define	DRVCTRL23_SSI_WS78(x)	((uint32_t)(x) << 24U)
+#define	DRVCTRL23_SSI_SDATA7(x)	((uint32_t)(x) << 20U)
+#define	DRVCTRL23_SSI_SDATA8(x)	((uint32_t)(x) << 16U)
+#define	DRVCTRL23_SSI_SDATA9(x)	((uint32_t)(x) << 12U)
+#define	DRVCTRL23_AUDIO_CLKA(x)	((uint32_t)(x) << 8U)
+#define	DRVCTRL23_AUDIO_CLKB(x)	((uint32_t)(x) << 4U)
+#define	DRVCTRL23_USB0_PWEN(x)	((uint32_t)(x) << 0U)
+#define	DRVCTRL24_USB0_OVC(x)	((uint32_t)(x) << 28U)
+#define	DRVCTRL24_USB1_PWEN(x)	((uint32_t)(x) << 24U)
+#define	DRVCTRL24_USB1_OVC(x)	((uint32_t)(x) << 20U)
+#define	DRVCTRL24_USB30_PWEN(x)	((uint32_t)(x) << 16U)
+#define	DRVCTRL24_USB30_OVC(x)	((uint32_t)(x) << 12U)
+#define	DRVCTRL24_USB31_PWEN(x)	((uint32_t)(x) << 8U)
+#define	DRVCTRL24_USB31_OVC(x)	((uint32_t)(x) << 4U)
+
+#define	MOD_SEL0_MSIOF3_A	((uint32_t)0U << 29U)
+#define	MOD_SEL0_MSIOF3_B	((uint32_t)1U << 29U)
+#define	MOD_SEL0_MSIOF3_C	((uint32_t)2U << 29U)
+#define	MOD_SEL0_MSIOF3_D	((uint32_t)3U << 29U)
+#define	MOD_SEL0_MSIOF3_E	((uint32_t)4U << 29U)
+#define	MOD_SEL0_MSIOF2_A	((uint32_t)0U << 27U)
+#define	MOD_SEL0_MSIOF2_B	((uint32_t)1U << 27U)
+#define	MOD_SEL0_MSIOF2_C	((uint32_t)2U << 27U)
+#define	MOD_SEL0_MSIOF2_D	((uint32_t)3U << 27U)
+#define	MOD_SEL0_MSIOF1_A	((uint32_t)0U << 24U)
+#define	MOD_SEL0_MSIOF1_B	((uint32_t)1U << 24U)
+#define	MOD_SEL0_MSIOF1_C	((uint32_t)2U << 24U)
+#define	MOD_SEL0_MSIOF1_D	((uint32_t)3U << 24U)
+#define	MOD_SEL0_MSIOF1_E	((uint32_t)4U << 24U)
+#define	MOD_SEL0_MSIOF1_F	((uint32_t)5U << 24U)
+#define	MOD_SEL0_MSIOF1_G	((uint32_t)6U << 24U)
+#define	MOD_SEL0_LBSC_A		((uint32_t)0U << 23U)
+#define	MOD_SEL0_LBSC_B		((uint32_t)1U << 23U)
+#define	MOD_SEL0_IEBUS_A	((uint32_t)0U << 22U)
+#define	MOD_SEL0_IEBUS_B	((uint32_t)1U << 22U)
+#define	MOD_SEL0_I2C2_A		((uint32_t)0U << 21U)
+#define	MOD_SEL0_I2C2_B		((uint32_t)1U << 21U)
+#define	MOD_SEL0_I2C1_A		((uint32_t)0U << 20U)
+#define	MOD_SEL0_I2C1_B		((uint32_t)1U << 20U)
+#define	MOD_SEL0_HSCIF4_A	((uint32_t)0U << 19U)
+#define	MOD_SEL0_HSCIF4_B	((uint32_t)1U << 19U)
+#define	MOD_SEL0_HSCIF3_A	((uint32_t)0U << 17U)
+#define	MOD_SEL0_HSCIF3_B	((uint32_t)1U << 17U)
+#define	MOD_SEL0_HSCIF3_C	((uint32_t)2U << 17U)
+#define	MOD_SEL0_HSCIF3_D	((uint32_t)3U << 17U)
+#define	MOD_SEL0_HSCIF1_A	((uint32_t)0U << 16U)
+#define	MOD_SEL0_HSCIF1_B	((uint32_t)1U << 16U)
+#define	MOD_SEL0_FSO_A		((uint32_t)0U << 15U)
+#define	MOD_SEL0_FSO_B		((uint32_t)1U << 15U)
+#define	MOD_SEL0_HSCIF2_A	((uint32_t)0U << 13U)
+#define	MOD_SEL0_HSCIF2_B	((uint32_t)1U << 13U)
+#define	MOD_SEL0_HSCIF2_C	((uint32_t)2U << 13U)
+#define	MOD_SEL0_ETHERAVB_A	((uint32_t)0U << 12U)
+#define	MOD_SEL0_ETHERAVB_B	((uint32_t)1U << 12U)
+#define	MOD_SEL0_DRIF3_A	((uint32_t)0U << 11U)
+#define	MOD_SEL0_DRIF3_B	((uint32_t)1U << 11U)
+#define	MOD_SEL0_DRIF2_A	((uint32_t)0U << 10U)
+#define	MOD_SEL0_DRIF2_B	((uint32_t)1U << 10U)
+#define	MOD_SEL0_DRIF1_A	((uint32_t)0U << 8U)
+#define	MOD_SEL0_DRIF1_B	((uint32_t)1U << 8U)
+#define	MOD_SEL0_DRIF1_C	((uint32_t)2U << 8U)
+#define	MOD_SEL0_DRIF0_A	((uint32_t)0U << 6U)
+#define	MOD_SEL0_DRIF0_B	((uint32_t)1U << 6U)
+#define	MOD_SEL0_DRIF0_C	((uint32_t)2U << 6U)
+#define	MOD_SEL0_CANFD0_A	((uint32_t)0U << 5U)
+#define	MOD_SEL0_CANFD0_B	((uint32_t)1U << 5U)
+#define	MOD_SEL0_ADG_A_A	((uint32_t)0U << 3U)
+#define	MOD_SEL0_ADG_A_B	((uint32_t)1U << 3U)
+#define	MOD_SEL0_ADG_A_C	((uint32_t)2U << 3U)
+#define	MOD_SEL1_TSIF1_A	((uint32_t)0U << 30U)
+#define	MOD_SEL1_TSIF1_B	((uint32_t)1U << 30U)
+#define	MOD_SEL1_TSIF1_C	((uint32_t)2U << 30U)
+#define	MOD_SEL1_TSIF1_D	((uint32_t)3U << 30U)
+#define	MOD_SEL1_TSIF0_A	((uint32_t)0U << 27U)
+#define	MOD_SEL1_TSIF0_B	((uint32_t)1U << 27U)
+#define	MOD_SEL1_TSIF0_C	((uint32_t)2U << 27U)
+#define	MOD_SEL1_TSIF0_D	((uint32_t)3U << 27U)
+#define	MOD_SEL1_TSIF0_E	((uint32_t)4U << 27U)
+#define	MOD_SEL1_TIMER_TMU_A	((uint32_t)0U << 26U)
+#define	MOD_SEL1_TIMER_TMU_B	((uint32_t)1U << 26U)
+#define	MOD_SEL1_SSP1_1_A	((uint32_t)0U << 24U)
+#define	MOD_SEL1_SSP1_1_B	((uint32_t)1U << 24U)
+#define	MOD_SEL1_SSP1_1_C	((uint32_t)2U << 24U)
+#define	MOD_SEL1_SSP1_1_D	((uint32_t)3U << 24U)
+#define	MOD_SEL1_SSP1_0_A	((uint32_t)0U << 21U)
+#define	MOD_SEL1_SSP1_0_B	((uint32_t)1U << 21U)
+#define	MOD_SEL1_SSP1_0_C	((uint32_t)2U << 21U)
+#define	MOD_SEL1_SSP1_0_D	((uint32_t)3U << 21U)
+#define	MOD_SEL1_SSP1_0_E	((uint32_t)4U << 21U)
+#define	MOD_SEL1_SSI_A		((uint32_t)0U << 20U)
+#define	MOD_SEL1_SSI_B		((uint32_t)1U << 20U)
+#define	MOD_SEL1_SPEED_PULSE_IF_A	((uint32_t)0U << 19U)
+#define	MOD_SEL1_SPEED_PULSE_IF_B	((uint32_t)1U << 19U)
+#define	MOD_SEL1_SIMCARD_A	((uint32_t)0U << 17U)
+#define	MOD_SEL1_SIMCARD_B	((uint32_t)1U << 17U)
+#define	MOD_SEL1_SIMCARD_C	((uint32_t)2U << 17U)
+#define	MOD_SEL1_SIMCARD_D	((uint32_t)3U << 17U)
+#define	MOD_SEL1_SDHI2_A	((uint32_t)0U << 16U)
+#define	MOD_SEL1_SDHI2_B	((uint32_t)1U << 16U)
+#define	MOD_SEL1_SCIF4_A	((uint32_t)0U << 14U)
+#define	MOD_SEL1_SCIF4_B	((uint32_t)1U << 14U)
+#define	MOD_SEL1_SCIF4_C	((uint32_t)2U << 14U)
+#define	MOD_SEL1_SCIF3_A	((uint32_t)0U << 13U)
+#define	MOD_SEL1_SCIF3_B	((uint32_t)1U << 13U)
+#define	MOD_SEL1_SCIF2_A	((uint32_t)0U << 12U)
+#define	MOD_SEL1_SCIF2_B	((uint32_t)1U << 12U)
+#define	MOD_SEL1_SCIF1_A	((uint32_t)0U << 11U)
+#define	MOD_SEL1_SCIF1_B	((uint32_t)1U << 11U)
+#define	MOD_SEL1_SCIF_A		((uint32_t)0U << 10U)
+#define	MOD_SEL1_SCIF_B		((uint32_t)1U << 10U)
+#define	MOD_SEL1_REMOCON_A	((uint32_t)0U << 9U)
+#define	MOD_SEL1_REMOCON_B	((uint32_t)1U << 9U)
+#define	MOD_SEL1_RCAN0_A	((uint32_t)0U << 6U)
+#define	MOD_SEL1_RCAN0_B	((uint32_t)1U << 6U)
+#define	MOD_SEL1_PWM6_A		((uint32_t)0U << 5U)
+#define	MOD_SEL1_PWM6_B		((uint32_t)1U << 5U)
+#define	MOD_SEL1_PWM5_A		((uint32_t)0U << 4U)
+#define	MOD_SEL1_PWM5_B		((uint32_t)1U << 4U)
+#define	MOD_SEL1_PWM4_A		((uint32_t)0U << 3U)
+#define	MOD_SEL1_PWM4_B		((uint32_t)1U << 3U)
+#define	MOD_SEL1_PWM3_A		((uint32_t)0U << 2U)
+#define	MOD_SEL1_PWM3_B		((uint32_t)1U << 2U)
+#define	MOD_SEL1_PWM2_A		((uint32_t)0U << 1U)
+#define	MOD_SEL1_PWM2_B		((uint32_t)1U << 1U)
+#define	MOD_SEL1_PWM1_A		((uint32_t)0U << 0U)
+#define	MOD_SEL1_PWM1_B		((uint32_t)1U << 0U)
+#define	MOD_SEL2_I2C_5_A	((uint32_t)0U << 31U)
+#define	MOD_SEL2_I2C_5_B	((uint32_t)1U << 31U)
+#define	MOD_SEL2_I2C_3_A	((uint32_t)0U << 30U)
+#define	MOD_SEL2_I2C_3_B	((uint32_t)1U << 30U)
+#define	MOD_SEL2_I2C_0_A	((uint32_t)0U << 29U)
+#define	MOD_SEL2_I2C_0_B	((uint32_t)1U << 29U)
+#define	MOD_SEL2_FM_A		((uint32_t)0U << 27U)
+#define	MOD_SEL2_FM_B		((uint32_t)1U << 27U)
+#define	MOD_SEL2_FM_C		((uint32_t)2U << 27U)
+#define	MOD_SEL2_FM_D		((uint32_t)3U << 27U)
+#define	MOD_SEL2_SCIF5_A	((uint32_t)0U << 26U)
+#define	MOD_SEL2_SCIF5_B	((uint32_t)1U << 26U)
+#define	MOD_SEL2_I2C6_A		((uint32_t)0U << 23U)
+#define	MOD_SEL2_I2C6_B		((uint32_t)1U << 23U)
+#define	MOD_SEL2_I2C6_C		((uint32_t)2U << 23U)
+#define	MOD_SEL2_NDF_A		((uint32_t)0U << 22U)
+#define	MOD_SEL2_NDF_B		((uint32_t)1U << 22U)
+#define	MOD_SEL2_SSI2_A		((uint32_t)0U << 21U)
+#define	MOD_SEL2_SSI2_B		((uint32_t)1U << 21U)
+#define	MOD_SEL2_SSI9_A		((uint32_t)0U << 20U)
+#define	MOD_SEL2_SSI9_B		((uint32_t)1U << 20U)
+#define	MOD_SEL2_TIMER_TMU2_A	((uint32_t)0U << 19U)
+#define	MOD_SEL2_TIMER_TMU2_B	((uint32_t)1U << 19U)
+#define	MOD_SEL2_ADG_B_A	((uint32_t)0U << 18U)
+#define	MOD_SEL2_ADG_B_B	((uint32_t)1U << 18U)
+#define	MOD_SEL2_ADG_C_A	((uint32_t)0U << 17U)
+#define	MOD_SEL2_ADG_C_B	((uint32_t)1U << 17U)
+#define	MOD_SEL2_VIN4_A		((uint32_t)0U << 0U)
+#define	MOD_SEL2_VIN4_B		((uint32_t)1U << 0U)
+
+
+/* SCIF3 Registers for Dummy write */
+#define SCIF3_BASE		(0xE6C50000U)
+#define SCIF3_SCFCR		(SCIF3_BASE + 0x0018U)
+#define SCIF3_SCFDR		(SCIF3_BASE + 0x001CU)
+#define SCFCR_DATA		(0x0000U)
+
+/* Realtime module stop control */
+#define	CPG_BASE		(0xE6150000U)
+#define CPG_MSTPSR0		(CPG_BASE + 0x0030U)
+#define CPG_RMSTPCR0		(CPG_BASE + 0x0110U)
+#define RMSTPCR0_RTDMAC		(0x00200000U)
+
+/* RT-DMAC Registers */
+#define RTDMAC_CH		(0U)		/* choose 0 to 15 */
+
+#define RTDMAC_BASE		(0xFFC10000U)
+#define RTDMAC_RDMOR		(RTDMAC_BASE + 0x0060U)
+#define RTDMAC_RDMCHCLR		(RTDMAC_BASE + 0x0080U)
+#define RTDMAC_RDMSAR(x)	(RTDMAC_BASE + 0x8000U + (0x80U * (x)))
+#define RTDMAC_RDMDAR(x)	(RTDMAC_BASE + 0x8004U + (0x80U * (x)))
+#define RTDMAC_RDMTCR(x)	(RTDMAC_BASE + 0x8008U + (0x80U * (x)))
+#define RTDMAC_RDMCHCR(x)	(RTDMAC_BASE + 0x800CU + (0x80U * (x)))
+#define RTDMAC_RDMCHCRB(x)	(RTDMAC_BASE + 0x801CU + (0x80U * (x)))
+#define RTDMAC_RDMDPBASE(x)	(RTDMAC_BASE + 0x8050U + (0x80U * (x)))
+#define RTDMAC_DESC_BASE	(RTDMAC_BASE + 0xA000U)
+#define RTDMAC_DESC_RDMSAR	(RTDMAC_DESC_BASE + 0x0000U)
+#define RTDMAC_DESC_RDMDAR	(RTDMAC_DESC_BASE + 0x0004U)
+#define RTDMAC_DESC_RDMTCR	(RTDMAC_DESC_BASE + 0x0008U)
+
+#define RDMOR_DME		(0x0001U)	/* DMA Master Enable */
+#define RDMCHCR_DPM_INFINITE	(0x30000000U)	/* Infinite repeat mode */
+#define RDMCHCR_RPT_TCR		(0x02000000U)	/* enable to update TCR */
+#define RDMCHCR_TS_2		(0x00000008U)	/* Word(2byte) units transfer */
+#define RDMCHCR_RS_AUTO		(0x00000400U)	/* Auto request */
+#define RDMCHCR_DE		(0x00000001U)	/* DMA Enable */
+#define RDMCHCRB_DRST		(0x00008000U)	/* Descriptor reset */
+#define RDMCHCRB_SLM_256	(0x00000080U)	/* once in 256 clock cycle */
+#define RDMDPBASE_SEL_EXT	(0x00000001U)	/* External memory use */
+
+
+static void pfc_reg_write(uint32_t addr, uint32_t data);
+
+static void pfc_reg_write(uint32_t addr, uint32_t data)
+{
+	uint32_t prr;
+
+	prr = mmio_read_32(RCAR_PRR);
+	prr &= (RCAR_PRODUCT_MASK | RCAR_CUT_MASK);
+
+	mmio_write_32(PFC_PMMR, ~data);
+	if (prr == (RCAR_PRODUCT_M3_CUT10)) {
+		mmio_write_16(SCIF3_SCFCR, SCFCR_DATA);	/* Dummy write */
+	}
+	mmio_write_32((uintptr_t)addr, data);
+	if (prr == (RCAR_PRODUCT_M3_CUT10)) {
+		mmio_write_16(SCIF3_SCFCR, SCFCR_DATA);	/* Dummy write */
+	}
+}
+
+
+void pfc_init_d3(void)
+{
+	/* initialize module select */
+	pfc_reg_write(PFC_MOD_SEL0, 0x00000000U);
+	pfc_reg_write(PFC_MOD_SEL1, 0x00000000U);
+
+	/* initialize peripheral function select */
+	pfc_reg_write(PFC_IPSR0,  0x00000001U);
+	pfc_reg_write(PFC_IPSR1,  0x00000000U);
+	pfc_reg_write(PFC_IPSR2,  0x00000000U);
+	pfc_reg_write(PFC_IPSR3,  0x00000000U);
+	pfc_reg_write(PFC_IPSR4,  0x00002000U);
+	pfc_reg_write(PFC_IPSR5,  0x00000000U);
+	pfc_reg_write(PFC_IPSR6,  0x00000000U);
+	pfc_reg_write(PFC_IPSR7,  0x00000000U);
+	pfc_reg_write(PFC_IPSR8,  0x11003301U);
+	pfc_reg_write(PFC_IPSR9,  0x11111111U);
+	pfc_reg_write(PFC_IPSR10, 0x00020000U);
+	pfc_reg_write(PFC_IPSR11, 0x40001110U);
+	pfc_reg_write(PFC_IPSR12, 0x00000000U);
+	pfc_reg_write(PFC_IPSR13, 0x00000000U);
+
+	/* initialize GPIO/perihperal function select */
+	pfc_reg_write(PFC_GPSR0, 0x0000001FU);
+	pfc_reg_write(PFC_GPSR1, 0x3FFFFFFFU);
+	pfc_reg_write(PFC_GPSR2, 0xFFFFFFFFU);
+	pfc_reg_write(PFC_GPSR3, 0x000003FFU);
+	pfc_reg_write(PFC_GPSR4, 0xFC7F0F7EU);
+	pfc_reg_write(PFC_GPSR5, 0x001BFFFBU);
+	pfc_reg_write(PFC_GPSR6, 0x00003FFFU);
+
+	/* initialize POC control register */
+	pfc_reg_write(PFC_POCCTRL0,   0xC00FFFFFU);
+	pfc_reg_write(PFC_POCCTRL1,   0XFFFFFFFEU);
+	pfc_reg_write(PFC_TDSELCTRL0, 0x00000000U);
+
+	/* initialize LSI pin pull-up/down control */
+	pfc_reg_write(PFC_PUD0, 0x0047C1A2U);
+	pfc_reg_write(PFC_PUD1, 0x4E13ABFFU);
+	pfc_reg_write(PFC_PUD2, 0xFFFFFFFFU);
+	pfc_reg_write(PFC_PUD3, 0xFF0FFFFFU);
+	pfc_reg_write(PFC_PUD4, 0xE0000000U);
+	pfc_reg_write(PFC_PUD5, 0x60000000U);
+                            
+	/* initialize LSI pin pull-enable register */
+	pfc_reg_write(PFC_PUEN0, 0x00000000U);
+	pfc_reg_write(PFC_PUEN1, 0x00000000U);
+	pfc_reg_write(PFC_PUEN2, 0x00000000U);
+	pfc_reg_write(PFC_PUEN3, 0x000F008CU);
+	pfc_reg_write(PFC_PUEN4, 0x00000000U);
+	pfc_reg_write(PFC_PUEN5, 0x00000000U);
+                             
+	/* initialize positive/negative logic select */
+	mmio_write_32(GPIO_POSNEG0, 0x00000000U);
+	mmio_write_32(GPIO_POSNEG1, 0x00000000U);
+	mmio_write_32(GPIO_POSNEG2, 0x00000000U);
+	mmio_write_32(GPIO_POSNEG3, 0x00000000U);
+	mmio_write_32(GPIO_POSNEG4, 0x00000000U);
+	mmio_write_32(GPIO_POSNEG5, 0x00000000U);
+	mmio_write_32(GPIO_POSNEG6, 0x00000000U);
+
+	/* initialize general IO/interrupt switching */
+	mmio_write_32(GPIO_IOINTSEL0, 0x00000000U);
+	mmio_write_32(GPIO_IOINTSEL1, 0x00000000U);
+	mmio_write_32(GPIO_IOINTSEL2, 0x00000000U);
+	mmio_write_32(GPIO_IOINTSEL3, 0x00000000U);
+	mmio_write_32(GPIO_IOINTSEL4, 0x00000000U);
+	mmio_write_32(GPIO_IOINTSEL5, 0x00000000U);
+	mmio_write_32(GPIO_IOINTSEL6, 0x00000000U);
+
+	/* initialize general output register */
+	mmio_write_32(GPIO_OUTDT0, 0x00000000U);
+	mmio_write_32(GPIO_OUTDT1, 0x00000000U);
+	mmio_write_32(GPIO_OUTDT2, 0x00000400U);
+	mmio_write_32(GPIO_OUTDT3, 0x00000000U);
+	mmio_write_32(GPIO_OUTDT4, 0x00000000U);
+	mmio_write_32(GPIO_OUTDT5, 0x00000006U);
+	mmio_write_32(GPIO_OUTDT6, 0x00003880U);
+
+	/* initialize general input/output switching */
+	mmio_write_32(GPIO_INOUTSEL0, 0x00000000U);
+	mmio_write_32(GPIO_INOUTSEL1, 0x00000000U);
+	mmio_write_32(GPIO_INOUTSEL2, 0x00000000U);
+	mmio_write_32(GPIO_INOUTSEL3, 0x00000000U);
+	mmio_write_32(GPIO_INOUTSEL4, 0x00802000U);
+	mmio_write_32(GPIO_INOUTSEL5, 0x00000000U);
+	mmio_write_32(GPIO_INOUTSEL6, 0x00000000U);
+}
diff --git a/drivers/staging/renesas/rcar/pfc/D3/pfc_init_d3.h b/drivers/staging/renesas/rcar/pfc/D3/pfc_init_d3.h
new file mode 100644
index 000000000..ee1fada3b
--- /dev/null
+++ b/drivers/staging/renesas/rcar/pfc/D3/pfc_init_d3.h
@@ -0,0 +1,12 @@
+/*
+ * Copyright (c) 2017, Renesas Electronics Corporation. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef PFC_INIT_D3_H__
+#define PFC_INIT_D3_H__
+
+void pfc_init_d3(void);
+
+#endif	/* PFC_INIT_D3_H__ */
diff --git a/drivers/staging/renesas/rcar/pfc/pfc.mk b/drivers/staging/renesas/rcar/pfc/pfc.mk
index 40e409000..5703558fa 100644
--- a/drivers/staging/renesas/rcar/pfc/pfc.mk
+++ b/drivers/staging/renesas/rcar/pfc/pfc.mk
@@ -28,6 +28,9 @@ else ifdef RCAR_LSI_CUT_COMPAT
   ifeq (${RCAR_LSI},${RCAR_E3})
     BL2_SOURCES += drivers/staging/renesas/rcar/pfc/E3/pfc_init_e3.c
   endif
+  ifeq (${RCAR_LSI},${RCAR_D3})
+    BL2_SOURCES += drivers/staging/renesas/rcar/pfc/D3/pfc_init_d3.c
+  endif
 else
   ifeq (${RCAR_LSI},${RCAR_H3})
     ifeq (${LSI_CUT},10)
@@ -51,6 +54,9 @@ else
   ifeq (${RCAR_LSI},${RCAR_E3})
     BL2_SOURCES += drivers/staging/renesas/rcar/pfc/E3/pfc_init_e3.c
   endif
+  ifeq (${RCAR_LSI},${RCAR_D3})
+    BL2_SOURCES += drivers/staging/renesas/rcar/pfc/D3/pfc_init_d3.c
+  endif
 endif
 
 BL2_SOURCES += drivers/staging/renesas/rcar/pfc/pfc_init.c
diff --git a/drivers/staging/renesas/rcar/pfc/pfc_init.c b/drivers/staging/renesas/rcar/pfc/pfc_init.c
index f20e8b0b5..cec562409 100644
--- a/drivers/staging/renesas/rcar/pfc/pfc_init.c
+++ b/drivers/staging/renesas/rcar/pfc/pfc_init.c
@@ -29,6 +29,9 @@
 #if RCAR_LSI == RCAR_E3		/* E3 */
 #include "E3/pfc_init_e3.h"
 #endif
+#if RCAR_LSI == RCAR_D3		/* D3 */
+#include "D3/pfc_init_d3.h"
+#endif
 
  /* Product Register */
 #define PRR			(0xFFF00044U)
@@ -38,6 +41,7 @@
 #define PRR_PRODUCT_M3		(0x00005200U)	/* R-Car M3 */
 #define PRR_PRODUCT_M3N		(0x00005500U)	/* R-Car M3N */
 #define PRR_PRODUCT_E3		(0x00005700U)	/* R-Car E3 */
+#define PRR_PRODUCT_D3		(0x00005800U)	/* R-Car D3 */
 #define PRR_PRODUCT_10		(0x00U)
 #define PRR_PRODUCT_11		(0x01U)
 #define PRR_PRODUCT_20		(0x10U)
@@ -124,6 +128,13 @@ void rcar_pfc_init(void)
 		pfc_init_e3();
 #endif
 		break;
+	case PRR_PRODUCT_D3:
+#if RCAR_LSI != RCAR_D3
+		PRR_PRODUCT_ERR(reg);
+#else
+		pfc_init_d3();
+#endif
+		break;
 	default:
 		PRR_PRODUCT_ERR(reg);
 		break;
@@ -167,6 +178,11 @@ void rcar_pfc_init(void)
 		PRR_PRODUCT_ERR(reg);
 	}
 	pfc_init_e3();
+#elif RCAR_LSI == RCAR_D3	/* D3 */
+	if ((PRR_PRODUCT_D3) != (reg & PRR_PRODUCT_MASK)) {
+		PRR_PRODUCT_ERR(reg);
+	}
+	pfc_init_d3();
 #else
 #error "Don't have PFC initialize routine(unknown)."
 #endif
diff --git a/drivers/staging/renesas/rcar/qos/D3/qos_init_d3.c b/drivers/staging/renesas/rcar/qos/D3/qos_init_d3.c
new file mode 100644
index 000000000..b115d633b
--- /dev/null
+++ b/drivers/staging/renesas/rcar/qos/D3/qos_init_d3.c
@@ -0,0 +1,581 @@
+/*
+ * Copyright (c) 2015-2017, Renesas Electronics Corporation. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <stdint.h>
+#include <common/debug.h>
+#include "qos_init_d3.h"
+
+
+#define	RCAR_QOS_VERSION		"rev.0.05"
+
+#define	RCAR_QOS_NONE			(3U)
+#define	RCAR_QOS_TYPE_DEFAULT		(0U)
+
+#define	RCAR_DRAM_SPLIT_LINEAR		(0U)
+#define	RCAR_DRAM_SPLIT_4CH		(1U)
+#define	RCAR_DRAM_SPLIT_2CH		(2U)
+#define	RCAR_DRAM_SPLIT_AUTO		(3U)
+
+#define	RST_BASE			(0xE6160000U)
+#define	RST_MODEMR			(RST_BASE + 0x0060U)
+
+#define	DBSC_BASE			(0xE6790000U)
+#define	DBSC_DBSYSCNT0			(DBSC_BASE + 0x0100U)
+#define	DBSC_AXARB			(DBSC_BASE + 0x0800U)
+#define DBSC_DBCAM0CNF0			(DBSC_BASE + 0x0900U)
+#define DBSC_DBCAM0CNF1			(DBSC_BASE + 0x0904U)
+#define DBSC_DBCAM0CNF2			(DBSC_BASE + 0x0908U)
+#define DBSC_DBCAM0CNF3			(DBSC_BASE + 0x090CU)
+#define DBSC_DBCAMDIS			(DBSC_BASE + 0x09fCU)
+#define DBSC_DBSCHCNT0			(DBSC_BASE + 0x1000U)
+#define DBSC_DBSCHCNT1			(DBSC_BASE + 0x1004U)
+#define DBSC_DBSCHSZ0			(DBSC_BASE + 0x1010U)
+#define DBSC_DBSCHRW0			(DBSC_BASE + 0x1020U)
+#define DBSC_DBSCHRW1			(DBSC_BASE + 0x1024U)
+#define DBSC_DBSCHQOS_0_0		(DBSC_BASE + 0x1030U)
+#define DBSC_DBSCHQOS_0_1		(DBSC_BASE + 0x1034U)
+#define DBSC_DBSCHQOS_0_2		(DBSC_BASE + 0x1038U)
+#define DBSC_DBSCHQOS_0_3		(DBSC_BASE + 0x103CU)
+#define DBSC_DBSCHQOS_1_0		(DBSC_BASE + 0x1040U)
+#define DBSC_DBSCHQOS_1_1		(DBSC_BASE + 0x1044U)
+#define DBSC_DBSCHQOS_1_2		(DBSC_BASE + 0x1048U)
+#define DBSC_DBSCHQOS_1_3		(DBSC_BASE + 0x104CU)
+#define DBSC_DBSCHQOS_2_0		(DBSC_BASE + 0x1050U)
+#define DBSC_DBSCHQOS_2_1		(DBSC_BASE + 0x1054U)
+#define DBSC_DBSCHQOS_2_2		(DBSC_BASE + 0x1058U)
+#define DBSC_DBSCHQOS_2_3		(DBSC_BASE + 0x105CU)
+#define DBSC_DBSCHQOS_3_0		(DBSC_BASE + 0x1060U)
+#define DBSC_DBSCHQOS_3_1		(DBSC_BASE + 0x1064U)
+#define DBSC_DBSCHQOS_3_2		(DBSC_BASE + 0x1068U)
+#define DBSC_DBSCHQOS_3_3		(DBSC_BASE + 0x106CU)
+#define DBSC_DBSCHQOS_4_0		(DBSC_BASE + 0x1070U)
+#define DBSC_DBSCHQOS_4_1		(DBSC_BASE + 0x1074U)
+#define DBSC_DBSCHQOS_4_2		(DBSC_BASE + 0x1078U)
+#define DBSC_DBSCHQOS_4_3		(DBSC_BASE + 0x107CU)
+#define DBSC_DBSCHQOS_5_0		(DBSC_BASE + 0x1080U)
+#define DBSC_DBSCHQOS_5_1		(DBSC_BASE + 0x1084U)
+#define DBSC_DBSCHQOS_5_2		(DBSC_BASE + 0x1088U)
+#define DBSC_DBSCHQOS_5_3		(DBSC_BASE + 0x108CU)
+#define DBSC_DBSCHQOS_6_0		(DBSC_BASE + 0x1090U)
+#define DBSC_DBSCHQOS_6_1		(DBSC_BASE + 0x1094U)
+#define DBSC_DBSCHQOS_6_2		(DBSC_BASE + 0x1098U)
+#define DBSC_DBSCHQOS_6_3		(DBSC_BASE + 0x109CU)
+#define DBSC_DBSCHQOS_7_0		(DBSC_BASE + 0x10A0U)
+#define DBSC_DBSCHQOS_7_1		(DBSC_BASE + 0x10A4U)
+#define DBSC_DBSCHQOS_7_2		(DBSC_BASE + 0x10A8U)
+#define DBSC_DBSCHQOS_7_3		(DBSC_BASE + 0x10ACU)
+#define DBSC_DBSCHQOS_8_0		(DBSC_BASE + 0x10B0U)
+#define DBSC_DBSCHQOS_8_1		(DBSC_BASE + 0x10B4U)
+#define DBSC_DBSCHQOS_8_2		(DBSC_BASE + 0x10B8U)
+#define DBSC_DBSCHQOS_8_3		(DBSC_BASE + 0x10BCU)
+#define DBSC_DBSCHQOS_9_0		(DBSC_BASE + 0x10C0U)
+#define DBSC_DBSCHQOS_9_1		(DBSC_BASE + 0x10C4U)
+#define DBSC_DBSCHQOS_9_2		(DBSC_BASE + 0x10C8U)
+#define DBSC_DBSCHQOS_9_3		(DBSC_BASE + 0x10CCU)
+#define DBSC_DBSCHQOS_10_0		(DBSC_BASE + 0x10D0U)
+#define DBSC_DBSCHQOS_10_1		(DBSC_BASE + 0x10D4U)
+#define DBSC_DBSCHQOS_10_2		(DBSC_BASE + 0x10D8U)
+#define DBSC_DBSCHQOS_10_3		(DBSC_BASE + 0x10DCU)
+#define DBSC_DBSCHQOS_11_0		(DBSC_BASE + 0x10E0U)
+#define DBSC_DBSCHQOS_11_1		(DBSC_BASE + 0x10E4U)
+#define DBSC_DBSCHQOS_11_2		(DBSC_BASE + 0x10E8U)
+#define DBSC_DBSCHQOS_11_3		(DBSC_BASE + 0x10ECU)
+#define DBSC_DBSCHQOS_12_0		(DBSC_BASE + 0x10F0U)
+#define DBSC_DBSCHQOS_12_1		(DBSC_BASE + 0x10F4U)
+#define DBSC_DBSCHQOS_12_2		(DBSC_BASE + 0x10F8U)
+#define DBSC_DBSCHQOS_12_3		(DBSC_BASE + 0x10FCU)
+#define DBSC_DBSCHQOS_13_0		(DBSC_BASE + 0x1100U)
+#define DBSC_DBSCHQOS_13_1		(DBSC_BASE + 0x1104U)
+#define DBSC_DBSCHQOS_13_2		(DBSC_BASE + 0x1108U)
+#define DBSC_DBSCHQOS_13_3		(DBSC_BASE + 0x110CU)
+#define DBSC_DBSCHQOS_14_0		(DBSC_BASE + 0x1110U)
+#define DBSC_DBSCHQOS_14_1		(DBSC_BASE + 0x1114U)
+#define DBSC_DBSCHQOS_14_2		(DBSC_BASE + 0x1118U)
+#define DBSC_DBSCHQOS_14_3		(DBSC_BASE + 0x111CU)
+#define DBSC_DBSCHQOS_15_0		(DBSC_BASE + 0x1120U)
+#define DBSC_DBSCHQOS_15_1		(DBSC_BASE + 0x1124U)
+#define DBSC_DBSCHQOS_15_2		(DBSC_BASE + 0x1128U)
+#define DBSC_DBSCHQOS_15_3		(DBSC_BASE + 0x112CU)
+#define DBSC_SCFCTST2			(DBSC_BASE + 0x170CU)
+
+#define	AXI_BASE			(0xE6784000U)
+#define	AXI_ADSPLCR0			(AXI_BASE + 0x0008U)
+#define	AXI_ADSPLCR3			(AXI_BASE + 0x0014U)
+
+#define	MSTAT_BASE			(0xE67E0000U)
+#define	MSTAT_FIX_QOS_BANK0		(MSTAT_BASE + 0x0000U)
+#define	MSTAT_FIX_QOS_BANK1		(MSTAT_BASE + 0x1000U)
+#define	MSTAT_BE_QOS_BANK0		(MSTAT_BASE + 0x2000U)
+#define	MSTAT_BE_QOS_BANK1		(MSTAT_BASE + 0x3000U)
+#define	MSTAT_SL_INIT			(MSTAT_BASE + 0x8000U)
+#define	MSTAT_REF_ARS			(MSTAT_BASE + 0x8004U)
+#define	MSTAT_STATQC			(MSTAT_BASE + 0x8008U)
+
+#define	RALLOC_BASE			(0xE67F0000U)
+#define	RALLOC_RAS			(RALLOC_BASE + 0x0000U)
+#define	RALLOC_FIXTH			(RALLOC_BASE + 0x0004U)
+#define	RALLOC_RAEN			(RALLOC_BASE + 0x0018U)
+#define	RALLOC_REGGD			(RALLOC_BASE + 0x0020U)
+#define	RALLOC_DANN			(RALLOC_BASE + 0x0030U)
+#define	RALLOC_DANT			(RALLOC_BASE + 0x0038U)
+#define	RALLOC_EC			(RALLOC_BASE + 0x003CU)
+#define	RALLOC_EMS			(RALLOC_BASE + 0x0040U)
+#define	RALLOC_FSS			(RALLOC_BASE + 0x0048U)
+#define	RALLOC_INSFC			(RALLOC_BASE + 0x0050U)
+#define	RALLOC_BERR			(RALLOC_BASE + 0x0054U)
+#define	RALLOC_EARLYR			(RALLOC_BASE + 0x0060U)
+#define	RALLOC_RACNT0			(RALLOC_BASE + 0x0080U)
+#define	RALLOC_TICKDUPL			(RALLOC_BASE + 0x0088U)
+
+#define ARRAY_SIZE(a)	(sizeof(a) / sizeof((a)[0]))
+
+static inline void io_write_32(uintptr_t addr, uint32_t value)
+{
+	*(volatile uint32_t*)addr = value;
+}
+
+static inline void io_write_64(uintptr_t addr, uint64_t value)
+{
+	*(volatile uint64_t*)addr = value;
+}
+
+typedef struct {
+	uintptr_t addr;
+	uint64_t value;
+} mstat_slot_t;
+
+
+#if RCAR_QOS_TYPE  == RCAR_QOS_TYPE_DEFAULT
+static const mstat_slot_t mstat_fix[] = {
+	{0x0000U, 0x0000000000000000U},
+	{0x0008U, 0x0000000000000000U},
+	{0x0010U, 0x0000000000000000U},
+	{0x0018U, 0x0000000000000000U},
+	{0x0020U, 0x0000000000000000U},
+	{0x0028U, 0x0000000000000000U},
+	{0x0030U, 0x001004340000FFFFU},
+	{0x0038U, 0x001004140000FFFFU},
+	{0x0040U, 0x0000000000000000U},
+	{0x0048U, 0x0000000000000000U},
+	{0x0050U, 0x0000000000000000U},
+	{0x0058U, 0x00140B030000FFFFU},
+	{0x0060U, 0x001408610000FFFFU},
+	{0x0068U, 0x0000000000000000U},
+	{0x0070U, 0x0000000000000000U},
+	{0x0078U, 0x0000000000000000U},
+	{0x0080U, 0x0000000000000000U},
+	{0x0088U, 0x001410620000FFFFU},
+	{0x0090U, 0x0000000000000000U},
+	{0x0098U, 0x0000000000000000U},
+	{0x00A0U, 0x000C041C0000FFFFU},
+	{0x00A8U, 0x000C04090000FFFFU},
+	{0x00B0U, 0x000C04110000FFFFU},
+	{0x00B8U, 0x0000000000000000U},
+	{0x00C0U, 0x000C041C0000FFFFU},
+	{0x00C8U, 0x000C04090000FFFFU},
+	{0x00D0U, 0x000C04110000FFFFU},
+	{0x00D8U, 0x0000000000000000U},
+	{0x00E0U, 0x0000000000000000U},
+	{0x00E8U, 0x0000000000000000U},
+	{0x00F0U, 0x001018570000FFFFU},
+	{0x00F8U, 0x0000000000000000U},
+	{0x0100U, 0x0000000000000000U},
+	{0x0108U, 0x0000000000000000U},
+	{0x0110U, 0x001008570000FFFFU},
+	{0x0118U, 0x0000000000000000U},
+	{0x0120U, 0x0000000000000000U},
+	{0x0128U, 0x0000000000000000U},
+	{0x0130U, 0x0000000000000000U},
+	{0x0138U, 0x0000000000000000U},
+	{0x0140U, 0x0000000000000000U},
+	{0x0148U, 0x0000000000000000U},
+	{0x0150U, 0x001008520000FFFFU},
+	{0x0158U, 0x0000000000000000U},
+	{0x0160U, 0x0000000000000000U},
+	{0x0168U, 0x0000000000000000U},
+	{0x0170U, 0x0000000000000000U},
+	{0x0178U, 0x0000000000000000U},
+	{0x0180U, 0x0000000000000000U},
+	{0x0188U, 0x0000000000000000U},
+	{0x0190U, 0x00100CA30000FFFFU},
+	{0x0198U, 0x0000000000000000U},
+	{0x01A0U, 0x0000000000000000U},
+	{0x01A8U, 0x0000000000000000U},
+	{0x01B0U, 0x0000000000000000U},
+	{0x01B8U, 0x0000000000000000U},
+	{0x01C0U, 0x0000000000000000U},
+	{0x01C8U, 0x0000000000000000U},
+	{0x01D0U, 0x0000000000000000U},
+	{0x01D8U, 0x0000000000000000U},
+	{0x01E0U, 0x0000000000000000U},
+	{0x01E8U, 0x000C04020000FFFFU},
+	{0x01F0U, 0x0000000000000000U},
+	{0x01F8U, 0x0000000000000000U},
+	{0x0200U, 0x0000000000000000U},
+	{0x0208U, 0x000C04090000FFFFU},
+	{0x0210U, 0x0000000000000000U},
+	{0x0218U, 0x0000000000000000U},
+	{0x0220U, 0x0000000000000000U},
+	{0x0228U, 0x0000000000000000U},
+	{0x0230U, 0x0000000000000000U},
+	{0x0238U, 0x0000000000000000U},
+	{0x0240U, 0x0000000000000000U},
+	{0x0248U, 0x0000000000000000U},
+	{0x0250U, 0x0000000000000000U},
+	{0x0258U, 0x0000000000000000U},
+	{0x0260U, 0x0000000000000000U},
+	{0x0268U, 0x001410040000FFFFU},
+	{0x0270U, 0x001404020000FFFFU},
+	{0x0278U, 0x0000000000000000U},
+	{0x0280U, 0x0000000000000000U},
+	{0x0288U, 0x0000000000000000U},
+	{0x0290U, 0x001410040000FFFFU},
+	{0x0298U, 0x001404020000FFFFU},
+	{0x02A0U, 0x000C04050000FFFFU},
+	{0x02A8U, 0x000C04050000FFFFU},
+	{0x02B0U, 0x0000000000000000U},
+	{0x02B8U, 0x0000000000000000U},
+	{0x02C0U, 0x0000000000000000U},
+	{0x02C8U, 0x0000000000000000U},
+	{0x02D0U, 0x000C04050000FFFFU},
+	{0x02D8U, 0x000C04050000FFFFU},
+	{0x02E0U, 0x0000000000000000U},
+	{0x02E8U, 0x0000000000000000U},
+	{0x02F0U, 0x0000000000000000U},
+	{0x02F8U, 0x0000000000000000U},
+	{0x0300U, 0x0000000000000000U},
+	{0x0308U, 0x0000000000000000U},
+	{0x0310U, 0x0000000000000000U},
+	{0x0318U, 0x0000000000000000U},
+	{0x0320U, 0x0000000000000000U},
+	{0x0328U, 0x0000000000000000U},
+	{0x0330U, 0x0000000000000000U},
+	{0x0338U, 0x0000000000000000U},
+	{0x0340U, 0x0000000000000000U},
+	{0x0348U, 0x0000000000000000U},
+	{0x0350U, 0x0000000000000000U},
+	{0x0358U, 0x0000000000000000U},
+	{0x0360U, 0x0000000000000000U},
+	{0x0368U, 0x0000000000000000U},
+	{0x0370U, 0x000C04020000FFFFU},
+	{0x0378U, 0x000C04020000FFFFU},
+	{0x0380U, 0x000C04090000FFFFU},
+	{0x0388U, 0x000C04090000FFFFU},
+	{0x0390U, 0x0000000000000000U},
+};
+
+static const mstat_slot_t mstat_be[] = {
+	{0x0000U, 0x0000000000000000U},
+	{0x0008U, 0x0000000000000000U},
+	{0x0010U, 0x0000000000000000U},
+	{0x0018U, 0x0000000000000000U},
+	{0x0020U, 0x0000000000000000U},
+	{0x0028U, 0x0000000000000000U},
+	{0x0030U, 0x0000000000000000U},
+	{0x0038U, 0x0000000000000000U},
+	{0x0040U, 0x0000000000000000U},
+	{0x0048U, 0x0000000000000000U},
+	{0x0050U, 0x0000000000000000U},
+	{0x0058U, 0x0000000000000000U},
+	{0x0060U, 0x0000000000000000U},
+	{0x0068U, 0x0000000000000000U},
+	{0x0070U, 0x0000000000000000U},
+	{0x0078U, 0x0000000000000000U},
+	{0x0080U, 0x0000000000000000U},
+	{0x0088U, 0x0000000000000000U},
+	{0x0090U, 0x0000000000000000U},
+	{0x0098U, 0x0000000000000000U},
+	{0x00A0U, 0x0000000000000000U},
+	{0x00A8U, 0x0000000000000000U},
+	{0x00B0U, 0x0000000000000000U},
+	{0x00B8U, 0x0000000000000000U},
+	{0x00C0U, 0x0000000000000000U},
+	{0x00C8U, 0x0000000000000000U},
+	{0x00D0U, 0x0000000000000000U},
+	{0x00D8U, 0x0000000000000000U},
+	{0x00E0U, 0x0000000000000000U},
+	{0x00E8U, 0x0000000000000000U},
+	{0x00F0U, 0x0000000000000000U},
+	{0x00F8U, 0x0000000000000000U},
+	{0x0100U, 0x0000000000000000U},
+	{0x0108U, 0x0000000000000000U},
+	{0x0110U, 0x0000000000000000U},
+	{0x0118U, 0x0000000000000000U},
+	{0x0120U, 0x0000000000000000U},
+	{0x0128U, 0x0000000000000000U},
+	{0x0130U, 0x0000000000000000U},
+	{0x0138U, 0x0000000000000000U},
+	{0x0140U, 0x0000000000000000U},
+	{0x0148U, 0x0000000000000000U},
+	{0x0150U, 0x0000000000000000U},
+	{0x0158U, 0x0000000000000000U},
+	{0x0160U, 0x0000000000000000U},
+	{0x0168U, 0x0000000000000000U},
+	{0x0170U, 0x0000000000000000U},
+	{0x0178U, 0x0000000000000000U},
+	{0x0180U, 0x0000000000000000U},
+	{0x0188U, 0x0000000000000000U},
+	{0x0190U, 0x0000000000000000U},
+	{0x0198U, 0x0000000000000000U},
+	{0x01A0U, 0x0000000000000000U},
+	{0x01A8U, 0x0000000000000000U},
+	{0x01B0U, 0x0000000000000000U},
+	{0x01B8U, 0x0000000000000000U},
+	{0x01C0U, 0x00110090060FA001U},
+	{0x01C8U, 0x00110090060FA001U},
+	{0x01D0U, 0x0000000000000000U},
+	{0x01D8U, 0x0000000000000000U},
+	{0x01E0U, 0x0000000000000000U},
+	{0x01E8U, 0x0000000000000000U},
+	{0x01F0U, 0x0011001006004401U},
+	{0x01F8U, 0x0000000000000000U},
+	{0x0200U, 0x0000000000000000U},
+	{0x0208U, 0x0000000000000000U},
+	{0x0210U, 0x0011001006004401U},
+	{0x0218U, 0x0011001006009801U},
+	{0x0220U, 0x0011001006009801U},
+	{0x0228U, 0x0000000000000000U},
+	{0x0230U, 0x0011001006009801U},
+	{0x0238U, 0x0011001006009801U},
+	{0x0240U, 0x0000000000000000U},
+	{0x0248U, 0x0000000000000000U},
+	{0x0250U, 0x0000000000000000U},
+	{0x0258U, 0x0000000000000000U},
+	{0x0260U, 0x0000000000000000U},
+	{0x0268U, 0x0000000000000000U},
+	{0x0270U, 0x0000000000000000U},
+	{0x0278U, 0x0000000000000000U},
+	{0x0280U, 0x0000000000000000U},
+	{0x0288U, 0x0000000000000000U},
+	{0x0290U, 0x0000000000000000U},
+	{0x0298U, 0x0000000000000000U},
+	{0x02A0U, 0x0000000000000000U},
+	{0x02A8U, 0x0000000000000000U},
+	{0x02B0U, 0x0000000000000000U},
+	{0x02B8U, 0x0011001006003401U},
+	{0x02C0U, 0x0000000000000000U},
+	{0x02C8U, 0x0000000000000000U},
+	{0x02D0U, 0x0000000000000000U},
+	{0x02D8U, 0x0000000000000000U},
+	{0x02E0U, 0x0000000000000000U},
+	{0x02E8U, 0x0011001006003401U},
+	{0x02F0U, 0x00110090060FA001U},
+	{0x02F8U, 0x00110090060FA001U},
+	{0x0300U, 0x0000000000000000U},
+	{0x0308U, 0x0000000000000000U},
+	{0x0310U, 0x0000000000000000U},
+	{0x0318U, 0x0012001006003401U},
+	{0x0320U, 0x0000000000000000U},
+	{0x0328U, 0x0000000000000000U},
+	{0x0330U, 0x0000000000000000U},
+	{0x0338U, 0x0000000000000000U},
+	{0x0340U, 0x0000000000000000U},
+	{0x0348U, 0x0000000000000000U},
+	{0x0350U, 0x0000000000000000U},
+	{0x0358U, 0x00120090060FA001U},
+	{0x0360U, 0x00120090060FA001U},
+	{0x0368U, 0x0012001006003401U},
+	{0x0370U, 0x0000000000000000U},
+	{0x0378U, 0x0000000000000000U},
+	{0x0380U, 0x0000000000000000U},
+	{0x0388U, 0x0000000000000000U},
+	{0x0390U, 0x0012001006003401U},
+};
+#endif
+
+static void dbsc_setting(void)
+{
+	uint32_t md=0;
+
+	/* BUFCAM settings */
+	//DBSC_DBCAM0CNF0 not set
+	io_write_32(DBSC_DBCAM0CNF1, 0x00043218);	//dbcam0cnf1
+	io_write_32(DBSC_DBCAM0CNF2, 0x000000F4);	//dbcam0cnf2
+	io_write_32(DBSC_DBSCHCNT0,  0x000F0037);	//dbschcnt0
+	//DBSC_DBSCHCNT1 not set
+	io_write_32(DBSC_DBSCHSZ0,   0x00000001);	//dbschsz0
+	io_write_32(DBSC_DBSCHRW0,   0x22421111);	//dbschrw0
+
+	md = (*((volatile uint32_t*)RST_MODEMR) & 0x00080000) >> 19;
+
+	switch (md) {
+	case 0x0:	//MD19=0 : DDR3L-1600, 4GByte(1GByte x4)
+		/* DDR1600 */
+		io_write_32(DBSC_SCFCTST2, 0x012F1123);
+		break;
+	default:	//MD19=1 : DDR3L-1856, 4GByte(1GByte x4)
+		/* DDR1856 */
+		io_write_32(DBSC_SCFCTST2, 0x012F1123);
+		break;
+	}
+
+	/* QoS Settings */
+	io_write_32(DBSC_DBSCHQOS_0_0,  0x00000F00);
+	io_write_32(DBSC_DBSCHQOS_0_1,  0x00000B00);
+	io_write_32(DBSC_DBSCHQOS_0_2,  0x00000000);
+	io_write_32(DBSC_DBSCHQOS_0_3,  0x00000000);
+	//DBSC_DBSCHQOS_1_0 not set
+	//DBSC_DBSCHQOS_1_1 not set
+	//DBSC_DBSCHQOS_1_2 not set
+	//DBSC_DBSCHQOS_1_3 not set
+	//DBSC_DBSCHQOS_2_0 not set
+	//DBSC_DBSCHQOS_2_1 not set
+	//DBSC_DBSCHQOS_2_2 not set
+	//DBSC_DBSCHQOS_2_3 not set
+	//DBSC_DBSCHQOS_3_0 not set
+	//DBSC_DBSCHQOS_3_1 not set
+	//DBSC_DBSCHQOS_3_2 not set
+	//DBSC_DBSCHQOS_3_3 not set
+	io_write_32(DBSC_DBSCHQOS_4_0,  0x00000300);
+	io_write_32(DBSC_DBSCHQOS_4_1,  0x000002F0);
+	io_write_32(DBSC_DBSCHQOS_4_2,  0x00000200);
+	io_write_32(DBSC_DBSCHQOS_4_3,  0x00000100);
+	//DBSC_DBSCHQOS_5_0 not set
+	//DBSC_DBSCHQOS_5_1 not set
+	//DBSC_DBSCHQOS_5_2 not set
+	//DBSC_DBSCHQOS_5_3 not set
+	//DBSC_DBSCHQOS_6_0 not set
+	//DBSC_DBSCHQOS_6_1 not set
+	//DBSC_DBSCHQOS_6_2 not set
+	//DBSC_DBSCHQOS_6_3 not set
+	//DBSC_DBSCHQOS_7_0 not set
+	//DBSC_DBSCHQOS_7_1 not set
+	//DBSC_DBSCHQOS_7_2 not set
+	//DBSC_DBSCHQOS_7_3 not set
+	//DBSC_DBSCHQOS_8_0 not set
+	//DBSC_DBSCHQOS_8_1 not set
+	//DBSC_DBSCHQOS_8_2 not set
+	//DBSC_DBSCHQOS_8_3 not set
+	io_write_32(DBSC_DBSCHQOS_9_0,  0x00000300);
+	io_write_32(DBSC_DBSCHQOS_9_1,  0x000002F0);
+	io_write_32(DBSC_DBSCHQOS_9_2,  0x00000200);
+	io_write_32(DBSC_DBSCHQOS_9_3,  0x00000100);
+	//DBSC_DBSCHQOS_10_0 not set
+	//DBSC_DBSCHQOS_10_1 not set
+	//DBSC_DBSCHQOS_10_2 not set
+	//DBSC_DBSCHQOS_10_3 not set
+	//DBSC_DBSCHQOS_11_0 not set
+	//DBSC_DBSCHQOS_11_1 not set
+	//DBSC_DBSCHQOS_11_2 not set
+	//DBSC_DBSCHQOS_11_3 not set
+	//DBSC_DBSCHQOS_12_0 not set
+	//DBSC_DBSCHQOS_12_1 not set
+	//DBSC_DBSCHQOS_12_2 not set
+	//DBSC_DBSCHQOS_12_3 not set
+	io_write_32(DBSC_DBSCHQOS_13_0, 0x00000100);
+	io_write_32(DBSC_DBSCHQOS_13_1, 0x000000F0);
+	io_write_32(DBSC_DBSCHQOS_13_2, 0x000000A0);
+	io_write_32(DBSC_DBSCHQOS_13_3, 0x00000040);
+	io_write_32(DBSC_DBSCHQOS_14_0, 0x000000C0);
+	io_write_32(DBSC_DBSCHQOS_14_1, 0x000000B0);
+	io_write_32(DBSC_DBSCHQOS_14_2, 0x00000080);
+	io_write_32(DBSC_DBSCHQOS_14_3, 0x00000040);
+	io_write_32(DBSC_DBSCHQOS_15_0, 0x00000040);
+	io_write_32(DBSC_DBSCHQOS_15_1, 0x00000030);
+	io_write_32(DBSC_DBSCHQOS_15_2, 0x00000020);
+	io_write_32(DBSC_DBSCHQOS_15_3, 0x00000010);
+}
+
+void qos_init_d3(void)
+{
+	io_write_32(DBSC_DBSYSCNT0, 0x00001234);
+
+	dbsc_setting();
+
+	/* DRAM Split Address mapping */
+#if RCAR_DRAM_SPLIT == RCAR_DRAM_SPLIT_4CH
+	ERROR("DRAM Split 4ch not supported.(D3)");
+	panic();
+#elif RCAR_DRAM_SPLIT == RCAR_DRAM_SPLIT_2CH
+	ERROR("DRAM Split 2ch not supported.(D3)");
+	panic();
+#elif RCAR_DRAM_SPLIT == RCAR_DRAM_SPLIT_AUTO
+	ERROR("DRAM Split Auto not supported.(D3)");
+	panic();
+#elif RCAR_DRAM_SPLIT == RCAR_DRAM_SPLIT_LINEAR
+/*	NOTICE("BL2: DRAM Split is OFF\n"); */
+	/* Split setting(DDR 1ch) */
+	io_write_32(AXI_ADSPLCR0, 0x00000000U);
+	io_write_32(AXI_ADSPLCR3, 0x00000000U);
+#else
+	ERROR("DRAM split is an invalid value.(D3)");
+	panic();
+#endif
+
+#if !(RCAR_QOS_TYPE == RCAR_QOS_NONE)
+#if RCAR_QOS_TYPE  == RCAR_QOS_TYPE_DEFAULT
+	NOTICE("BL2: QoS is default setting(%s)\n", RCAR_QOS_VERSION);
+#endif
+
+	/* Resource Alloc setting */
+	io_write_32(RALLOC_RAS,   0x00000020U);
+	io_write_32(RALLOC_FIXTH, 0x000F0005U);
+	io_write_32(RALLOC_RAEN,  0x00000001U);
+	io_write_32(RALLOC_REGGD, 0x00000000U);
+	io_write_64(RALLOC_DANN,  0x0404020002020201U);
+	io_write_32(RALLOC_DANT,  0x00100804U);
+	io_write_32(RALLOC_EC,    0x00000000U);
+	io_write_64(RALLOC_EMS,   0x0000000000000000U);
+	io_write_32(RALLOC_FSS,   0x0000000AU);
+	io_write_32(RALLOC_INSFC, 0xC7840001U);
+	io_write_32(RALLOC_BERR,  0x00000000U);
+	io_write_32(RALLOC_EARLYR,  0x00000000U);
+	io_write_32(RALLOC_RACNT0,  0x00010003U);
+	io_write_32(RALLOC_TICKDUPL, 0x00000000U);
+
+	/* GPU setting */
+	io_write_32(0xFD812030U, 0x00000000U);
+
+	/* MSTAT setting */
+	io_write_32(MSTAT_SL_INIT, 0x030500ACU);
+	io_write_32(MSTAT_REF_ARS, 0x00780000U);
+
+	/* MSTAT SRAM setting */
+	{
+	uint32_t i;
+
+	for (i = 0U; i < ARRAY_SIZE(mstat_fix); i++) {
+		io_write_64(MSTAT_FIX_QOS_BANK0 + mstat_fix[i].addr,
+				mstat_fix[i].value);
+		io_write_64(MSTAT_FIX_QOS_BANK1 + mstat_fix[i].addr,
+				mstat_fix[i].value);
+	}
+	for (i = 0U; i < ARRAY_SIZE(mstat_be); i++) {
+		io_write_64(MSTAT_BE_QOS_BANK0 + mstat_be[i].addr,
+				mstat_be[i].value);
+		io_write_64(MSTAT_BE_QOS_BANK1 + mstat_be[i].addr,
+				mstat_be[i].value);
+	}
+	}
+
+	/* 3DG bus Leaf setting */
+	io_write_32(0xFD820808U, 0x00001234U);
+	io_write_32(0xFD820800U, 0x00000000U);
+	io_write_32(0xFD821800U, 0x00000000U);
+	io_write_32(0xFD822800U, 0x00000000U);
+	io_write_32(0xFD823800U, 0x00000000U);
+
+	/* RT bus Leaf setting */
+	io_write_32(0xF1300800U, 0x00000003U);
+	io_write_32(0xF1340800U, 0x00000003U);
+	io_write_32(0xFFC50800U, 0x00000000U);
+	io_write_32(0xFFC51800U, 0x00000000U);
+
+	/* Resource Alloc start */
+	io_write_32(RALLOC_RAEN,  0x00000001U);
+
+	/* MSTAT start */
+	io_write_32(MSTAT_STATQC, 0x00000001U);
+#else
+	NOTICE("BL2: QoS is None\n");
+
+	/* Resource Alloc setting */
+	io_write_32(RALLOC_EC,    0x00000000U);
+	/* Resource Alloc start */
+	io_write_32(RALLOC_RAEN,  0x00000001U);
+#endif /* !(RCAR_QOS_TYPE == RCAR_QOS_NONE) */
+	io_write_32(DBSC_DBSYSCNT0, 0x00000000);
+}
diff --git a/drivers/staging/renesas/rcar/qos/D3/qos_init_d3.h b/drivers/staging/renesas/rcar/qos/D3/qos_init_d3.h
new file mode 100644
index 000000000..968ee7a47
--- /dev/null
+++ b/drivers/staging/renesas/rcar/qos/D3/qos_init_d3.h
@@ -0,0 +1,13 @@
+/*
+ * Copyright (c) 2015-2017, Renesas Electronics Corporation
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef QOS_INIT_H_D3__
+#define QOS_INIT_H_D3__
+
+void qos_init_d3(void);
+
+#endif	/* QOS_INIT_H_D3__ */
diff --git a/drivers/staging/renesas/rcar/qos/qos.mk b/drivers/staging/renesas/rcar/qos/qos.mk
index 9fabc56f8..77b3c6179 100644
--- a/drivers/staging/renesas/rcar/qos/qos.mk
+++ b/drivers/staging/renesas/rcar/qos/qos.mk
@@ -35,6 +35,9 @@ else ifdef RCAR_LSI_CUT_COMPAT
   ifeq (${RCAR_LSI},${RCAR_E3})
     BL2_SOURCES += drivers/staging/renesas/rcar/qos/E3/qos_init_e3_v10.c
   endif
+  ifeq (${RCAR_LSI},${RCAR_D3})
+    BL2_SOURCES += drivers/staging/renesas/rcar/qos/D3/qos_init_d3.c
+  endif
 else
   ifeq (${RCAR_LSI},${RCAR_H3})
     ifeq (${LSI_CUT},10)
@@ -88,6 +91,9 @@ else
      BL2_SOURCES += drivers/staging/renesas/rcar/qos/E3/qos_init_e3_v10.c
     endif
   endif
+  ifeq (${RCAR_LSI},${RCAR_D3})
+    BL2_SOURCES += drivers/staging/renesas/rcar/qos/E3/qos_init_d3.c
+  endif
 endif
 
 BL2_SOURCES += drivers/staging/renesas/rcar/qos/qos_init.c
diff --git a/drivers/staging/renesas/rcar/qos/qos_init.c b/drivers/staging/renesas/rcar/qos/qos_init.c
index affd42502..895f43f5b 100644
--- a/drivers/staging/renesas/rcar/qos/qos_init.c
+++ b/drivers/staging/renesas/rcar/qos/qos_init.c
@@ -41,6 +41,9 @@
 #if RCAR_LSI == RCAR_E3		/* E3 */
 #include "E3/qos_init_e3_v10.h"
 #endif
+#if RCAR_LSI == RCAR_D3		/* D3 */
+#include "D3/qos_init_d3.h"
+#endif
 
  /* Product Register */
 #define PRR			(0xFFF00044U)
@@ -50,13 +53,14 @@
 #define PRR_PRODUCT_M3		(0x00005200U)	/* R-Car M3 */
 #define PRR_PRODUCT_M3N		(0x00005500U)	/* R-Car M3N */
 #define PRR_PRODUCT_E3		(0x00005700U)	/* R-Car E3 */
+#define PRR_PRODUCT_D3		(0x00005800U)	/* R-Car D3 */
 #define PRR_PRODUCT_10		(0x00U)
 #define PRR_PRODUCT_11		(0x01U)
 #define PRR_PRODUCT_20		(0x10U)
 #define PRR_PRODUCT_21		(0x11U)
 #define PRR_PRODUCT_30		(0x20U)
 
-#if !(RCAR_LSI == RCAR_E3)
+#if (RCAR_LSI != RCAR_E3) && (RCAR_LSI != RCAR_D3)
 
 #define DRAM_CH_CNT			0x04
 uint32_t qos_init_ddr_ch;
@@ -81,7 +85,7 @@ uint8_t qos_init_ddr_phyvalid;
 void rcar_qos_init(void)
 {
 	uint32_t reg;
-#if !(RCAR_LSI == RCAR_E3)
+#if (RCAR_LSI != RCAR_E3) && (RCAR_LSI != RCAR_D3)
 	uint32_t i;
 
 	qos_init_ddr_ch = 0;
@@ -166,6 +170,18 @@ void rcar_qos_init(void)
 		PRR_PRODUCT_ERR(reg);
 #endif
 		break;
+	case PRR_PRODUCT_D3:
+#if (RCAR_LSI == RCAR_D3)
+		switch (reg & PRR_CUT_MASK) {
+		case PRR_PRODUCT_10:
+		default:
+			qos_init_d3();
+			break;
+		}
+#else
+		PRR_PRODUCT_ERR(reg);
+#endif
+		break;
 	default:
 		PRR_PRODUCT_ERR(reg);
 		break;
@@ -245,6 +261,13 @@ void rcar_qos_init(void)
 		PRR_PRODUCT_ERR(reg);
 	}
 	qos_init_m3n_v10();
+#elif RCAR_LSI == RCAR_D3	/* D3 */
+	/* D3 Cut 10 or later */
+	if ((PRR_PRODUCT_D3)
+	    != (reg & (PRR_PRODUCT_MASK))) {
+		PRR_PRODUCT_ERR(reg);
+	}
+	qos_init_d3();
 #elif RCAR_LSI == RCAR_E3	/* E3 */
 	/* E3 Cut 10 or later */
 	if ((PRR_PRODUCT_E3)
@@ -258,7 +281,7 @@ void rcar_qos_init(void)
 #endif
 }
 
-#if !(RCAR_LSI == RCAR_E3)
+#if (RCAR_LSI != RCAR_E3) && (RCAR_LSI != RCAR_D3)
 uint32_t get_refperiod(void)
 {
 	uint32_t refperiod = QOSWT_WTSET0_CYCLE;