Merge '5f62213e684dbea03b5a2bb732405a03ccc1a815' into master am: 5dfd96a0b3 am: 780068d4ee am: 1d4a3be615android-mainline-11.0.0_r9android-mainline-11.0.0_r8android-mainline-11.0.0_r7android-mainline-11.0.0_r6android-mainline-11.0.0_r5android-mainline-11.0.0_r44android-mainline-11.0.0_r43android-mainline-11.0.0_r42android-mainline-11.0.0_r41android-mainline-11.0.0_r40android-mainline-11.0.0_r4android-mainline-11.0.0_r39android-mainline-11.0.0_r38android-mainline-11.0.0_r37android-mainline-11.0.0_r36android-mainline-11.0.0_r35android-mainline-11.0.0_r34android-mainline-11.0.0_r33android-mainline-11.0.0_r32android-mainline-11.0.0_r31android-mainline-11.0.0_r30android-mainline-11.0.0_r3android-mainline-11.0.0_r29android-mainline-11.0.0_r28android-mainline-11.0.0_r27android-mainline-11.0.0_r26android-mainline-11.0.0_r25android-mainline-11.0.0_r24android-mainline-11.0.0_r23android-mainline-11.0.0_r22android-mainline-11.0.0_r21android-mainline-11.0.0_r20android-mainline-11.0.0_r2android-mainline-11.0.0_r19android-mainline-11.0.0_r18android-mainline-11.0.0_r17android-mainline-11.0.0_r16android-mainline-11.0.0_r15android-mainline-11.0.0_r14android-mainline-11.0.0_r13android-mainline-11.0.0_r12android-mainline-11.0.0_r10android-mainline-11.0.0_r1android-11.0.0_r45android-11.0.0_r44android-11.0.0_r43android-11.0.0_r42android-11.0.0_r41android-11.0.0_r40android-11.0.0_r39android-11.0.0_r38android-11.0.0_r37android-11.0.0_r36android-11.0.0_r35android-11.0.0_r34android-11.0.0_r33android-11.0.0_r32android-11.0.0_r31android-11.0.0_r30android-11.0.0_r29android-11.0.0_r28android-11.0.0_r27android-11.0.0_r26android-11.0.0_r24android-11.0.0_r23android-11.0.0_r22android-11.0.0_r21android-11.0.0_r20android-11.0.0_r19android-11.0.0_r18android-11.0.0_r16android11-qpr3-s1-releaseandroid11-qpr3-releaseandroid11-qpr2-releaseandroid11-qpr1-s2-releaseandroid11-qpr1-s1-releaseandroid11-qpr1-releaseandroid11-qpr1-d-s1-releaseandroid11-qpr1-d-releaseandroid11-qpr1-c-releaseandroid11-mainline-tethering-releaseandroid11-mainline-sparse-2021-jan-releaseandroid11-mainline-sparse-2020-dec-releaseandroid11-mainline-releaseandroid11-mainline-permission-releaseandroid11-mainline-os-statsd-releaseandroid11-mainline-networkstack-releaseandroid11-mainline-media-swcodec-releaseandroid11-mainline-media-releaseandroid11-mainline-extservices-releaseandroid11-mainline-documentsui-releaseandroid11-mainline-conscrypt-releaseandroid11-mainline-cellbroadcast-releaseandroid11-mainline-captiveportallogin-releaseandroid11-devandroid11-d2-releaseandroid11-d1-b-release

Change-Id: Ia911040759d199f8c1ec0b51abd4fa556a6b8b40

105 files changed, 11436 insertions, 7167 deletions

diff --git a/drivers/allwinner/axp/axp803.c b/drivers/allwinner/axp/axp803.c
new file mode 100644
index 000000000..53b11c11a
--- /dev/null
+++ b/drivers/allwinner/axp/axp803.c
@@ -0,0 +1,22 @@
+/*
+ * Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <drivers/allwinner/axp.h>
+
+const uint8_t axp_chip_id = AXP803_CHIP_ID;
+const char *const axp_compatible = "x-powers,axp803";
+
+const struct axp_regulator axp_regulators[] = {
+	{"dcdc1", 1600, 3400, 100, NA, 0x20, 0x10, 0},
+	{"dcdc5",  800, 1840,  10, 32, 0x24, 0x10, 4},
+	{"dcdc6",  600, 1520,  10, 50, 0x25, 0x10, 5},
+	{"dldo1",  700, 3300, 100, NA, 0x15, 0x12, 3},
+	{"dldo2",  700, 4200, 100, 27, 0x16, 0x12, 4},
+	{"dldo3",  700, 3300, 100, NA, 0x17, 0x12, 5},
+	{"dldo4",  700, 3300, 100, NA, 0x18, 0x12, 6},
+	{"fldo1",  700, 1450,  50, NA, 0x1c, 0x13, 2},
+	{}
+};
diff --git a/drivers/allwinner/axp/axp805.c b/drivers/allwinner/axp/axp805.c
new file mode 100644
index 000000000..8d029c0bd
--- /dev/null
+++ b/drivers/allwinner/axp/axp805.c
@@ -0,0 +1,33 @@
+/*
+ * Copyright (c) 2019, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <drivers/allwinner/axp.h>
+
+const uint8_t axp_chip_id = AXP805_CHIP_ID;
+const char *const axp_compatible = "x-powers,axp805";
+
+/*
+ * The "dcdcd" split changes the step size by a factor of 5, not 2;
+ * disallow values above the split to maintain accuracy.
+ */
+const struct axp_regulator axp_regulators[] = {
+	{"dcdca",  600, 1520,  10, 50, 0x12, 0x10, 0},
+	{"dcdcb", 1000, 2550,  50, NA, 0x13, 0x10, 1},
+	{"dcdcc",  600, 1520,  10, 50, 0x14, 0x10, 2},
+	{"dcdcd",  600, 1500,  20, NA, 0x15, 0x10, 3},
+	{"dcdce", 1100, 3400, 100, NA, 0x16, 0x10, 4},
+	{"aldo1",  700, 3300, 100, NA, 0x17, 0x10, 5},
+	{"aldo2",  700, 3300, 100, NA, 0x18, 0x10, 6},
+	{"aldo3",  700, 3300, 100, NA, 0x19, 0x10, 7},
+	{"bldo1",  700, 1900, 100, NA, 0x20, 0x11, 0},
+	{"bldo2",  700, 1900, 100, NA, 0x21, 0x11, 1},
+	{"bldo3",  700, 1900, 100, NA, 0x22, 0x11, 2},
+	{"bldo4",  700, 1900, 100, NA, 0x23, 0x11, 3},
+	{"cldo1",  700, 3300, 100, NA, 0x24, 0x11, 4},
+	{"cldo2",  700, 4200, 100, 27, 0x25, 0x11, 5},
+	{"cldo3",  700, 3300, 100, NA, 0x26, 0x11, 6},
+	{}
+};
diff --git a/drivers/allwinner/axp/common.c b/drivers/allwinner/axp/common.c
new file mode 100644
index 000000000..13437fec8
--- /dev/null
+++ b/drivers/allwinner/axp/common.c
@@ -0,0 +1,175 @@
+/*
+ * Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <errno.h>
+
+#include <libfdt.h>
+
+#include <common/debug.h>
+#include <drivers/allwinner/axp.h>
+
+int axp_check_id(void)
+{
+	int ret;
+
+	ret = axp_read(0x03);
+	if (ret < 0)
+		return ret;
+
+	ret &= 0xcf;
+	if (ret != axp_chip_id) {
+		ERROR("PMIC: Found unknown PMIC %02x\n", ret);
+		return ret;
+	}
+
+	return 0;
+}
+
+int axp_clrsetbits(uint8_t reg, uint8_t clr_mask, uint8_t set_mask)
+{
+	uint8_t val;
+	int ret;
+
+	ret = axp_read(reg);
+	if (ret < 0)
+		return ret;
+
+	val = (ret & ~clr_mask) | set_mask;
+
+	return axp_write(reg, val);
+}
+
+void axp_power_off(void)
+{
+	/* Set "power disable control" bit */
+	axp_setbits(0x32, BIT(7));
+}
+
+/*
+ * Retrieve the voltage from a given regulator DTB node.
+ * Both the regulator-{min,max}-microvolt properties must be present and
+ * have the same value. Return that value in millivolts.
+ */
+static int fdt_get_regulator_millivolt(const void *fdt, int node)
+{
+	const fdt32_t *prop;
+	uint32_t min_volt;
+
+	prop = fdt_getprop(fdt, node, "regulator-min-microvolt", NULL);
+	if (prop == NULL)
+		return -EINVAL;
+	min_volt = fdt32_to_cpu(*prop);
+
+	prop = fdt_getprop(fdt, node, "regulator-max-microvolt", NULL);
+	if (prop == NULL)
+		return -EINVAL;
+
+	if (fdt32_to_cpu(*prop) != min_volt)
+		return -EINVAL;
+
+	return min_volt / 1000;
+}
+
+static int setup_regulator(const void *fdt, int node,
+			   const struct axp_regulator *reg)
+{
+	uint8_t val;
+	int mvolt;
+
+	mvolt = fdt_get_regulator_millivolt(fdt, node);
+	if (mvolt < reg->min_volt || mvolt > reg->max_volt)
+		return -EINVAL;
+
+	val = (mvolt / reg->step) - (reg->min_volt / reg->step);
+	if (val > reg->split)
+		val = ((val - reg->split) / 2) + reg->split;
+
+	axp_write(reg->volt_reg, val);
+	axp_setbits(reg->switch_reg, BIT(reg->switch_bit));
+
+	INFO("PMIC: %s voltage: %d.%03dV\n", reg->dt_name,
+	     mvolt / 1000, mvolt % 1000);
+
+	return 0;
+}
+
+static bool should_enable_regulator(const void *fdt, int node)
+{
+	if (fdt_getprop(fdt, node, "phandle", NULL) != NULL)
+		return true;
+	if (fdt_getprop(fdt, node, "regulator-always-on", NULL) != NULL)
+		return true;
+	return false;
+}
+
+void axp_setup_regulators(const void *fdt)
+{
+	int node;
+	bool sw = false;
+
+	if (fdt == NULL)
+		return;
+
+	/* locate the PMIC DT node, bail out if not found */
+	node = fdt_node_offset_by_compatible(fdt, -1, axp_compatible);
+	if (node < 0) {
+		WARN("PMIC: No PMIC DT node, skipping setup\n");
+		return;
+	}
+
+	/* This applies to AXP803 only. */
+	if (fdt_getprop(fdt, node, "x-powers,drive-vbus-en", NULL)) {
+		axp_clrbits(0x8f, BIT(4));
+		axp_setbits(0x30, BIT(2));
+		INFO("PMIC: Enabling DRIVEVBUS\n");
+	}
+
+	/* descend into the "regulators" subnode */
+	node = fdt_subnode_offset(fdt, node, "regulators");
+	if (node < 0) {
+		WARN("PMIC: No regulators DT node, skipping setup\n");
+		return;
+	}
+
+	/* iterate over all regulators to find used ones */
+	fdt_for_each_subnode(node, fdt, node) {
+		const struct axp_regulator *reg;
+		const char *name;
+		int length;
+
+		/* We only care if it's always on or referenced. */
+		if (!should_enable_regulator(fdt, node))
+			continue;
+
+		name = fdt_get_name(fdt, node, &length);
+
+		/* Enable the switch last to avoid overheating. */
+		if (!strncmp(name, "dc1sw", length) ||
+		    !strncmp(name, "sw", length)) {
+			sw = true;
+			continue;
+		}
+
+		for (reg = axp_regulators; reg->dt_name; reg++) {
+			if (!strncmp(name, reg->dt_name, length)) {
+				setup_regulator(fdt, node, reg);
+				break;
+			}
+		}
+	}
+
+	/*
+	 * On the AXP803, if DLDO2 is enabled after DC1SW, the PMIC overheats
+	 * and shuts down. So always enable DC1SW as the very last regulator.
+	 */
+	if (sw) {
+		INFO("PMIC: Enabling DC SW\n");
+		if (axp_chip_id == AXP803_CHIP_ID)
+			axp_setbits(0x12, BIT(7));
+		if (axp_chip_id == AXP805_CHIP_ID)
+			axp_setbits(0x11, BIT(7));
+	}
+}
diff --git a/drivers/meson/console/aarch64/meson_console.S b/drivers/amlogic/console/aarch64/meson_console.S
index 22d077332..e645cbab8 100644
--- a/drivers/meson/console/aarch64/meson_console.S
+++ b/drivers/amlogic/console/aarch64/meson_console.S
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -7,7 +7,7 @@
 #include <asm_macros.S>
 #include <assert_macros.S>
 #include <console_macros.S>
-#include <drivers/meson/meson_console.h>
+#include <drivers/amlogic/meson_console.h>
 
 	.globl console_meson_register
 	.globl console_meson_init
diff --git a/drivers/meson/gxl/crypto/sha_dma.c b/drivers/amlogic/crypto/sha_dma.c
index a969dea74..fceb1c0d3 100644
--- a/drivers/meson/gxl/crypto/sha_dma.c
+++ b/drivers/amlogic/crypto/sha_dma.c
@@ -4,15 +4,12 @@
  * SPDX-License-Identifier: BSD-3-Clause
  */
 
-#include <assert.h>
 #include <arch_helpers.h>
-#include <lib/mmio.h>
+#include <assert.h>
 #include <crypto/sha_dma.h>
+#include <lib/mmio.h>
 
-#define AML_SHA_DMA_BASE 0xc883e000
-
-#define AML_SHA_DMA_DESC (AML_SHA_DMA_BASE + 0x08)
-#define AML_SHA_DMA_STATUS (AML_SHA_DMA_BASE + 0x18)
+#include "aml_private.h"
 
 #define ASD_MODE_SHA224 0x7
 #define ASD_MODE_SHA256 0x6
diff --git a/drivers/arm/css/scp/css_pm_scmi.c b/drivers/arm/css/scp/css_pm_scmi.c
index 8dbefa16b..b945cda78 100644
--- a/drivers/arm/css/scp/css_pm_scmi.c
+++ b/drivers/arm/css/scp/css_pm_scmi.c
@@ -186,7 +186,7 @@ void css_scp_off(const struct psci_power_state *target_state)
 void css_scp_on(u_register_t mpidr)
 {
 	unsigned int lvl = 0;
-	int ret, core_pos;
+	int core_pos, ret;
 	uint32_t scmi_pwr_state = 0;
 
 	for (; lvl <= PLAT_MAX_PWR_LVL; lvl++)
@@ -196,7 +196,8 @@ void css_scp_on(u_register_t mpidr)
 	SCMI_SET_PWR_STATE_MAX_PWR_LVL(scmi_pwr_state, lvl - 1);
 
 	core_pos = plat_core_pos_by_mpidr(mpidr);
-	assert(core_pos >= 0 && core_pos < PLATFORM_CORE_COUNT);
+	assert((core_pos >= 0) &&
+		(((unsigned int)core_pos) < PLATFORM_CORE_COUNT));
 
 	ret = scmi_pwr_state_set(scmi_handle,
 		plat_css_core_pos_to_scmi_dmn_id_map[core_pos],
diff --git a/drivers/arm/gic/v3/gic600.c b/drivers/arm/gic/v3/gic600.c
index 9cb2ab25e..59652da63 100644
--- a/drivers/arm/gic/v3/gic600.c
+++ b/drivers/arm/gic/v3/gic600.c
@@ -1,14 +1,14 @@
 /*
- * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
 
 /*
- * Driver for GIC600-specific features. This driver only overrides APIs that are
- * different to those generic ones in GICv3 driver.
+ * Driver for GIC-600 specific features. This driver only overrides
+ * APIs that are different to those generic ones in GICv3 driver.
  *
- * GIC600 supports independently power-gating redistributor interface.
+ * GIC-600 supports independently power-gating redistributor interface.
  */
 
 #include <assert.h>
@@ -18,22 +18,28 @@
 
 #include "gicv3_private.h"
 
-/* GIC600-specific register offsets */
+/* GIC-600 specific register offsets */
 #define GICR_PWRR	0x24
 
 /* GICR_PWRR fields */
 #define PWRR_RDPD_SHIFT		0
+#define PWRR_RDAG_SHIFT		1
 #define PWRR_RDGPD_SHIFT	2
 #define PWRR_RDGPO_SHIFT	3
 
+#define PWRR_RDPD	(1 << PWRR_RDPD_SHIFT)
+#define PWRR_RDAG	(1 << PWRR_RDAG_SHIFT)
 #define PWRR_RDGPD	(1 << PWRR_RDGPD_SHIFT)
 #define PWRR_RDGPO	(1 << PWRR_RDGPO_SHIFT)
 
-/* Values to write to GICR_PWRR register to power redistributor */
+/*
+ * Values to write to GICR_PWRR register to power redistributor
+ * for operating through the core (GICR_PWRR.RDAG = 0)
+ */
 #define PWRR_ON		(0 << PWRR_RDPD_SHIFT)
 #define PWRR_OFF	(1 << PWRR_RDPD_SHIFT)
 
-/* GIC600-specific accessor functions */
+/* GIC-600 specific accessor functions */
 static void gicr_write_pwrr(uintptr_t base, unsigned int val)
 {
 	mmio_write_32(base + GICR_PWRR, val);
@@ -44,39 +50,46 @@ static uint32_t gicr_read_pwrr(uintptr_t base)
 	return mmio_read_32(base + GICR_PWRR);
 }
 
-static int gicr_group_powering_down(uint32_t pwrr)
+static void gicr_wait_group_not_in_transit(uintptr_t base)
 {
-	/*
-	 * Whether the redistributor group power down operation is in transit:
-	 * i.e. it's intending to, but not finished yet.
-	 */
-	return ((pwrr & PWRR_RDGPD) && !(pwrr & PWRR_RDGPO));
+	/* Check group not transitioning: RDGPD == RDGPO */
+	while (((gicr_read_pwrr(base) & PWRR_RDGPD) >> PWRR_RDGPD_SHIFT) !=
+		((gicr_read_pwrr(base) & PWRR_RDGPO) >> PWRR_RDGPO_SHIFT))
+		;
 }
 
 static void gic600_pwr_on(uintptr_t base)
 {
-	/* Power on redistributor */
-	gicr_write_pwrr(base, PWRR_ON);
+	do {	/* Wait until group not transitioning */
+		gicr_wait_group_not_in_transit(base);
 
-	/* Wait until the power on state is reflected */
-	while (gicr_read_pwrr(base) & PWRR_RDGPO)
-		;
+		/* Power on redistributor */
+		gicr_write_pwrr(base, PWRR_ON);
+
+		/*
+		 * Wait until the power on state is reflected.
+		 * If RDPD == 0 then powered on.
+		 */
+	} while ((gicr_read_pwrr(base) & PWRR_RDPD) != PWRR_ON);
 }
 
 static void gic600_pwr_off(uintptr_t base)
 {
+	/* Wait until group not transitioning */
+	gicr_wait_group_not_in_transit(base);
+
 	/* Power off redistributor */
 	gicr_write_pwrr(base, PWRR_OFF);
 
 	/*
 	 * If this is the last man, turning this redistributor frame off will
-	 * result in the group itself being powered off. In that case, wait as
-	 * long as it's in transition, or has aborted the transition altogether
-	 * for any reason.
+	 * result in the group itself being powered off and RDGPD = 1.
+	 * In that case, wait as long as it's in transition, or has aborted
+	 * the transition altogether for any reason.
 	 */
-	if (gicr_read_pwrr(base) & PWRR_RDGPD) {
-		while (gicr_group_powering_down(gicr_read_pwrr(base)))
-			;
+	if ((gicr_read_pwrr(base) & PWRR_RDGPD) != 0) {
+		/* Wait until group not transitioning */
+		gicr_wait_group_not_in_transit(base);
 	}
 }
 
@@ -91,7 +104,7 @@ void gicv3_distif_post_restore(unsigned int proc_num)
 }
 
 /*
- * Power off GIC600 redistributor
+ * Power off GIC-600 redistributor
  */
 void gicv3_rdistif_off(unsigned int proc_num)
 {
@@ -109,7 +122,7 @@ void gicv3_rdistif_off(unsigned int proc_num)
 }
 
 /*
- * Power on GIC600 redistributor
+ * Power on GIC-600 redistributor
  */
 void gicv3_rdistif_on(unsigned int proc_num)
 {
diff --git a/drivers/arm/gic/v3/gic600_multichip.c b/drivers/arm/gic/v3/gic600_multichip.c
new file mode 100644
index 000000000..ca7c43bf9
--- /dev/null
+++ b/drivers/arm/gic/v3/gic600_multichip.c
@@ -0,0 +1,240 @@
+/*
+ * Copyright (c) 2019, Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+/*
+ * GIC-600 driver extension for multichip setup
+ */
+
+#include <assert.h>
+
+#include <common/debug.h>
+#include <drivers/arm/gic600_multichip.h>
+#include <drivers/arm/gicv3.h>
+
+#include "../common/gic_common_private.h"
+#include "gic600_multichip_private.h"
+
+#warning "GIC-600 Multichip driver is currently experimental and the API may change in future."
+
+/*******************************************************************************
+ * GIC-600 multichip operation related helper functions
+ ******************************************************************************/
+static void gicd_dchipr_wait_for_power_update_progress(uintptr_t base)
+{
+	unsigned int retry = GICD_PUP_UPDATE_RETRIES;
+
+	while ((read_gicd_dchipr(base) & GICD_DCHIPR_PUP_BIT) != 0U) {
+		if (retry-- == 0) {
+			ERROR("GIC-600 connection to Routing Table Owner timed "
+					 "out\n");
+			panic();
+		}
+	}
+}
+
+/*******************************************************************************
+ * Sets up the routing table owner.
+ ******************************************************************************/
+static void set_gicd_dchipr_rt_owner(uintptr_t base, unsigned int rt_owner)
+{
+	/*
+	 * Ensure that Group enables in GICD_CTLR are disabled and no pending
+	 * register writes to GICD_CTLR.
+	 */
+	if ((gicd_read_ctlr(base) &
+			(CTLR_ENABLE_G0_BIT | CTLR_ENABLE_G1S_BIT |
+			 CTLR_ENABLE_G1NS_BIT | GICD_CTLR_RWP_BIT)) != 0) {
+		ERROR("GICD_CTLR group interrupts are either enabled or have "
+				"pending writes. Cannot set RT owner.\n");
+		panic();
+	}
+
+	/* Poll till PUP is zero before intiating write */
+	gicd_dchipr_wait_for_power_update_progress(base);
+
+	write_gicd_dchipr(base, read_gicd_dchipr(base) |
+			(rt_owner << GICD_DCHIPR_RT_OWNER_SHIFT));
+
+	/* Poll till PUP is zero to ensure write is complete */
+	gicd_dchipr_wait_for_power_update_progress(base);
+}
+
+/*******************************************************************************
+ * Configures the Chip Register to make connections to GICDs on
+ * a multichip platform.
+ ******************************************************************************/
+static void set_gicd_chipr_n(uintptr_t base,
+				unsigned int chip_id,
+				uint64_t chip_addr,
+				unsigned int spi_id_min,
+				unsigned int spi_id_max)
+{
+	unsigned int spi_block_min, spi_blocks;
+	uint64_t chipr_n_val;
+
+	/*
+	 * Ensure that group enables in GICD_CTLR are disabled and no pending
+	 * register writes to GICD_CTLR.
+	 */
+	if ((gicd_read_ctlr(base) &
+			(CTLR_ENABLE_G0_BIT | CTLR_ENABLE_G1S_BIT |
+			 CTLR_ENABLE_G1NS_BIT | GICD_CTLR_RWP_BIT)) != 0) {
+		ERROR("GICD_CTLR group interrupts are either enabled or have "
+				"pending writes. Cannot set CHIPR register.\n");
+		panic();
+	}
+
+	/*
+	 * spi_id_min and spi_id_max of value 0 is used to intidicate that the
+	 * chip doesn't own any SPI block. Re-assign min and max values as SPI
+	 * id starts from 32.
+	 */
+	if (spi_id_min == 0 && spi_id_max == 0) {
+		spi_id_min = GIC600_SPI_ID_MIN;
+		spi_id_max = GIC600_SPI_ID_MIN;
+	}
+
+	spi_block_min = SPI_BLOCK_MIN_VALUE(spi_id_min);
+	spi_blocks    = SPI_BLOCKS_VALUE(spi_id_min, spi_id_max);
+
+	chipr_n_val = (GICD_CHIPR_VALUE(chip_addr, spi_block_min, spi_blocks)) |
+		GICD_CHIPRx_SOCKET_STATE;
+
+	/*
+	 * Wait for DCHIPR.PUP to be zero before commencing writes to
+	 * GICD_CHIPRx.
+	 */
+	gicd_dchipr_wait_for_power_update_progress(base);
+
+	/*
+	 * Assign chip addr, spi min block, number of spi blocks and bring chip
+	 * online by setting SocketState.
+	 */
+	write_gicd_chipr_n(base, chip_id, chipr_n_val);
+
+	/*
+	 * Poll until DCHIP.PUP is zero to verify connection to rt_owner chip
+	 * is complete.
+	 */
+	gicd_dchipr_wait_for_power_update_progress(base);
+
+	/*
+	 * Ensure that write to GICD_CHIPRx is successful and the chip_n came
+	 * online.
+	 */
+	if (read_gicd_chipr_n(base, chip_id) != chipr_n_val) {
+		ERROR("GICD_CHIPR%u write failed\n", chip_id);
+		panic();
+	}
+
+	/* Ensure that chip is in consistent state */
+	if (((read_gicd_chipsr(base) & GICD_CHIPSR_RTS_MASK) >>
+				GICD_CHIPSR_RTS_SHIFT) !=
+			GICD_CHIPSR_RTS_STATE_CONSISTENT) {
+		ERROR("Chip %u routing table is not in consistent state\n",
+				chip_id);
+		panic();
+	}
+}
+
+/*******************************************************************************
+ * Validates the GIC-600 Multichip data structure passed by the platform.
+ ******************************************************************************/
+static void gic600_multichip_validate_data(
+		struct gic600_multichip_data *multichip_data)
+{
+	unsigned int i, spi_id_min, spi_id_max, blocks_of_32;
+	unsigned int multichip_spi_blocks = 0;
+
+	assert(multichip_data != NULL);
+
+	if (multichip_data->chip_count > GIC600_MAX_MULTICHIP) {
+		ERROR("GIC-600 Multichip count should not exceed %d\n",
+				GIC600_MAX_MULTICHIP);
+		panic();
+	}
+
+	for (i = 0; i < multichip_data->chip_count; i++) {
+		spi_id_min = multichip_data->spi_ids[i][SPI_MIN_INDEX];
+		spi_id_max = multichip_data->spi_ids[i][SPI_MAX_INDEX];
+
+		if ((spi_id_min != 0) || (spi_id_max != 0)) {
+
+			/* SPI IDs range check */
+			if (!(spi_id_min >= GIC600_SPI_ID_MIN) ||
+			    !(spi_id_max < GIC600_SPI_ID_MAX) ||
+			    !(spi_id_min <= spi_id_max) ||
+			    !((spi_id_max - spi_id_min + 1) % 32 == 0)) {
+				ERROR("Invalid SPI IDs {%u, %u} passed for "
+						"Chip %u\n", spi_id_min,
+						spi_id_max, i);
+				panic();
+			}
+
+			/* SPI IDs overlap check */
+			blocks_of_32 = BLOCKS_OF_32(spi_id_min, spi_id_max);
+			if ((multichip_spi_blocks & blocks_of_32) != 0) {
+				ERROR("SPI IDs of Chip %u overlapping\n", i);
+				panic();
+			}
+			multichip_spi_blocks |= blocks_of_32;
+		}
+	}
+}
+
+/*******************************************************************************
+ * Intialize GIC-600 Multichip operation.
+ ******************************************************************************/
+void gic600_multichip_init(struct gic600_multichip_data *multichip_data)
+{
+	unsigned int i;
+
+	gic600_multichip_validate_data(multichip_data);
+
+	INFO("GIC-600 Multichip driver is experimental\n");
+
+	/*
+	 * Ensure that G0/G1S/G1NS interrupts are disabled. This also ensures
+	 * that GIC-600 Multichip configuration is done first.
+	 */
+	if ((gicd_read_ctlr(multichip_data->rt_owner_base) &
+			(CTLR_ENABLE_G0_BIT | CTLR_ENABLE_G1S_BIT |
+			 CTLR_ENABLE_G1NS_BIT | GICD_CTLR_RWP_BIT)) != 0) {
+		ERROR("GICD_CTLR group interrupts are either enabled or have "
+				"pending writes.\n");
+		panic();
+	}
+
+	/* Ensure that the routing table owner is in disconnected state */
+	if (((read_gicd_chipsr(multichip_data->rt_owner_base) &
+		GICD_CHIPSR_RTS_MASK) >> GICD_CHIPSR_RTS_SHIFT) !=
+			GICD_CHIPSR_RTS_STATE_DISCONNECTED) {
+		ERROR("GIC-600 routing table owner is not in disconnected "
+				"state to begin multichip configuration\n");
+		panic();
+	}
+
+	/* Initialize the GICD which is marked as routing table owner first */
+	set_gicd_dchipr_rt_owner(multichip_data->rt_owner_base,
+			multichip_data->rt_owner);
+
+	set_gicd_chipr_n(multichip_data->rt_owner_base, multichip_data->rt_owner,
+			multichip_data->chip_addrs[multichip_data->rt_owner],
+			multichip_data->
+			spi_ids[multichip_data->rt_owner][SPI_MIN_INDEX],
+			multichip_data->
+			spi_ids[multichip_data->rt_owner][SPI_MAX_INDEX]);
+
+	for (i = 0; i < multichip_data->chip_count; i++) {
+		if (i == multichip_data->rt_owner)
+			continue;
+
+		set_gicd_chipr_n(multichip_data->rt_owner_base, i,
+				multichip_data->chip_addrs[i],
+				multichip_data->spi_ids[i][SPI_MIN_INDEX],
+				multichip_data->spi_ids[i][SPI_MAX_INDEX]);
+	}
+}
diff --git a/drivers/arm/gic/v3/gic600_multichip_private.h b/drivers/arm/gic/v3/gic600_multichip_private.h
new file mode 100644
index 000000000..b0217b6d4
--- /dev/null
+++ b/drivers/arm/gic/v3/gic600_multichip_private.h
@@ -0,0 +1,97 @@
+/*
+ * Copyright (c) 2019, ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef GIC600_MULTICHIP_PRIVATE_H
+#define GIC600_MULTICHIP_PRIVATE_H
+
+#include <drivers/arm/gic600_multichip.h>
+
+#include "gicv3_private.h"
+
+/* GIC600 GICD multichip related offsets */
+#define GICD_CHIPSR			U(0xC000)
+#define GICD_DCHIPR			U(0xC004)
+#define GICD_CHIPR			U(0xC008)
+
+/* GIC600 GICD multichip related masks */
+#define GICD_CHIPRx_PUP_BIT		BIT_64(1)
+#define GICD_CHIPRx_SOCKET_STATE	BIT_64(0)
+#define GICD_DCHIPR_PUP_BIT		BIT_32(0)
+#define GICD_CHIPSR_RTS_MASK		(BIT_32(4) | BIT_32(5))
+
+/* GIC600 GICD multichip related shifts */
+#define GICD_CHIPRx_ADDR_SHIFT		16
+#define GICD_CHIPRx_SPI_BLOCK_MIN_SHIFT	10
+#define GICD_CHIPRx_SPI_BLOCKS_SHIFT	5
+#define GICD_CHIPSR_RTS_SHIFT		4
+#define GICD_DCHIPR_RT_OWNER_SHIFT	4
+
+#define GICD_CHIPSR_RTS_STATE_DISCONNECTED	U(0)
+#define GICD_CHIPSR_RTS_STATE_UPDATING		U(1)
+#define GICD_CHIPSR_RTS_STATE_CONSISTENT	U(2)
+
+/* SPI interrupt id minimum and maximum range */
+#define GIC600_SPI_ID_MIN		32
+#define GIC600_SPI_ID_MAX		960
+
+/* Number of retries for PUP update */
+#define GICD_PUP_UPDATE_RETRIES		10000
+
+#define SPI_MIN_INDEX			0
+#define SPI_MAX_INDEX			1
+
+#define SPI_BLOCK_MIN_VALUE(spi_id_min) \
+			(((spi_id_min) - GIC600_SPI_ID_MIN) / \
+			GIC600_SPI_ID_MIN)
+#define SPI_BLOCKS_VALUE(spi_id_min, spi_id_max) \
+			(((spi_id_max) - (spi_id_min) + 1) / \
+			GIC600_SPI_ID_MIN)
+#define GICD_CHIPR_VALUE(chip_addr, spi_block_min, spi_blocks) \
+			(((chip_addr) << GICD_CHIPRx_ADDR_SHIFT) | \
+			((spi_block_min) << GICD_CHIPRx_SPI_BLOCK_MIN_SHIFT) | \
+			((spi_blocks) << GICD_CHIPRx_SPI_BLOCKS_SHIFT))
+
+/*
+ * Multichip data assertion macros
+ */
+/* Set bits from 0 to ((spi_id_max + 1) / 32) */
+#define SPI_BLOCKS_TILL_MAX(spi_id_max)	((1 << (((spi_id_max) + 1) >> 5)) - 1)
+/* Set bits from 0 to (spi_id_min / 32) */
+#define SPI_BLOCKS_TILL_MIN(spi_id_min)	((1 << ((spi_id_min) >> 5)) - 1)
+/* Set bits from (spi_id_min / 32) to ((spi_id_max + 1) / 32) */
+#define BLOCKS_OF_32(spi_id_min, spi_id_max) \
+					SPI_BLOCKS_TILL_MAX(spi_id_max) ^ \
+					SPI_BLOCKS_TILL_MIN(spi_id_min)
+
+/*******************************************************************************
+ * GIC-600 multichip operation related helper functions
+ ******************************************************************************/
+static inline uint32_t read_gicd_dchipr(uintptr_t base)
+{
+	return mmio_read_32(base + GICD_DCHIPR);
+}
+
+static inline uint64_t read_gicd_chipr_n(uintptr_t base, uint8_t n)
+{
+	return mmio_read_64(base + (GICD_CHIPR + (8U * n)));
+}
+
+static inline uint32_t read_gicd_chipsr(uintptr_t base)
+{
+	return mmio_read_32(base + GICD_CHIPSR);
+}
+
+static inline void write_gicd_dchipr(uintptr_t base, uint32_t val)
+{
+	mmio_write_32(base + GICD_DCHIPR, val);
+}
+
+static inline void write_gicd_chipr_n(uintptr_t base, uint8_t n, uint64_t val)
+{
+	mmio_write_64(base + (GICD_CHIPR + (8U * n)), val);
+}
+
+#endif /* GIC600_MULTICHIP_PRIVATE_H */
diff --git a/drivers/arm/gic/v3/gicv3_main.c b/drivers/arm/gic/v3/gicv3_main.c
index 94a20ba07..a672b18f3 100644
--- a/drivers/arm/gic/v3/gicv3_main.c
+++ b/drivers/arm/gic/v3/gicv3_main.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2015-2020, ARM Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -16,7 +16,6 @@
 #include "gicv3_private.h"
 
 const gicv3_driver_data_t *gicv3_driver_data;
-static unsigned int gicv2_compat;
 
 /*
  * Spinlock to guard registers needing read-modify-write. APIs protected by this
@@ -60,51 +59,61 @@ static spinlock_t gic_lock;
 void __init gicv3_driver_init(const gicv3_driver_data_t *plat_driver_data)
 {
 	unsigned int gic_version;
+	unsigned int gicv2_compat;
 
 	assert(plat_driver_data != NULL);
 	assert(plat_driver_data->gicd_base != 0U);
-	assert(plat_driver_data->gicr_base != 0U);
 	assert(plat_driver_data->rdistif_num != 0U);
 	assert(plat_driver_data->rdistif_base_addrs != NULL);
 
 	assert(IS_IN_EL3());
 
-	assert(plat_driver_data->interrupt_props_num > 0 ?
-	       plat_driver_data->interrupt_props != NULL : 1);
+	assert((plat_driver_data->interrupt_props_num != 0U) ?
+	       (plat_driver_data->interrupt_props != NULL) : 1);
 
 	/* Check for system register support */
-#ifdef __aarch64__
+#ifndef __aarch64__
+	assert((read_id_pfr1() &
+			(ID_PFR1_GIC_MASK << ID_PFR1_GIC_SHIFT)) != 0U);
+#else
 	assert((read_id_aa64pfr0_el1() &
 			(ID_AA64PFR0_GIC_MASK << ID_AA64PFR0_GIC_SHIFT)) != 0U);
-#else
-	assert((read_id_pfr1() & (ID_PFR1_GIC_MASK << ID_PFR1_GIC_SHIFT)) != 0U);
-#endif /* __aarch64__ */
+#endif /* !__aarch64__ */
 
 	/* The GIC version should be 3.0 */
 	gic_version = gicd_read_pidr2(plat_driver_data->gicd_base);
-	gic_version >>=	PIDR2_ARCH_REV_SHIFT;
+	gic_version >>= PIDR2_ARCH_REV_SHIFT;
 	gic_version &= PIDR2_ARCH_REV_MASK;
 	assert(gic_version == ARCH_REV_GICV3);
 
 	/*
-	 * Find out whether the GIC supports the GICv2 compatibility mode. The
-	 * ARE_S bit resets to 0 if supported
+	 * Find out whether the GIC supports the GICv2 compatibility mode.
+	 * The ARE_S bit resets to 0 if supported
 	 */
 	gicv2_compat = gicd_read_ctlr(plat_driver_data->gicd_base);
 	gicv2_compat >>= CTLR_ARE_S_SHIFT;
-	gicv2_compat = !(gicv2_compat & CTLR_ARE_S_MASK);
-
-	/*
-	 * Find the base address of each implemented Redistributor interface.
-	 * The number of interfaces should be equal to the number of CPUs in the
-	 * system. The memory for saving these addresses has to be allocated by
-	 * the platform port
-	 */
-	gicv3_rdistif_base_addrs_probe(plat_driver_data->rdistif_base_addrs,
-					   plat_driver_data->rdistif_num,
-					   plat_driver_data->gicr_base,
-					   plat_driver_data->mpidr_to_core_pos);
-
+	gicv2_compat = gicv2_compat & CTLR_ARE_S_MASK;
+
+	if (plat_driver_data->gicr_base != 0U) {
+		/*
+		 * Find the base address of each implemented Redistributor interface.
+		 * The number of interfaces should be equal to the number of CPUs in the
+		 * system. The memory for saving these addresses has to be allocated by
+		 * the platform port
+		 */
+		gicv3_rdistif_base_addrs_probe(plat_driver_data->rdistif_base_addrs,
+						   plat_driver_data->rdistif_num,
+						   plat_driver_data->gicr_base,
+						   plat_driver_data->mpidr_to_core_pos);
+#if !HW_ASSISTED_COHERENCY
+		/*
+		 * Flush the rdistif_base_addrs[] contents linked to the GICv3 driver.
+		 */
+		flush_dcache_range((uintptr_t)(plat_driver_data->rdistif_base_addrs),
+			plat_driver_data->rdistif_num *
+			sizeof(*(plat_driver_data->rdistif_base_addrs)));
+#endif
+	}
 	gicv3_driver_data = plat_driver_data;
 
 	/*
@@ -112,19 +121,19 @@ void __init gicv3_driver_init(const gicv3_driver_data_t *plat_driver_data)
 	 * enabled. When the secondary CPU boots up, it initializes the
 	 * GICC/GICR interface with the caches disabled. Hence flush the
 	 * driver data to ensure coherency. This is not required if the
-	 * platform has HW_ASSISTED_COHERENCY or WARMBOOT_ENABLE_DCACHE_EARLY
-	 * enabled.
+	 * platform has HW_ASSISTED_COHERENCY enabled.
 	 */
-#if !(HW_ASSISTED_COHERENCY || WARMBOOT_ENABLE_DCACHE_EARLY)
-	flush_dcache_range((uintptr_t) &gicv3_driver_data,
-			sizeof(gicv3_driver_data));
-	flush_dcache_range((uintptr_t) gicv3_driver_data,
-			sizeof(*gicv3_driver_data));
+#if !HW_ASSISTED_COHERENCY
+	flush_dcache_range((uintptr_t)&gicv3_driver_data,
+		sizeof(gicv3_driver_data));
+	flush_dcache_range((uintptr_t)gicv3_driver_data,
+		sizeof(*gicv3_driver_data));
 #endif
 
-	INFO("GICv3 %s legacy support detected."
-			" ARM GICV3 driver initialized in EL3\n",
-			gicv2_compat ? "with" : "without");
+	INFO("GICv3 with%s legacy support detected."
+			" ARM GICv3 driver initialized in EL3\n",
+			(gicv2_compat == 0U) ? "" : "out");
+
 }
 
 /*******************************************************************************
@@ -192,6 +201,7 @@ void gicv3_rdistif_init(unsigned int proc_num)
 	gicv3_rdistif_on(proc_num);
 
 	gicr_base = gicv3_driver_data->rdistif_base_addrs[proc_num];
+	assert(gicr_base != 0U);
 
 	/* Set the default attribute of all SGIs and PPIs */
 	gicv3_ppi_sgi_config_defaults(gicr_base);
@@ -225,7 +235,7 @@ void gicv3_rdistif_on(unsigned int proc_num)
 void gicv3_cpuif_enable(unsigned int proc_num)
 {
 	uintptr_t gicr_base;
-	unsigned int scr_el3;
+	u_register_t scr_el3;
 	unsigned int icc_sre_el3;
 
 	assert(gicv3_driver_data != NULL);
@@ -248,7 +258,7 @@ void gicv3_cpuif_enable(unsigned int proc_num)
 	icc_sre_el3 |= (ICC_SRE_EN_BIT | ICC_SRE_SRE_BIT);
 	write_icc_sre_el3(read_icc_sre_el3() | icc_sre_el3);
 
-	scr_el3 = (uint32_t) read_scr_el3();
+	scr_el3 = read_scr_el3();
 
 	/*
 	 * Switch to NS state to write Non secure ICC_SRE_EL1 and
@@ -313,6 +323,7 @@ void gicv3_cpuif_disable(unsigned int proc_num)
 
 	/* Mark the connected core as asleep */
 	gicr_base = gicv3_driver_data->rdistif_base_addrs[proc_num];
+	assert(gicr_base != 0U);
 	gicv3_rdistif_mark_core_asleep(gicr_base);
 }
 
@@ -629,7 +640,9 @@ void gicv3_distif_save(gicv3_dist_ctx_t * const dist_ctx)
 	num_ints &= TYPER_IT_LINES_NO_MASK;
 	num_ints = (num_ints + 1U) << 5;
 
-	assert(num_ints <= (MAX_SPI_ID + 1U));
+	/* Filter out special INTIDs 1020-1023 */
+	if (num_ints > (MAX_SPI_ID + 1U))
+		num_ints = MAX_SPI_ID + 1U;
 
 	/* Wait for pending write to complete */
 	gicd_wait_for_pending_write(gicd_base);
@@ -637,31 +650,31 @@ void gicv3_distif_save(gicv3_dist_ctx_t * const dist_ctx)
 	/* Save the GICD_CTLR */
 	dist_ctx->gicd_ctlr = gicd_read_ctlr(gicd_base);
 
-	/* Save GICD_IGROUPR for INTIDs 32 - 1020 */
+	/* Save GICD_IGROUPR for INTIDs 32 - 1019 */
 	SAVE_GICD_REGS(gicd_base, dist_ctx, num_ints, igroupr, IGROUPR);
 
-	/* Save GICD_ISENABLER for INT_IDs 32 - 1020 */
+	/* Save GICD_ISENABLER for INT_IDs 32 - 1019 */
 	SAVE_GICD_REGS(gicd_base, dist_ctx, num_ints, isenabler, ISENABLER);
 
-	/* Save GICD_ISPENDR for INTIDs 32 - 1020 */
+	/* Save GICD_ISPENDR for INTIDs 32 - 1019 */
 	SAVE_GICD_REGS(gicd_base, dist_ctx, num_ints, ispendr, ISPENDR);
 
-	/* Save GICD_ISACTIVER for INTIDs 32 - 1020 */
+	/* Save GICD_ISACTIVER for INTIDs 32 - 1019 */
 	SAVE_GICD_REGS(gicd_base, dist_ctx, num_ints, isactiver, ISACTIVER);
 
-	/* Save GICD_IPRIORITYR for INTIDs 32 - 1020 */
+	/* Save GICD_IPRIORITYR for INTIDs 32 - 1019 */
 	SAVE_GICD_REGS(gicd_base, dist_ctx, num_ints, ipriorityr, IPRIORITYR);
 
-	/* Save GICD_ICFGR for INTIDs 32 - 1020 */
+	/* Save GICD_ICFGR for INTIDs 32 - 1019 */
 	SAVE_GICD_REGS(gicd_base, dist_ctx, num_ints, icfgr, ICFGR);
 
-	/* Save GICD_IGRPMODR for INTIDs 32 - 1020 */
+	/* Save GICD_IGRPMODR for INTIDs 32 - 1019 */
 	SAVE_GICD_REGS(gicd_base, dist_ctx, num_ints, igrpmodr, IGRPMODR);
 
-	/* Save GICD_NSACR for INTIDs 32 - 1020 */
+	/* Save GICD_NSACR for INTIDs 32 - 1019 */
 	SAVE_GICD_REGS(gicd_base, dist_ctx, num_ints, nsacr, NSACR);
 
-	/* Save GICD_IROUTER for INTIDs 32 - 1024 */
+	/* Save GICD_IROUTER for INTIDs 32 - 1019 */
 	SAVE_GICD_REGS(gicd_base, dist_ctx, num_ints, irouter, IROUTER);
 
 	/*
@@ -707,24 +720,26 @@ void gicv3_distif_init_restore(const gicv3_dist_ctx_t * const dist_ctx)
 	num_ints &= TYPER_IT_LINES_NO_MASK;
 	num_ints = (num_ints + 1U) << 5;
 
-	assert(num_ints <= (MAX_SPI_ID + 1U));
+	/* Filter out special INTIDs 1020-1023 */
+	if (num_ints > (MAX_SPI_ID + 1U))
+		num_ints = MAX_SPI_ID + 1U;
 
-	/* Restore GICD_IGROUPR for INTIDs 32 - 1020 */
+	/* Restore GICD_IGROUPR for INTIDs 32 - 1019 */
 	RESTORE_GICD_REGS(gicd_base, dist_ctx, num_ints, igroupr, IGROUPR);
 
-	/* Restore GICD_IPRIORITYR for INTIDs 32 - 1020 */
+	/* Restore GICD_IPRIORITYR for INTIDs 32 - 1019 */
 	RESTORE_GICD_REGS(gicd_base, dist_ctx, num_ints, ipriorityr, IPRIORITYR);
 
-	/* Restore GICD_ICFGR for INTIDs 32 - 1020 */
+	/* Restore GICD_ICFGR for INTIDs 32 - 1019 */
 	RESTORE_GICD_REGS(gicd_base, dist_ctx, num_ints, icfgr, ICFGR);
 
-	/* Restore GICD_IGRPMODR for INTIDs 32 - 1020 */
+	/* Restore GICD_IGRPMODR for INTIDs 32 - 1019 */
 	RESTORE_GICD_REGS(gicd_base, dist_ctx, num_ints, igrpmodr, IGRPMODR);
 
-	/* Restore GICD_NSACR for INTIDs 32 - 1020 */
+	/* Restore GICD_NSACR for INTIDs 32 - 1019 */
 	RESTORE_GICD_REGS(gicd_base, dist_ctx, num_ints, nsacr, NSACR);
 
-	/* Restore GICD_IROUTER for INTIDs 32 - 1020 */
+	/* Restore GICD_IROUTER for INTIDs 32 - 1019 */
 	RESTORE_GICD_REGS(gicd_base, dist_ctx, num_ints, irouter, IROUTER);
 
 	/*
@@ -732,13 +747,13 @@ void gicv3_distif_init_restore(const gicv3_dist_ctx_t * const dist_ctx)
 	 * configured.
 	 */
 
-	/* Restore GICD_ISENABLER for INT_IDs 32 - 1020 */
+	/* Restore GICD_ISENABLER for INT_IDs 32 - 1019 */
 	RESTORE_GICD_REGS(gicd_base, dist_ctx, num_ints, isenabler, ISENABLER);
 
-	/* Restore GICD_ISPENDR for INTIDs 32 - 1020 */
+	/* Restore GICD_ISPENDR for INTIDs 32 - 1019 */
 	RESTORE_GICD_REGS(gicd_base, dist_ctx, num_ints, ispendr, ISPENDR);
 
-	/* Restore GICD_ISACTIVER for INTIDs 32 - 1020 */
+	/* Restore GICD_ISACTIVER for INTIDs 32 - 1019 */
 	RESTORE_GICD_REGS(gicd_base, dist_ctx, num_ints, isactiver, ISACTIVER);
 
 	/* Restore the GICD_CTLR */
@@ -1081,3 +1096,71 @@ unsigned int gicv3_set_pmr(unsigned int mask)
 
 	return old_mask;
 }
+
+/*******************************************************************************
+ * This function delegates the responsibility of discovering the corresponding
+ * Redistributor frames to each CPU itself. It is a modified version of
+ * gicv3_rdistif_base_addrs_probe() and is executed by each CPU in the platform
+ * unlike the previous way in which only the Primary CPU did the discovery of
+ * all the Redistributor frames for every CPU. It also handles the scenario in
+ * which the frames of various CPUs are not contiguous in physical memory.
+ ******************************************************************************/
+int gicv3_rdistif_probe(const uintptr_t gicr_frame)
+{
+	u_register_t mpidr;
+	unsigned int proc_num, proc_self;
+	uint64_t typer_val;
+	uintptr_t rdistif_base;
+	bool gicr_frame_found = false;
+
+	assert(gicv3_driver_data->gicr_base == 0U);
+
+	/* Ensure this function is called with Data Cache enabled */
+#ifndef __aarch64__
+	assert((read_sctlr() & SCTLR_C_BIT) != 0U);
+#else
+	assert((read_sctlr_el3() & SCTLR_C_BIT) != 0U);
+#endif /* !__aarch64__ */
+
+	proc_self = gicv3_driver_data->mpidr_to_core_pos(read_mpidr_el1());
+	rdistif_base = gicr_frame;
+	do {
+		typer_val = gicr_read_typer(rdistif_base);
+		if (gicv3_driver_data->mpidr_to_core_pos != NULL) {
+			mpidr = mpidr_from_gicr_typer(typer_val);
+			proc_num = gicv3_driver_data->mpidr_to_core_pos(mpidr);
+		} else {
+			proc_num = (unsigned int)(typer_val >> TYPER_PROC_NUM_SHIFT) &
+					TYPER_PROC_NUM_MASK;
+		}
+		if (proc_num == proc_self) {
+			/* The base address doesn't need to be initialized on
+			 * every warm boot.
+			 */
+			if (gicv3_driver_data->rdistif_base_addrs[proc_num] != 0U)
+				return 0;
+			gicv3_driver_data->rdistif_base_addrs[proc_num] =
+			rdistif_base;
+			gicr_frame_found = true;
+			break;
+		}
+		rdistif_base += (uintptr_t)(ULL(1) << GICR_PCPUBASE_SHIFT);
+	} while ((typer_val & TYPER_LAST_BIT) == 0U);
+
+	if (!gicr_frame_found)
+		return -1;
+
+	/*
+	 * Flush the driver data to ensure coherency. This is
+	 * not required if platform has HW_ASSISTED_COHERENCY
+	 * enabled.
+	 */
+#if !HW_ASSISTED_COHERENCY
+	/*
+	 * Flush the rdistif_base_addrs[] contents linked to the GICv3 driver.
+	 */
+	flush_dcache_range((uintptr_t)&(gicv3_driver_data->rdistif_base_addrs[proc_num]),
+		sizeof(*(gicv3_driver_data->rdistif_base_addrs)));
+#endif
+	return 0; /* Found matching GICR frame */
+}
diff --git a/drivers/arm/pl011/aarch32/pl011_console.S b/drivers/arm/pl011/aarch32/pl011_console.S
index e1e346c2f..05c8250dc 100644
--- a/drivers/arm/pl011/aarch32/pl011_console.S
+++ b/drivers/arm/pl011/aarch32/pl011_console.S
@@ -57,7 +57,7 @@ func console_pl011_core_init
 #if (ARM_ARCH_MAJOR == 7) && !defined(ARMV7_SUPPORTS_VIRTUALIZATION)
 	push	{r0,r3}
 	softudiv	r0,r1,r2,r3
-	mov	r1, r0
+	mov	r2, r0
 	pop	{r0,r3}
 #else
 	udiv	r2, r1, r2
diff --git a/drivers/arm/sbsa/sbsa.c b/drivers/arm/sbsa/sbsa.c
index 6f00a6019..79c6f2620 100644
--- a/drivers/arm/sbsa/sbsa.c
+++ b/drivers/arm/sbsa/sbsa.c
@@ -4,11 +4,11 @@
  * SPDX-License-Identifier: BSD-3-Clause
  */
 
-#include <plat/common/platform.h>
+#include <assert.h>
+#include <stdint.h>
 #include <drivers/arm/sbsa.h>
 #include <lib/mmio.h>
-#include <stdint_.h>
-#include <assert.h>
+#include <plat/common/platform.h>
 
 void sbsa_watchdog_offset_reg_write(uintptr_t base, uint64_t value)
 {
diff --git a/drivers/arm/scu/scu.c b/drivers/arm/scu/scu.c
new file mode 100644
index 000000000..aceac92fa
--- /dev/null
+++ b/drivers/arm/scu/scu.c
@@ -0,0 +1,51 @@
+/*
+ * Copyright (c) 2019, Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <assert.h>
+#include <drivers/arm/scu.h>
+#include <lib/mmio.h>
+#include <plat/common/platform.h>
+#include <stdint.h>
+
+/*******************************************************************************
+ * Turn ON snoop control unit. This is needed to synchronize the data between
+ * CPU's.
+ ******************************************************************************/
+void enable_snoop_ctrl_unit(uintptr_t base)
+{
+	uint32_t scu_ctrl;
+
+	INFO("[SCU]: enabling snoop control unit ... \n");
+
+	assert(base != 0U);
+	scu_ctrl = mmio_read_32(base + SCU_CTRL_REG);
+
+	/* already enabled? */
+	if ((scu_ctrl & SCU_ENABLE_BIT) != 0) {
+		return;
+	}
+
+	scu_ctrl |= SCU_ENABLE_BIT;
+	mmio_write_32(base + SCU_CTRL_REG, scu_ctrl);
+}
+
+/*******************************************************************************
+ * Snoop Control Unit configuration register. This is read-only register and
+ * contains information such as
+ * - number of CPUs present
+ * - is a particular CPU operating in SMP mode or AMP mode
+ * - data cache size of a particular CPU
+ * - does SCU has ACP port
+ * - is L2CPRESENT
+ * NOTE: user of this API should interpert the bits in this register according
+ * to the TRM
+ ******************************************************************************/
+uint32_t read_snoop_ctrl_unit_cfg(uintptr_t base)
+{
+	assert(base != 0U);
+
+	return mmio_read_32(base + SCU_CFG_REG);
+}
diff --git a/drivers/arm/smmu/smmu_v3.c b/drivers/arm/smmu/smmu_v3.c
index 5493b850a..a082a8107 100644
--- a/drivers/arm/smmu/smmu_v3.c
+++ b/drivers/arm/smmu/smmu_v3.c
@@ -7,23 +7,27 @@
 #include <common/debug.h>
 #include <cdefs.h>
 #include <drivers/arm/smmu_v3.h>
+#include <drivers/delay_timer.h>
 #include <lib/mmio.h>
 
 /* SMMU poll number of retries */
-#define SMMU_POLL_RETRY		1000000
+#define SMMU_POLL_TIMEOUT_US	U(1000)
 
 static int __init smmuv3_poll(uintptr_t smmu_reg, uint32_t mask,
 				uint32_t value)
 {
-	uint32_t reg_val, retries = SMMU_POLL_RETRY;
+	uint32_t reg_val;
+	uint64_t timeout;
 
+	/* Set 1ms timeout value */
+	timeout = timeout_init_us(SMMU_POLL_TIMEOUT_US);
 	do {
 		reg_val = mmio_read_32(smmu_reg);
 		if ((reg_val & mask) == value)
 			return 0;
-	} while (--retries != 0U);
+	} while (!timeout_elapsed(timeout));
 
-	ERROR("Failed to poll SMMUv3 register @%p\n", (void *)smmu_reg);
+	ERROR("Timeout polling SMMUv3 register @%p\n", (void *)smmu_reg);
 	ERROR("Read value 0x%x, expected 0x%x\n", reg_val,
 		value == 0U ? reg_val & ~mask : reg_val | mask);
 	return -1;
diff --git a/drivers/auth/auth_mod.c b/drivers/auth/auth_mod.c
index a6538c4e5..3fb2d1a48 100644
--- a/drivers/auth/auth_mod.c
+++ b/drivers/auth/auth_mod.c
@@ -30,9 +30,6 @@
 
 #pragma weak plat_set_nv_ctr2
 
-/* Pointer to CoT */
-extern const auth_img_desc_t *const *const cot_desc_ptr;
-extern unsigned int auth_img_flags[MAX_NUMBER_IDS];
 
 static int cmp_auth_param_type_desc(const auth_param_type_desc_t *a,
 		const auth_param_type_desc_t *b)
diff --git a/drivers/auth/crypto_mod.c b/drivers/auth/crypto_mod.c
index 5e5ac2b03..110c5045f 100644
--- a/drivers/auth/crypto_mod.c
+++ b/drivers/auth/crypto_mod.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2015-2020, ARM Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -103,3 +103,24 @@ int crypto_mod_verify_hash(void *data_ptr, unsigned int data_len,
 	return crypto_lib_desc.verify_hash(data_ptr, data_len,
 					   digest_info_ptr, digest_info_len);
 }
+
+#if MEASURED_BOOT
+/*
+ * Calculate a hash
+ *
+ * Parameters:
+ *
+ *   alg: message digest algorithm
+ *   data_ptr, data_len: data to be hashed
+ *   output: resulting hash
+ */
+int crypto_mod_calc_hash(unsigned int alg, void *data_ptr,
+			 unsigned int data_len, unsigned char *output)
+{
+	assert(data_ptr != NULL);
+	assert(data_len != 0);
+	assert(output != NULL);
+
+	return crypto_lib_desc.calc_hash(alg, data_ptr, data_len, output);
+}
+#endif	/* MEASURED_BOOT */
diff --git a/drivers/auth/cryptocell/712/cryptocell_crypto.c b/drivers/auth/cryptocell/712/cryptocell_crypto.c
index 395c55085..25eb6bcb6 100644
--- a/drivers/auth/cryptocell/712/cryptocell_crypto.c
+++ b/drivers/auth/cryptocell/712/cryptocell_crypto.c
@@ -225,7 +225,7 @@ static int verify_signature(void *data_ptr, unsigned int data_len,
 	/* Verify the signature */
 	error = CCSbVerifySignature((uintptr_t)PLAT_CRYPTOCELL_BASE,
 			(uint32_t *)data_ptr, &pk, &signature,
-			data_len, RSA_PSS_2048);
+			data_len, RSA_PSS);
 	if (error != CC_OK)
 		return CRYPTO_ERR_SIGNATURE;
 
diff --git a/drivers/auth/cryptocell/cryptocell_crypto.mk b/drivers/auth/cryptocell/cryptocell_crypto.mk
index d42a2e7e1..2fc4ddb11 100644
--- a/drivers/auth/cryptocell/cryptocell_crypto.mk
+++ b/drivers/auth/cryptocell/cryptocell_crypto.mk
@@ -1,5 +1,5 @@
 #
-# Copyright (c) 2017, ARM Limited and Contributors. All rights reserved.
+# Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved.
 #
 # SPDX-License-Identifier: BSD-3-Clause
 #
@@ -12,6 +12,8 @@ TF_MBEDTLS_KEY_ALG_ID		:=	TF_MBEDTLS_RSA
 # Needs to be set to drive mbed TLS configuration correctly
 $(eval $(call add_define,TF_MBEDTLS_KEY_ALG_ID))
 
+$(eval $(call add_define,KEY_SIZE))
+
 # CCSBROM_LIB_PATH must be set to the Cryptocell SBROM library path
 ifeq (${CCSBROM_LIB_PATH},)
   $(error Error: CCSBROM_LIB_PATH not set)
diff --git a/drivers/auth/mbedtls/mbedtls_common.mk b/drivers/auth/mbedtls/mbedtls_common.mk
index 63e65bd47..4b8301541 100644
--- a/drivers/auth/mbedtls/mbedtls_common.mk
+++ b/drivers/auth/mbedtls/mbedtls_common.mk
@@ -1,5 +1,5 @@
 #
-# Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved.
+# Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved.
 #
 # SPDX-License-Identifier: BSD-3-Clause
 #
@@ -48,9 +48,9 @@ LIBMBEDTLS_SRCS		:= $(addprefix ${MBEDTLS_DIR}/library/,	\
 					)
 
 # The platform may define the variable 'TF_MBEDTLS_KEY_ALG' to select the key
-# algorithm to use. If the variable is not defined, select it based on algorithm
-# used for key generation `KEY_ALG`. If `KEY_ALG` is not defined or is
-# defined to `rsa`/`rsa_1_5`, then set the variable to `rsa`.
+# algorithm to use. If the variable is not defined, select it based on
+# algorithm used for key generation `KEY_ALG`. If `KEY_ALG` is not defined,
+# then it is set to `rsa`.
 ifeq (${TF_MBEDTLS_KEY_ALG},)
     ifeq (${KEY_ALG}, ecdsa)
         TF_MBEDTLS_KEY_ALG		:=	ecdsa
@@ -59,6 +59,16 @@ ifeq (${TF_MBEDTLS_KEY_ALG},)
     endif
 endif
 
+ifeq (${TF_MBEDTLS_KEY_SIZE},)
+    ifneq ($(findstring rsa,${TF_MBEDTLS_KEY_ALG}),)
+	ifeq (${KEY_SIZE},)
+            TF_MBEDTLS_KEY_SIZE		:=	2048
+	else
+            TF_MBEDTLS_KEY_SIZE		:=	${KEY_SIZE}
+	endif
+    endif
+endif
+
 ifeq (${HASH_ALG}, sha384)
     TF_MBEDTLS_HASH_ALG_ID	:=	TF_MBEDTLS_SHA384
 else ifeq (${HASH_ALG}, sha512)
@@ -79,6 +89,7 @@ endif
 
 # Needs to be set to drive mbed TLS configuration correctly
 $(eval $(call add_define,TF_MBEDTLS_KEY_ALG_ID))
+$(eval $(call add_define,TF_MBEDTLS_KEY_SIZE))
 $(eval $(call add_define,TF_MBEDTLS_HASH_ALG_ID))
 
 
diff --git a/drivers/auth/mbedtls/mbedtls_crypto.c b/drivers/auth/mbedtls/mbedtls_crypto.c
index 33420fbbd..04fbc648b 100644
--- a/drivers/auth/mbedtls/mbedtls_crypto.c
+++ b/drivers/auth/mbedtls/mbedtls_crypto.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2015-2020, ARM Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -205,7 +205,32 @@ static int verify_hash(void *data_ptr, unsigned int data_len,
 	return CRYPTO_SUCCESS;
 }
 
+#if MEASURED_BOOT
+/*
+ * Calculate a hash
+ *
+ * output points to the computed hash
+ */
+int calc_hash(unsigned int alg, void *data_ptr,
+	      unsigned int data_len, unsigned char *output)
+{
+	const mbedtls_md_info_t *md_info;
+
+	md_info = mbedtls_md_info_from_type((mbedtls_md_type_t)alg);
+	if (md_info == NULL) {
+		return CRYPTO_ERR_HASH;
+	}
+
+	/* Calculate the hash of the data */
+	return mbedtls_md(md_info, data_ptr, data_len, output);
+}
+#endif /* MEASURED_BOOT */
+
 /*
  * Register crypto library descriptor
  */
+#if MEASURED_BOOT
+REGISTER_CRYPTO_LIB(LIB_NAME, init, verify_signature, verify_hash, calc_hash);
+#else
 REGISTER_CRYPTO_LIB(LIB_NAME, init, verify_signature, verify_hash);
+#endif /* MEASURED_BOOT */
diff --git a/drivers/auth/tbbr/tbbr_cot.c b/drivers/auth/tbbr/tbbr_cot.c
index da3631bbf..6dd4ae252 100644
--- a/drivers/auth/tbbr/tbbr_cot.c
+++ b/drivers/auth/tbbr/tbbr_cot.c
@@ -7,6 +7,7 @@
 #include <stddef.h>
 
 #include <platform_def.h>
+#include <drivers/auth/mbedtls/mbedtls_config.h>
 
 #include <drivers/auth/auth_mod.h>
 #if USE_TBBR_DEFS
@@ -19,7 +20,22 @@
 /*
  * Maximum key and hash sizes (in DER format)
  */
+#if TF_MBEDTLS_USE_RSA
+#if TF_MBEDTLS_KEY_SIZE == 1024
+#define PK_DER_LEN			162
+#elif TF_MBEDTLS_KEY_SIZE == 2048
 #define PK_DER_LEN			294
+#elif TF_MBEDTLS_KEY_SIZE == 3072
+#define PK_DER_LEN			422
+#elif TF_MBEDTLS_KEY_SIZE == 4096
+#define PK_DER_LEN			550
+#else
+#error "Invalid value for TF_MBEDTLS_KEY_SIZE"
+#endif
+#else
+#define PK_DER_LEN			294
+#endif
+
 #define HASH_DER_LEN			83
 
 /*
diff --git a/drivers/console/multi_console.c b/drivers/console/multi_console.c
index d9eba7f02..215f49517 100644
--- a/drivers/console/multi_console.c
+++ b/drivers/console/multi_console.c
@@ -70,6 +70,20 @@ void console_set_scope(console_t *console, unsigned int scope)
 	console->flags = (console->flags & ~CONSOLE_FLAG_SCOPE_MASK) | scope;
 }
 
+static int do_putc(int c, console_t *console)
+{
+	int ret;
+
+	if ((c == '\n') &&
+	    ((console->flags & CONSOLE_FLAG_TRANSLATE_CRLF) != 0)) {
+		ret = console->putc('\r', console);
+		if (ret < 0)
+			return ret;
+	}
+
+	return console->putc(c, console);
+}
+
 int console_putc(int c)
 {
 	int err = ERROR_NO_VALID_CONSOLE;
@@ -77,7 +91,7 @@ int console_putc(int c)
 
 	for (console = console_list; console != NULL; console = console->next)
 		if ((console->flags & console_state) && console->putc) {
-			int ret = console->putc(c, console);
+			int ret = do_putc(c, console);
 			if ((err == ERROR_NO_VALID_CONSOLE) || (ret < err))
 				err = ret;
 		}
diff --git a/drivers/delay_timer/delay_timer.c b/drivers/delay_timer/delay_timer.c
index 8c2996ec3..a3fd7bfeb 100644
--- a/drivers/delay_timer/delay_timer.c
+++ b/drivers/delay_timer/delay_timer.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -27,23 +27,32 @@ void udelay(uint32_t usec)
 		(timer_ops->clk_div != 0U) &&
 		(timer_ops->get_timer_value != NULL));
 
-	uint32_t start, delta, total_delta;
+	uint32_t start, delta;
+	uint64_t total_delta;
 
-	assert(usec < (UINT32_MAX / timer_ops->clk_div));
+	assert(usec < (UINT64_MAX / timer_ops->clk_div));
 
 	start = timer_ops->get_timer_value();
 
 	/* Add an extra tick to avoid delaying less than requested. */
 	total_delta =
-		div_round_up(usec * timer_ops->clk_div,
+		div_round_up((uint64_t)usec * timer_ops->clk_div,
 						timer_ops->clk_mult) + 1U;
+	/*
+	 * Precaution for the total_delta ~ UINT32_MAX and the fact that we
+	 * cannot catch every tick of the timer.
+	 * For example 100MHz timer over 25MHz APB will miss at least 4 ticks.
+	 * 1000U is an arbitrary big number which is believed to be sufficient.
+	 */
+	assert(total_delta < (UINT32_MAX - 1000U));
 
 	do {
 		/*
 		 * If the timer value wraps around, the subtraction will
 		 * overflow and it will still give the correct result.
+		 * delta is decreasing counter
 		 */
-		delta = start - timer_ops->get_timer_value(); /* Decreasing counter */
+		delta = start - timer_ops->get_timer_value();
 
 	} while (delta < total_delta);
 }
@@ -54,6 +63,7 @@ void udelay(uint32_t usec)
  ***********************************************************/
 void mdelay(uint32_t msec)
 {
+	assert((msec * 1000UL) < UINT32_MAX);
 	udelay(msec * 1000U);
 }
 
diff --git a/drivers/intel/soc/stratix10/io/s10_memmap_qspi.c b/drivers/intel/soc/stratix10/io/s10_memmap_qspi.c
index a0fc034d8..dcd199148 100644
--- a/drivers/intel/soc/stratix10/io/s10_memmap_qspi.c
+++ b/drivers/intel/soc/stratix10/io/s10_memmap_qspi.c
@@ -26,9 +26,9 @@ typedef struct {
 	 * valid.
 	 */
 	int		in_use;
-	uintptr_t	base;
-	size_t		file_pos;
-	size_t		size;
+	uintptr_t		base;
+	unsigned long long	file_pos;
+	unsigned long long	size;
 } file_state_t;
 
 static file_state_t current_file = {0};
@@ -44,7 +44,7 @@ static int memmap_dev_open(const uintptr_t dev_spec, io_dev_info_t **dev_info);
 static int memmap_block_open(io_dev_info_t *dev_info, const uintptr_t spec,
 			     io_entity_t *entity);
 static int memmap_block_seek(io_entity_t *entity, int mode,
-			     ssize_t offset);
+			     signed long long offset);
 static int memmap_block_len(io_entity_t *entity, size_t *length);
 static int memmap_block_read(io_entity_t *entity, uintptr_t buffer,
 			     size_t length, size_t *length_read);
@@ -131,7 +131,8 @@ static int memmap_block_open(io_dev_info_t *dev_info, const uintptr_t spec,
 
 
 /* Seek to a particular file offset on the memmap device */
-static int memmap_block_seek(io_entity_t *entity, int mode, ssize_t offset)
+static int memmap_block_seek(io_entity_t *entity, int mode,
+			     signed long long offset)
 {
 	int result = -ENOENT;
 	file_state_t *fp;
@@ -143,7 +144,8 @@ static int memmap_block_seek(io_entity_t *entity, int mode, ssize_t offset)
 		fp = (file_state_t *) entity->info;
 
 		/* Assert that new file position is valid */
-		assert((offset >= 0) && (offset < fp->size));
+		assert((offset >= 0) &&
+		       ((unsigned long long)offset < fp->size));
 
 		/* Reset file position */
 		fp->file_pos = offset;
@@ -171,7 +173,7 @@ static int memmap_block_read(io_entity_t *entity, uintptr_t buffer,
 			     size_t length, size_t *length_read)
 {
 	file_state_t *fp;
-	size_t pos_after;
+	unsigned long long pos_after;
 
 	assert(entity != NULL);
 	assert(length_read != NULL);
@@ -198,7 +200,7 @@ static int memmap_block_write(io_entity_t *entity, const uintptr_t buffer,
 			      size_t length, size_t *length_written)
 {
 	file_state_t *fp;
-	size_t pos_after;
+	unsigned long long pos_after;
 
 	assert(entity != NULL);
 	assert(length_written != NULL);
diff --git a/drivers/io/io_block.c b/drivers/io/io_block.c
index f190a4307..5d45c2f17 100644
--- a/drivers/io/io_block.c
+++ b/drivers/io/io_block.c
@@ -19,17 +19,17 @@
 typedef struct {
 	io_block_dev_spec_t	*dev_spec;
 	uintptr_t		base;
-	size_t			file_pos;
-	size_t			size;
+	unsigned long long	file_pos;
+	unsigned long long	size;
 } block_dev_state_t;
 
-#define is_power_of_2(x)	((x != 0) && ((x & (x - 1)) == 0))
+#define is_power_of_2(x)	(((x) != 0U) && (((x) & ((x) - 1U)) == 0U))
 
 io_type_t device_type_block(void);
 
 static int block_open(io_dev_info_t *dev_info, const uintptr_t spec,
 		      io_entity_t *entity);
-static int block_seek(io_entity_t *entity, int mode, ssize_t offset);
+static int block_seek(io_entity_t *entity, int mode, signed long long offset);
 static int block_read(io_entity_t *entity, uintptr_t buffer, size_t length,
 		      size_t *length_read);
 static int block_write(io_entity_t *entity, const uintptr_t buffer,
@@ -148,21 +148,21 @@ static int block_open(io_dev_info_t *dev_info, const uintptr_t spec,
 }
 
 /* parameter offset is relative address at here */
-static int block_seek(io_entity_t *entity, int mode, ssize_t offset)
+static int block_seek(io_entity_t *entity, int mode, signed long long offset)
 {
 	block_dev_state_t *cur;
 
 	assert(entity->info != (uintptr_t)NULL);
 
 	cur = (block_dev_state_t *)entity->info;
-	assert((offset >= 0) && (offset < cur->size));
+	assert((offset >= 0) && ((unsigned long long)offset < cur->size));
 
 	switch (mode) {
 	case IO_SEEK_SET:
-		cur->file_pos = offset;
+		cur->file_pos = (unsigned long long)offset;
 		break;
 	case IO_SEEK_CUR:
-		cur->file_pos += offset;
+		cur->file_pos += (unsigned long long)offset;
 		break;
 	default:
 		return -EINVAL;
@@ -270,7 +270,7 @@ static int block_read(io_entity_t *entity, uintptr_t buffer, size_t length,
 	buf = &(cur->dev_spec->buffer);
 	block_size = cur->dev_spec->block_size;
 	assert((length <= cur->size) &&
-	       (length > 0) &&
+	       (length > 0U) &&
 	       (ops->read != 0));
 
 	/*
@@ -279,7 +279,7 @@ static int block_read(io_entity_t *entity, uintptr_t buffer, size_t length,
 	 * on the low level driver.
 	 */
 	count = 0;
-	for (left = length; left > 0; left -= nbytes) {
+	for (left = length; left > 0U; left -= nbytes) {
 		/*
 		 * We must only request operations aligned to the block
 		 * size. Therefore if file_pos is not block-aligned,
@@ -288,7 +288,7 @@ static int block_read(io_entity_t *entity, uintptr_t buffer, size_t length,
 		 * similarly, the number of bytes requested must be a
 		 * block size multiple
 		 */
-		skip = cur->file_pos & (block_size - 1);
+		skip = cur->file_pos & (block_size - 1U);
 
 		/*
 		 * Calculate the block number containing file_pos
@@ -296,7 +296,7 @@ static int block_read(io_entity_t *entity, uintptr_t buffer, size_t length,
 		 */
 		lba = (cur->file_pos + cur->base) / block_size;
 
-		if (skip + left > buf->length) {
+		if ((skip + left) > buf->length) {
 			/*
 			 * The underlying read buffer is too small to
 			 * read all the required data - limit to just
@@ -311,7 +311,8 @@ static int block_read(io_entity_t *entity, uintptr_t buffer, size_t length,
 			 * block size.
 			 */
 			request = skip + left;
-			request = (request + (block_size - 1)) & ~(block_size - 1);
+			request = (request + (block_size - 1U)) &
+				~(block_size - 1U);
 		}
 		request = ops->read(lba, buf->offset, request);
 
@@ -330,7 +331,7 @@ static int block_read(io_entity_t *entity, uintptr_t buffer, size_t length,
 		 * the read data when copying to the user buffer.
 		 */
 		nbytes = request - skip;
-		padding = (nbytes > left) ? nbytes - left : 0;
+		padding = (nbytes > left) ? nbytes - left : 0U;
 		nbytes -= padding;
 
 		memcpy((void *)(buffer + count),
@@ -381,7 +382,7 @@ static int block_write(io_entity_t *entity, const uintptr_t buffer,
 	buf = &(cur->dev_spec->buffer);
 	block_size = cur->dev_spec->block_size;
 	assert((length <= cur->size) &&
-	       (length > 0) &&
+	       (length > 0U) &&
 	       (ops->read != 0) &&
 	       (ops->write != 0));
 
@@ -391,7 +392,7 @@ static int block_write(io_entity_t *entity, const uintptr_t buffer,
 	 * on the low level driver.
 	 */
 	count = 0;
-	for (left = length; left > 0; left -= nbytes) {
+	for (left = length; left > 0U; left -= nbytes) {
 		/*
 		 * We must only request operations aligned to the block
 		 * size. Therefore if file_pos is not block-aligned,
@@ -400,7 +401,7 @@ static int block_write(io_entity_t *entity, const uintptr_t buffer,
 		 * similarly, the number of bytes requested must be a
 		 * block size multiple
 		 */
-		skip = cur->file_pos & (block_size - 1);
+		skip = cur->file_pos & (block_size - 1U);
 
 		/*
 		 * Calculate the block number containing file_pos
@@ -408,7 +409,7 @@ static int block_write(io_entity_t *entity, const uintptr_t buffer,
 		 */
 		lba = (cur->file_pos + cur->base) / block_size;
 
-		if (skip + left > buf->length) {
+		if ((skip + left) > buf->length) {
 			/*
 			 * The underlying read buffer is too small to
 			 * read all the required data - limit to just
@@ -423,7 +424,8 @@ static int block_write(io_entity_t *entity, const uintptr_t buffer,
 			 * block size.
 			 */
 			request = skip + left;
-			request = (request + (block_size - 1)) & ~(block_size - 1);
+			request = (request + (block_size - 1U)) &
+				~(block_size - 1U);
 		}
 
 		/*
@@ -432,7 +434,7 @@ static int block_write(io_entity_t *entity, const uintptr_t buffer,
 		 * of the current request.
 		 */
 		nbytes = request - skip;
-		padding = (nbytes > left) ? nbytes - left : 0;
+		padding = (nbytes > left) ? nbytes - left : 0U;
 		nbytes -= padding;
 
 		/*
@@ -440,14 +442,14 @@ static int block_write(io_entity_t *entity, const uintptr_t buffer,
 		 * some content and it means that we have to read before
 		 * writing
 		 */
-		if (skip > 0 || padding > 0) {
+		if ((skip > 0U) || (padding > 0U)) {
 			request = ops->read(lba, buf->offset, request);
 			/*
 			 * The read may return size less than
 			 * requested. Round down to the nearest block
 			 * boundary
 			 */
-			request &= ~(block_size-1);
+			request &= ~(block_size - 1U);
 			if (request <= skip) {
 				/*
 				 * We couldn't read enough bytes to jump over
@@ -458,7 +460,7 @@ static int block_write(io_entity_t *entity, const uintptr_t buffer,
 				return -EIO;
 			}
 			nbytes = request - skip;
-			padding = (nbytes > left) ? nbytes - left : 0;
+			padding = (nbytes > left) ? nbytes - left : 0U;
 			nbytes -= padding;
 		}
 
@@ -477,7 +479,7 @@ static int block_write(io_entity_t *entity, const uintptr_t buffer,
 		 * buffer
 		 */
 		nbytes = request - skip;
-		padding = (nbytes > left) ? nbytes - left : 0;
+		padding = (nbytes > left) ? nbytes - left : 0U;
 		nbytes -= padding;
 
 		cur->file_pos += nbytes;
@@ -505,7 +507,7 @@ static int block_dev_open(const uintptr_t dev_spec, io_dev_info_t **dev_info)
 
 	assert(dev_info != NULL);
 	result = allocate_dev_info(&info);
-	if (result)
+	if (result != 0)
 		return -ENOENT;
 
 	cur = (block_dev_state_t *)info->info;
@@ -513,10 +515,10 @@ static int block_dev_open(const uintptr_t dev_spec, io_dev_info_t **dev_info)
 	cur->dev_spec = (io_block_dev_spec_t *)dev_spec;
 	buffer = &(cur->dev_spec->buffer);
 	block_size = cur->dev_spec->block_size;
-	assert((block_size > 0) &&
-	       (is_power_of_2(block_size) != 0) &&
-	       ((buffer->offset % block_size) == 0) &&
-	       ((buffer->length % block_size) == 0));
+	assert((block_size > 0U) &&
+	       (is_power_of_2(block_size) != 0U) &&
+	       ((buffer->offset % block_size) == 0U) &&
+	       ((buffer->length % block_size) == 0U));
 
 	*dev_info = info;	/* cast away const */
 	(void)block_size;
diff --git a/drivers/io/io_fip.c b/drivers/io/io_fip.c
index 544b37dbe..5d49fffaa 100644
--- a/drivers/io/io_fip.c
+++ b/drivers/io/io_fip.c
@@ -304,7 +304,8 @@ static int fip_file_open(io_dev_info_t *dev_info, const uintptr_t spec,
 	}
 
 	/* Seek past the FIP header into the Table of Contents */
-	result = io_seek(backend_handle, IO_SEEK_SET, sizeof(fip_toc_header_t));
+	result = io_seek(backend_handle, IO_SEEK_SET,
+			 (signed long long)sizeof(fip_toc_header_t));
 	if (result != 0) {
 		WARN("fip_file_open: failed to seek\n");
 		result = -ENOENT;
@@ -389,7 +390,8 @@ static int fip_file_read(io_entity_t *entity, uintptr_t buffer, size_t length,
 
 	/* Seek to the position in the FIP where the payload lives */
 	file_offset = fp->entry.offset_address + fp->file_pos;
-	result = io_seek(backend_handle, IO_SEEK_SET, file_offset);
+	result = io_seek(backend_handle, IO_SEEK_SET,
+			 (signed long long)file_offset);
 	if (result != 0) {
 		WARN("fip_file_read: failed to seek\n");
 		result = -ENOENT;
diff --git a/drivers/io/io_memmap.c b/drivers/io/io_memmap.c
index 96590b6c0..eed50cc08 100644
--- a/drivers/io/io_memmap.c
+++ b/drivers/io/io_memmap.c
@@ -23,10 +23,10 @@ typedef struct {
 	/* Use the 'in_use' flag as any value for base and file_pos could be
 	 * valid.
 	 */
-	int		in_use;
-	uintptr_t	base;
-	size_t		file_pos;
-	size_t		size;
+	int			in_use;
+	uintptr_t		base;
+	unsigned long long	file_pos;
+	unsigned long long	size;
 } file_state_t;
 
 static file_state_t current_file = {0};
@@ -42,7 +42,7 @@ static int memmap_dev_open(const uintptr_t dev_spec, io_dev_info_t **dev_info);
 static int memmap_block_open(io_dev_info_t *dev_info, const uintptr_t spec,
 			     io_entity_t *entity);
 static int memmap_block_seek(io_entity_t *entity, int mode,
-			     ssize_t offset);
+			     signed long long offset);
 static int memmap_block_len(io_entity_t *entity, size_t *length);
 static int memmap_block_read(io_entity_t *entity, uintptr_t buffer,
 			     size_t length, size_t *length_read);
@@ -129,7 +129,8 @@ static int memmap_block_open(io_dev_info_t *dev_info, const uintptr_t spec,
 
 
 /* Seek to a particular file offset on the memmap device */
-static int memmap_block_seek(io_entity_t *entity, int mode, ssize_t offset)
+static int memmap_block_seek(io_entity_t *entity, int mode,
+			     signed long long offset)
 {
 	int result = -ENOENT;
 	file_state_t *fp;
@@ -141,10 +142,11 @@ static int memmap_block_seek(io_entity_t *entity, int mode, ssize_t offset)
 		fp = (file_state_t *) entity->info;
 
 		/* Assert that new file position is valid */
-		assert((offset >= 0) && (offset < fp->size));
+		assert((offset >= 0) &&
+		       ((unsigned long long)offset < fp->size));
 
 		/* Reset file position */
-		fp->file_pos = offset;
+		fp->file_pos = (unsigned long long)offset;
 		result = 0;
 	}
 
@@ -158,7 +160,7 @@ static int memmap_block_len(io_entity_t *entity, size_t *length)
 	assert(entity != NULL);
 	assert(length != NULL);
 
-	*length = ((file_state_t *)entity->info)->size;
+	*length = (size_t)((file_state_t *)entity->info)->size;
 
 	return 0;
 }
@@ -169,7 +171,7 @@ static int memmap_block_read(io_entity_t *entity, uintptr_t buffer,
 			     size_t length, size_t *length_read)
 {
 	file_state_t *fp;
-	size_t pos_after;
+	unsigned long long pos_after;
 
 	assert(entity != NULL);
 	assert(length_read != NULL);
@@ -180,7 +182,8 @@ static int memmap_block_read(io_entity_t *entity, uintptr_t buffer,
 	pos_after = fp->file_pos + length;
 	assert((pos_after >= fp->file_pos) && (pos_after <= fp->size));
 
-	memcpy((void *)buffer, (void *)(fp->base + fp->file_pos), length);
+	memcpy((void *)buffer,
+	       (void *)((uintptr_t)(fp->base + fp->file_pos)), length);
 
 	*length_read = length;
 
@@ -196,7 +199,7 @@ static int memmap_block_write(io_entity_t *entity, const uintptr_t buffer,
 			      size_t length, size_t *length_written)
 {
 	file_state_t *fp;
-	size_t pos_after;
+	unsigned long long pos_after;
 
 	assert(entity != NULL);
 	assert(length_written != NULL);
@@ -207,7 +210,8 @@ static int memmap_block_write(io_entity_t *entity, const uintptr_t buffer,
 	pos_after = fp->file_pos + length;
 	assert((pos_after >= fp->file_pos) && (pos_after <= fp->size));
 
-	memcpy((void *)(fp->base + fp->file_pos), (void *)buffer, length);
+	memcpy((void *)((uintptr_t)(fp->base + fp->file_pos)),
+	       (void *)buffer, length);
 
 	*length_written = length;
 
diff --git a/drivers/io/io_mtd.c b/drivers/io/io_mtd.c
new file mode 100644
index 000000000..7575fa250
--- /dev/null
+++ b/drivers/io/io_mtd.c
@@ -0,0 +1,248 @@
+/*
+ * Copyright (c) 2019, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <assert.h>
+#include <errno.h>
+#include <string.h>
+
+#include <platform_def.h>
+
+#include <common/debug.h>
+#include <drivers/io/io_driver.h>
+#include <drivers/io/io_mtd.h>
+#include <lib/utils.h>
+
+typedef struct {
+	io_mtd_dev_spec_t	*dev_spec;
+	uintptr_t		base;
+	unsigned long long	offset;		/* Offset in bytes */
+	unsigned long long	size;	/* Size of device in bytes */
+} mtd_dev_state_t;
+
+io_type_t device_type_mtd(void);
+
+static int mtd_open(io_dev_info_t *dev_info, const uintptr_t spec,
+		    io_entity_t *entity);
+static int mtd_seek(io_entity_t *entity, int mode, signed long long offset);
+static int mtd_read(io_entity_t *entity, uintptr_t buffer, size_t length,
+		    size_t *length_read);
+static int mtd_close(io_entity_t *entity);
+static int mtd_dev_open(const uintptr_t dev_spec, io_dev_info_t **dev_info);
+static int mtd_dev_close(io_dev_info_t *dev_info);
+
+static const io_dev_connector_t mtd_dev_connector = {
+	.dev_open	= mtd_dev_open
+};
+
+static const io_dev_funcs_t mtd_dev_funcs = {
+	.type		= device_type_mtd,
+	.open		= mtd_open,
+	.seek		= mtd_seek,
+	.read		= mtd_read,
+	.close		= mtd_close,
+	.dev_close	= mtd_dev_close,
+};
+
+static mtd_dev_state_t state_pool[MAX_IO_MTD_DEVICES];
+static io_dev_info_t dev_info_pool[MAX_IO_MTD_DEVICES];
+
+io_type_t device_type_mtd(void)
+{
+	return IO_TYPE_MTD;
+}
+
+/* Locate a MTD state in the pool, specified by address */
+static int find_first_mtd_state(const io_mtd_dev_spec_t *dev_spec,
+				unsigned int *index_out)
+{
+	unsigned int index;
+	int result = -ENOENT;
+
+	for (index = 0U; index < MAX_IO_MTD_DEVICES; index++) {
+		/* dev_spec is used as identifier since it's unique */
+		if (state_pool[index].dev_spec == dev_spec) {
+			result = 0;
+			*index_out = index;
+			break;
+		}
+	}
+
+	return result;
+}
+
+/* Allocate a device info from the pool */
+static int allocate_dev_info(io_dev_info_t **dev_info)
+{
+	unsigned int index = 0U;
+	int result;
+
+	result = find_first_mtd_state(NULL, &index);
+	if (result != 0) {
+		return -ENOMEM;
+	}
+
+	dev_info_pool[index].funcs = &mtd_dev_funcs;
+	dev_info_pool[index].info = (uintptr_t)&state_pool[index];
+	*dev_info = &dev_info_pool[index];
+
+	return 0;
+}
+
+/* Release a device info from the pool */
+static int free_dev_info(io_dev_info_t *dev_info)
+{
+	int result;
+	unsigned int index = 0U;
+	mtd_dev_state_t *state;
+
+	state = (mtd_dev_state_t *)dev_info->info;
+	result = find_first_mtd_state(state->dev_spec, &index);
+	if (result != 0) {
+		return result;
+	}
+
+	zeromem(state, sizeof(mtd_dev_state_t));
+	zeromem(dev_info, sizeof(io_dev_info_t));
+
+	return 0;
+}
+
+static int mtd_open(io_dev_info_t *dev_info, const uintptr_t spec,
+		    io_entity_t *entity)
+{
+	mtd_dev_state_t *cur;
+
+	assert((dev_info->info != 0UL) && (entity->info == 0UL));
+
+	cur = (mtd_dev_state_t *)dev_info->info;
+	entity->info = (uintptr_t)cur;
+	cur->offset = 0U;
+
+	return 0;
+}
+
+/* Seek to a specific position using offset */
+static int mtd_seek(io_entity_t *entity, int mode, signed long long offset)
+{
+	mtd_dev_state_t *cur;
+
+	assert((entity->info != (uintptr_t)NULL) && (offset >= 0));
+
+	cur = (mtd_dev_state_t *)entity->info;
+
+	switch (mode) {
+	case IO_SEEK_SET:
+		if ((offset >= 0) &&
+		    ((unsigned long long)offset >= cur->size)) {
+			return -EINVAL;
+		}
+
+		cur->offset = offset;
+		break;
+	case IO_SEEK_CUR:
+		if (((cur->offset + (unsigned long long)offset) >=
+		     cur->size) ||
+		    ((cur->offset + (unsigned long long)offset) <
+		     cur->offset)) {
+			return -EINVAL;
+		}
+
+		cur->offset += (unsigned long long)offset;
+		break;
+	default:
+		return -EINVAL;
+	}
+
+	return 0;
+}
+
+static int mtd_read(io_entity_t *entity, uintptr_t buffer, size_t length,
+		    size_t *out_length)
+{
+	mtd_dev_state_t *cur;
+	io_mtd_ops_t *ops;
+	int ret;
+
+	assert(entity->info != (uintptr_t)NULL);
+	assert((length > 0U) && (buffer != (uintptr_t)NULL));
+
+	cur = (mtd_dev_state_t *)entity->info;
+	ops = &cur->dev_spec->ops;
+	assert(ops->read != NULL);
+
+	VERBOSE("Read at %llx into %lx, length %zi\n",
+		cur->offset, buffer, length);
+	if ((cur->offset + length) > cur->dev_spec->device_size) {
+		return -EINVAL;
+	}
+
+	ret = ops->read(cur->offset, buffer, length, out_length);
+	if (ret < 0) {
+		return ret;
+	}
+
+	assert(*out_length == length);
+	cur->offset += *out_length;
+
+	return 0;
+}
+
+static int mtd_close(io_entity_t *entity)
+{
+	entity->info = (uintptr_t)NULL;
+
+	return 0;
+}
+
+static int mtd_dev_open(const uintptr_t dev_spec, io_dev_info_t **dev_info)
+{
+	mtd_dev_state_t *cur;
+	io_dev_info_t *info;
+	io_mtd_ops_t *ops;
+	int result;
+
+	result = allocate_dev_info(&info);
+	if (result != 0) {
+		return -ENOENT;
+	}
+
+	cur = (mtd_dev_state_t *)info->info;
+	cur->dev_spec = (io_mtd_dev_spec_t *)dev_spec;
+	*dev_info = info;
+	ops = &(cur->dev_spec->ops);
+	if (ops->init != NULL) {
+		result = ops->init(&cur->dev_spec->device_size,
+				   &cur->dev_spec->erase_size);
+	}
+
+	if (result == 0) {
+		cur->size = cur->dev_spec->device_size;
+	} else {
+		cur->size = 0ULL;
+	}
+
+	return result;
+}
+
+static int mtd_dev_close(io_dev_info_t *dev_info)
+{
+	return free_dev_info(dev_info);
+}
+
+/* Exported functions */
+
+/* Register the MTD driver in the IO abstraction */
+int register_io_dev_mtd(const io_dev_connector_t **dev_con)
+{
+	int result;
+
+	result = io_register_device(&dev_info_pool[0]);
+	if (result == 0) {
+		*dev_con = &mtd_dev_connector;
+	}
+
+	return result;
+}
diff --git a/drivers/io/io_semihosting.c b/drivers/io/io_semihosting.c
index 23d09c118..4ceddc6cc 100644
--- a/drivers/io/io_semihosting.c
+++ b/drivers/io/io_semihosting.c
@@ -25,7 +25,7 @@ static io_type_t device_type_sh(void)
 static int sh_dev_open(const uintptr_t dev_spec, io_dev_info_t **dev_info);
 static int sh_file_open(io_dev_info_t *dev_info, const uintptr_t spec,
 		io_entity_t *entity);
-static int sh_file_seek(io_entity_t *entity, int mode, ssize_t offset);
+static int sh_file_seek(io_entity_t *entity, int mode, signed long long offset);
 static int sh_file_len(io_entity_t *entity, size_t *length);
 static int sh_file_read(io_entity_t *entity, uintptr_t buffer, size_t length,
 		size_t *length_read);
@@ -90,7 +90,7 @@ static int sh_file_open(io_dev_info_t *dev_info __unused,
 
 
 /* Seek to a particular file offset on the semi-hosting device */
-static int sh_file_seek(io_entity_t *entity, int mode, ssize_t offset)
+static int sh_file_seek(io_entity_t *entity, int mode, signed long long offset)
 {
 	long file_handle, sh_result;
 
@@ -98,7 +98,7 @@ static int sh_file_seek(io_entity_t *entity, int mode, ssize_t offset)
 
 	file_handle = (long)entity->info;
 
-	sh_result = semihosting_file_seek(file_handle, offset);
+	sh_result = semihosting_file_seek(file_handle, (ssize_t)offset);
 
 	return (sh_result == 0) ? 0 : -ENOENT;
 }
diff --git a/drivers/io/io_storage.c b/drivers/io/io_storage.c
index e444f87f7..b8c1d6479 100644
--- a/drivers/io/io_storage.c
+++ b/drivers/io/io_storage.c
@@ -237,7 +237,7 @@ int io_open(uintptr_t dev_handle, const uintptr_t spec, uintptr_t *handle)
 
 
 /* Seek to a specific position in an IO entity */
-int io_seek(uintptr_t handle, io_seek_mode_t mode, ssize_t offset)
+int io_seek(uintptr_t handle, io_seek_mode_t mode, signed long long offset)
 {
 	int result = -ENODEV;
 	assert(is_valid_entity(handle) && is_valid_seek_mode(mode));
diff --git a/drivers/marvell/comphy/phy-comphy-3700.c b/drivers/marvell/comphy/phy-comphy-3700.c
index 2e8c4128e..f6a40a587 100644
--- a/drivers/marvell/comphy/phy-comphy-3700.c
+++ b/drivers/marvell/comphy/phy-comphy-3700.c
@@ -195,6 +195,45 @@ error:
 	ERROR("COMPHY[%d] mode[%d] is invalid\n", comphy_index, mode);
 }
 
+/*
+ * This is something like the inverse of the previous function: for given
+ * lane it returns COMPHY_*_MODE.
+ *
+ * It is useful when powering the phy off.
+ *
+ * This function returns COMPHY_USB3_MODE even if the phy was configured
+ * with COMPHY_USB3D_MODE or COMPHY_USB3H_MODE. (The usb3 phy initialization
+ * code does not differentiate between these modes.)
+ * Also it returns COMPHY_SGMII_MODE even if the phy was configures with
+ * COMPHY_HS_SGMII_MODE. (The sgmii phy initialization code does differentiate
+ * between these modes, but it is irrelevant when powering the phy off.)
+ */
+static int mvebu_a3700_comphy_get_mode(uint8_t comphy_index)
+{
+	uint32_t reg;
+
+	reg = mmio_read_32(MVEBU_COMPHY_REG_BASE + COMPHY_SELECTOR_PHY_REG);
+	switch (comphy_index) {
+	case COMPHY_LANE0:
+		if ((reg & COMPHY_SELECTOR_USB3_GBE1_SEL_BIT) != 0)
+			return COMPHY_USB3_MODE;
+		else
+			return COMPHY_SGMII_MODE;
+	case COMPHY_LANE1:
+		if ((reg & COMPHY_SELECTOR_PCIE_GBE0_SEL_BIT) != 0)
+			return COMPHY_PCIE_MODE;
+		else
+			return COMPHY_SGMII_MODE;
+	case COMPHY_LANE2:
+		if ((reg & COMPHY_SELECTOR_USB3_PHY_SEL_BIT) != 0)
+			return COMPHY_USB3_MODE;
+		else
+			return COMPHY_SATA_MODE;
+	}
+
+	return COMPHY_UNUSED;
+}
+
 /* It is only used for SATA and USB3 on comphy lane2. */
 static void comphy_set_indirect(uintptr_t addr, uint32_t offset, uint16_t data,
 				uint16_t mask, int mode)
@@ -547,6 +586,23 @@ static int mvebu_a3700_comphy_sgmii_power_on(uint8_t comphy_index,
 	return ret;
 }
 
+static int mvebu_a3700_comphy_sgmii_power_off(uint8_t comphy_index)
+{
+	int ret = 0;
+	uint32_t mask, data, offset;
+
+	debug_enter();
+
+	data = PIN_RESET_CORE_BIT | PIN_RESET_COMPHY_BIT;
+	mask = 0;
+	offset = MVEBU_COMPHY_REG_BASE + COMPHY_PHY_CFG1_OFFSET(comphy_index);
+	reg_set(offset, data, mask);
+
+	debug_exit();
+
+	return ret;
+}
+
 static int mvebu_a3700_comphy_usb3_power_on(uint8_t comphy_index,
 					    uint32_t comphy_mode)
 {
@@ -721,11 +777,11 @@ static int mvebu_a3700_comphy_usb3_power_on(uint8_t comphy_index,
 	udelay(PLL_SET_DELAY_US);
 
 	if (comphy_index == COMPHY_LANE2) {
-		data = COMPHY_LOOPBACK_REG0 + USB3PHY_LANE2_REG_BASE_OFFSET;
+		data = COMPHY_REG_LANE_STATUS1_ADDR + USB3PHY_LANE2_REG_BASE_OFFSET;
 		mmio_write_32(reg_base + COMPHY_LANE2_INDIR_ADDR_OFFSET,
 			      data);
 
-		addr = COMPHY_LOOPBACK_REG0 + USB3PHY_LANE2_REG_BASE_OFFSET;
+		addr = reg_base + COMPHY_LANE2_INDIR_DATA_OFFSET;
 		ret = polling_with_timeout(addr, TXDCLK_PCLK_EN, TXDCLK_PCLK_EN,
 					   COMPHY_PLL_TIMEOUT, REG_32BIT);
 	} else {
@@ -908,7 +964,20 @@ int mvebu_3700_comphy_power_off(uint8_t comphy_index, uint32_t comphy_mode)
 
 	debug_enter();
 
+	if (!mode) {
+		/*
+		 * The user did not specify which mode should be powered off.
+		 * In this case we can identify this by reading the phy selector
+		 * register.
+		 */
+		mode = mvebu_a3700_comphy_get_mode(comphy_index);
+	}
+
 	switch (mode) {
+	case(COMPHY_SGMII_MODE):
+	case(COMPHY_HS_SGMII_MODE):
+		err = mvebu_a3700_comphy_sgmii_power_off(comphy_index);
+		break;
 	case (COMPHY_USB3_MODE):
 	case (COMPHY_USB3H_MODE):
 		err = mvebu_a3700_comphy_usb3_power_off();
diff --git a/drivers/mentor/i2c/mi2cv.c b/drivers/mentor/i2c/mi2cv.c
index 1cdcf7478..b0270c955 100644
--- a/drivers/mentor/i2c/mi2cv.c
+++ b/drivers/mentor/i2c/mi2cv.c
@@ -81,14 +81,14 @@ static void mentor_i2c_interrupt_clear(void)
 	udelay(1);
 }
 
-static int mentor_i2c_interrupt_get(void)
+static bool mentor_i2c_interrupt_get(void)
 {
 	uint32_t reg;
 
 	/* get the interrupt flag bit */
 	reg = mmio_read_32((uintptr_t)&base->control);
 	reg &= I2C_CONTROL_IFLG;
-	return reg && I2C_CONTROL_IFLG;
+	return (reg != 0U);
 }
 
 static int mentor_i2c_wait_interrupt(void)
diff --git a/drivers/mmc/mmc.c b/drivers/mmc/mmc.c
index db6f3f9e4..b5f6a10d3 100644
--- a/drivers/mmc/mmc.c
+++ b/drivers/mmc/mmc.c
@@ -361,7 +361,7 @@ static int sd_send_op_cond(void)
 			return 0;
 		}
 
-		mdelay(1);
+		mdelay(10);
 	}
 
 	ERROR("ACMD41 failed after %d retries\n", SEND_OP_COND_MAX_RETRIES);
diff --git a/drivers/mtd/nand/core.c b/drivers/mtd/nand/core.c
new file mode 100644
index 000000000..44b001e35
--- /dev/null
+++ b/drivers/mtd/nand/core.c
@@ -0,0 +1,118 @@
+/*
+ * Copyright (c) 2019, STMicroelectronics - All Rights Reserved
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <assert.h>
+#include <errno.h>
+#include <stddef.h>
+
+#include <platform_def.h>
+
+#include <common/debug.h>
+#include <drivers/delay_timer.h>
+#include <drivers/nand.h>
+#include <lib/utils.h>
+
+/*
+ * Define a single nand_device used by specific NAND frameworks.
+ */
+static struct nand_device nand_dev;
+static uint8_t scratch_buff[PLATFORM_MTD_MAX_PAGE_SIZE];
+
+int nand_read(unsigned int offset, uintptr_t buffer, size_t length,
+	      size_t *length_read)
+{
+	unsigned int block = offset / nand_dev.block_size;
+	unsigned int end_block = (offset + length - 1U) / nand_dev.block_size;
+	unsigned int page_start =
+		(offset % nand_dev.block_size) / nand_dev.page_size;
+	unsigned int nb_pages = nand_dev.block_size / nand_dev.page_size;
+	unsigned int start_offset = offset % nand_dev.page_size;
+	unsigned int page;
+	unsigned int bytes_read;
+	int is_bad;
+	int ret;
+
+	VERBOSE("Block %u - %u, page_start %u, nb %u, length %zu, offset %u\n",
+		block, end_block, page_start, nb_pages, length, offset);
+
+	*length_read = 0UL;
+
+	if (((start_offset != 0U) || (length % nand_dev.page_size) != 0U) &&
+	    (sizeof(scratch_buff) < nand_dev.page_size)) {
+		return -EINVAL;
+	}
+
+	while (block <= end_block) {
+		is_bad = nand_dev.mtd_block_is_bad(block);
+		if (is_bad < 0) {
+			return is_bad;
+		}
+
+		if (is_bad == 1) {
+			/* Skip the block */
+			uint32_t max_block =
+				nand_dev.size / nand_dev.block_size;
+
+			block++;
+			end_block++;
+			if ((block < max_block) && (end_block < max_block)) {
+				continue;
+			}
+
+			return -EIO;
+		}
+
+		for (page = page_start; page < nb_pages; page++) {
+			if ((start_offset != 0U) ||
+			    (length < nand_dev.page_size)) {
+				ret = nand_dev.mtd_read_page(
+						&nand_dev,
+						(block * nb_pages) + page,
+						(uintptr_t)scratch_buff);
+				if (ret != 0) {
+					return ret;
+				}
+
+				bytes_read = MIN((size_t)(nand_dev.page_size -
+							  start_offset),
+						 length);
+
+				memcpy((uint8_t *)buffer,
+				       scratch_buff + start_offset,
+				       bytes_read);
+
+				start_offset = 0U;
+			} else {
+				ret = nand_dev.mtd_read_page(&nand_dev,
+						(block * nb_pages) + page,
+						buffer);
+				if (ret != 0) {
+					return ret;
+				}
+
+				bytes_read = nand_dev.page_size;
+			}
+
+			length -= bytes_read;
+			buffer += bytes_read;
+			*length_read += bytes_read;
+
+			if (length == 0U) {
+				break;
+			}
+		}
+
+		page_start = 0U;
+		block++;
+	}
+
+	return 0;
+}
+
+struct nand_device *get_nand_device(void)
+{
+	return &nand_dev;
+}
diff --git a/drivers/mtd/nand/raw_nand.c b/drivers/mtd/nand/raw_nand.c
new file mode 100644
index 000000000..48131fcb2
--- /dev/null
+++ b/drivers/mtd/nand/raw_nand.c
@@ -0,0 +1,446 @@
+/*
+ * Copyright (c) 2019, STMicroelectronics - All Rights Reserved
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <assert.h>
+#include <errno.h>
+#include <stddef.h>
+
+#include <platform_def.h>
+
+#include <common/debug.h>
+#include <drivers/delay_timer.h>
+#include <drivers/raw_nand.h>
+#include <lib/utils.h>
+
+#define ONFI_SIGNATURE_ADDR	0x20U
+
+/* CRC calculation */
+#define CRC_POLYNOM		0x8005U
+#define CRC_INIT_VALUE		0x4F4EU
+
+/* Status register */
+#define NAND_STATUS_READY	BIT(6)
+
+#define SZ_128M			0x08000000U
+#define SZ_512			0x200U
+
+static struct rawnand_device rawnand_dev;
+
+#pragma weak plat_get_raw_nand_data
+int plat_get_raw_nand_data(struct rawnand_device *device)
+{
+	return 0;
+}
+
+static int nand_send_cmd(uint8_t cmd, unsigned int tim)
+{
+	struct nand_req req;
+
+	zeromem(&req, sizeof(struct nand_req));
+	req.nand = rawnand_dev.nand_dev;
+	req.type = NAND_REQ_CMD | cmd;
+	req.inst_delay = tim;
+
+	return rawnand_dev.ops->exec(&req);
+}
+
+static int nand_send_addr(uint8_t addr, unsigned int tim)
+{
+	struct nand_req req;
+
+	zeromem(&req, sizeof(struct nand_req));
+	req.nand = rawnand_dev.nand_dev;
+	req.type = NAND_REQ_ADDR;
+	req.addr = &addr;
+	req.inst_delay = tim;
+
+	return rawnand_dev.ops->exec(&req);
+}
+
+static int nand_send_wait(unsigned int delay, unsigned int tim)
+{
+	struct nand_req req;
+
+	zeromem(&req, sizeof(struct nand_req));
+	req.nand = rawnand_dev.nand_dev;
+	req.type = NAND_REQ_WAIT;
+	req.inst_delay = tim;
+	req.delay_ms = delay;
+
+	return rawnand_dev.ops->exec(&req);
+}
+
+
+static int nand_read_data(uint8_t *data, unsigned int length, bool use_8bit)
+{
+	struct nand_req req;
+
+	zeromem(&req, sizeof(struct nand_req));
+	req.nand = rawnand_dev.nand_dev;
+	req.type = NAND_REQ_DATAIN | (use_8bit ? NAND_REQ_BUS_WIDTH_8 : 0U);
+	req.addr = data;
+	req.length = length;
+
+	return rawnand_dev.ops->exec(&req);
+}
+
+int nand_change_read_column_cmd(unsigned int offset, uintptr_t buffer,
+				unsigned int len)
+{
+	int ret;
+	uint8_t addr[2];
+	unsigned int i;
+
+	ret = nand_send_cmd(NAND_CMD_CHANGE_1ST, 0U);
+	if (ret !=  0) {
+		return ret;
+	}
+
+	if (rawnand_dev.nand_dev->buswidth == NAND_BUS_WIDTH_16) {
+		offset /= 2U;
+	}
+
+	addr[0] = offset;
+	addr[1] = offset >> 8;
+
+	for (i = 0; i < 2U; i++) {
+		ret = nand_send_addr(addr[i], 0U);
+		if (ret !=  0) {
+			return ret;
+		}
+	}
+
+	ret = nand_send_cmd(NAND_CMD_CHANGE_2ND, NAND_TCCS_MIN);
+	if (ret !=  0) {
+		return ret;
+	}
+
+	return nand_read_data((uint8_t *)buffer, len, false);
+}
+
+int nand_read_page_cmd(unsigned int page, unsigned int offset,
+		       uintptr_t buffer, unsigned int len)
+{
+	uint8_t addr[5];
+	uint8_t i = 0U;
+	uint8_t j;
+	int ret;
+
+	VERBOSE(">%s page %u offset %u buffer 0x%lx\n", __func__, page, offset,
+		buffer);
+
+	if (rawnand_dev.nand_dev->buswidth == NAND_BUS_WIDTH_16) {
+		offset /= 2U;
+	}
+
+	addr[i++] = offset;
+	addr[i++] = offset >> 8;
+
+	addr[i++] = page;
+	addr[i++] = page >> 8;
+	if (rawnand_dev.nand_dev->size > SZ_128M) {
+		addr[i++] = page >> 16;
+	}
+
+	ret = nand_send_cmd(NAND_CMD_READ_1ST, 0U);
+	if (ret != 0) {
+		return ret;
+	}
+
+	for (j = 0U; j < i; j++) {
+		ret = nand_send_addr(addr[j], 0U);
+		if (ret != 0) {
+			return ret;
+		}
+	}
+
+	ret = nand_send_cmd(NAND_CMD_READ_2ND, NAND_TWB_MAX);
+	if (ret != 0) {
+		return ret;
+	}
+
+	ret = nand_send_wait(PSEC_TO_MSEC(NAND_TR_MAX), NAND_TRR_MIN);
+	if (ret != 0) {
+		return ret;
+	}
+
+	if (buffer != 0U) {
+		ret = nand_read_data((uint8_t *)buffer, len, false);
+	}
+
+	return ret;
+}
+
+static int nand_status(uint8_t *status)
+{
+	int ret;
+
+	ret = nand_send_cmd(NAND_CMD_STATUS, NAND_TWHR_MIN);
+	if (ret != 0) {
+		return ret;
+	}
+
+	if (status != NULL) {
+		ret = nand_read_data(status, 1U, true);
+	}
+
+	return ret;
+}
+
+int nand_wait_ready(unsigned long delay)
+{
+	uint8_t status;
+	int ret;
+	uint64_t timeout;
+
+	/* Wait before reading status */
+	udelay(1);
+
+	ret = nand_status(NULL);
+	if (ret != 0) {
+		return ret;
+	}
+
+	timeout = timeout_init_us(delay);
+	while (!timeout_elapsed(timeout)) {
+		ret = nand_read_data(&status, 1U, true);
+		if (ret != 0) {
+			return ret;
+		}
+
+		if ((status & NAND_STATUS_READY) != 0U) {
+			return nand_send_cmd(NAND_CMD_READ_1ST, 0U);
+		}
+
+		udelay(10);
+	}
+
+	return -ETIMEDOUT;
+}
+
+#if NAND_ONFI_DETECT
+static uint16_t nand_check_crc(uint16_t crc, uint8_t *data_in,
+			       unsigned int data_len)
+{
+	uint32_t i;
+	uint32_t j;
+	uint32_t bit;
+
+	for (i = 0U; i < data_len; i++) {
+		uint8_t cur_param = *data_in++;
+
+		for (j = BIT(7); j != 0U; j >>= 1) {
+			bit = crc & BIT(15);
+			crc <<= 1;
+
+			if ((cur_param & j) != 0U) {
+				bit ^= BIT(15);
+			}
+
+			if (bit != 0U) {
+				crc ^= CRC_POLYNOM;
+			}
+		}
+
+		crc &= GENMASK(15, 0);
+	}
+
+	return crc;
+}
+
+static int nand_read_id(uint8_t addr, uint8_t *id, unsigned int size)
+{
+	int ret;
+
+	ret = nand_send_cmd(NAND_CMD_READID, 0U);
+	if (ret !=  0) {
+		return ret;
+	}
+
+	ret = nand_send_addr(addr, NAND_TWHR_MIN);
+	if (ret !=  0) {
+		return ret;
+	}
+
+	return nand_read_data(id, size, true);
+}
+
+static int nand_reset(void)
+{
+	int ret;
+
+	ret = nand_send_cmd(NAND_CMD_RESET, NAND_TWB_MAX);
+	if (ret != 0) {
+		return ret;
+	}
+
+	return nand_send_wait(PSEC_TO_MSEC(NAND_TRST_MAX), 0U);
+}
+
+static int nand_read_param_page(void)
+{
+	struct nand_param_page page;
+	uint8_t addr = 0U;
+	int ret;
+
+	ret = nand_send_cmd(NAND_CMD_READ_PARAM_PAGE, 0U);
+	if (ret != 0) {
+		return ret;
+	}
+
+	ret = nand_send_addr(addr, NAND_TWB_MAX);
+	if (ret != 0) {
+		return ret;
+	}
+
+	ret = nand_send_wait(PSEC_TO_MSEC(NAND_TR_MAX), NAND_TRR_MIN);
+	if (ret != 0) {
+		return ret;
+	}
+
+	ret = nand_read_data((uint8_t *)&page, sizeof(page), true);
+	if (ret != 0) {
+		return ret;
+	}
+
+	if (strncmp((char *)&page.page_sig, "ONFI", 4) != 0) {
+		WARN("Error ONFI detection\n");
+		return -EINVAL;
+	}
+
+	if (nand_check_crc(CRC_INIT_VALUE, (uint8_t *)&page, 254U) !=
+	    page.crc16) {
+		WARN("Error reading param\n");
+		return -EINVAL;
+	}
+
+	if ((page.features & ONFI_FEAT_BUS_WIDTH_16) != 0U) {
+		rawnand_dev.nand_dev->buswidth = NAND_BUS_WIDTH_16;
+	} else {
+		rawnand_dev.nand_dev->buswidth = NAND_BUS_WIDTH_8;
+	}
+
+	rawnand_dev.nand_dev->block_size = page.num_pages_per_blk *
+					   page.bytes_per_page;
+	rawnand_dev.nand_dev->page_size = page.bytes_per_page;
+	rawnand_dev.nand_dev->size = page.num_pages_per_blk *
+				     page.bytes_per_page *
+				     page.num_blk_in_lun * page.num_lun;
+
+	if (page.nb_ecc_bits != GENMASK_32(7, 0)) {
+		rawnand_dev.nand_dev->ecc.max_bit_corr = page.nb_ecc_bits;
+		rawnand_dev.nand_dev->ecc.size = SZ_512;
+	}
+
+	VERBOSE("Page size %u, block_size %u, Size %llu, ecc %u, buswidth %u\n",
+		rawnand_dev.nand_dev->page_size,
+		rawnand_dev.nand_dev->block_size, rawnand_dev.nand_dev->size,
+		rawnand_dev.nand_dev->ecc.max_bit_corr,
+		rawnand_dev.nand_dev->buswidth);
+
+	return 0;
+}
+
+static int detect_onfi(void)
+{
+	int ret;
+	char id[4];
+
+	ret = nand_reset();
+	if (ret != 0) {
+		return ret;
+	}
+
+	ret = nand_read_id(ONFI_SIGNATURE_ADDR, (uint8_t *)id, sizeof(id));
+	if (ret != 0) {
+		return ret;
+	}
+
+	if (strncmp(id, "ONFI", sizeof(id)) != 0) {
+		WARN("NAND Non ONFI detected\n");
+		return -ENODEV;
+	}
+
+	return nand_read_param_page();
+}
+#endif
+
+static int nand_mtd_block_is_bad(unsigned int block)
+{
+	unsigned int nbpages_per_block = rawnand_dev.nand_dev->block_size /
+					 rawnand_dev.nand_dev->page_size;
+	uint8_t bbm_marker[2];
+	uint8_t page;
+	int ret;
+
+	for (page = 0U; page < 2U; page++) {
+		ret = nand_read_page_cmd(block * nbpages_per_block,
+					 rawnand_dev.nand_dev->page_size,
+					 (uintptr_t)bbm_marker,
+					 sizeof(bbm_marker));
+		if (ret != 0) {
+			return ret;
+		}
+
+		if ((bbm_marker[0] != GENMASK_32(7, 0)) ||
+		    (bbm_marker[1] != GENMASK_32(7, 0))) {
+			WARN("Block %u is bad\n", block);
+			return 1;
+		}
+	}
+
+	return 0;
+}
+
+static int nand_mtd_read_page_raw(struct nand_device *nand, unsigned int page,
+				  uintptr_t buffer)
+{
+	return nand_read_page_cmd(page, 0U, buffer,
+				  rawnand_dev.nand_dev->page_size);
+}
+
+void nand_raw_ctrl_init(const struct nand_ctrl_ops *ops)
+{
+	rawnand_dev.ops = ops;
+}
+
+int nand_raw_init(unsigned long long *size, unsigned int *erase_size)
+{
+	rawnand_dev.nand_dev = get_nand_device();
+	if (rawnand_dev.nand_dev == NULL) {
+		return -EINVAL;
+	}
+
+	rawnand_dev.nand_dev->mtd_block_is_bad = nand_mtd_block_is_bad;
+	rawnand_dev.nand_dev->mtd_read_page = nand_mtd_read_page_raw;
+	rawnand_dev.nand_dev->ecc.mode = NAND_ECC_NONE;
+
+	if ((rawnand_dev.ops->setup == NULL) ||
+	    (rawnand_dev.ops->exec == NULL)) {
+		return -ENODEV;
+	}
+
+#if NAND_ONFI_DETECT
+	if (detect_onfi() != 0) {
+		WARN("Detect ONFI failed\n");
+	}
+#endif
+
+	if (plat_get_raw_nand_data(&rawnand_dev) != 0) {
+		return -EINVAL;
+	}
+
+	assert((rawnand_dev.nand_dev->page_size != 0U) &&
+	       (rawnand_dev.nand_dev->block_size != 0U) &&
+	       (rawnand_dev.nand_dev->size != 0U));
+
+	*size = rawnand_dev.nand_dev->size;
+	*erase_size = rawnand_dev.nand_dev->block_size;
+
+	rawnand_dev.ops->setup(rawnand_dev.nand_dev);
+
+	return 0;
+}
diff --git a/drivers/mtd/nand/spi_nand.c b/drivers/mtd/nand/spi_nand.c
new file mode 100644
index 000000000..d01a11963
--- /dev/null
+++ b/drivers/mtd/nand/spi_nand.c
@@ -0,0 +1,320 @@
+/*
+ * Copyright (c) 2019,  STMicroelectronics - All Rights Reserved
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <assert.h>
+#include <errno.h>
+#include <stddef.h>
+
+#include <platform_def.h>
+
+#include <common/debug.h>
+#include <drivers/delay_timer.h>
+#include <drivers/spi_nand.h>
+#include <lib/utils.h>
+
+#define SPI_NAND_MAX_ID_LEN		4U
+#define DELAY_US_400MS			400000U
+#define MACRONIX_ID			0xC2U
+
+static struct spinand_device spinand_dev;
+
+#pragma weak plat_get_spi_nand_data
+int plat_get_spi_nand_data(struct spinand_device *device)
+{
+	return 0;
+}
+
+static int spi_nand_reg(bool read_reg, uint8_t reg, uint8_t *val,
+			enum spi_mem_data_dir dir)
+{
+	struct spi_mem_op op;
+
+	zeromem(&op, sizeof(struct spi_mem_op));
+	if (read_reg) {
+		op.cmd.opcode = SPI_NAND_OP_GET_FEATURE;
+	} else {
+		op.cmd.opcode = SPI_NAND_OP_SET_FEATURE;
+	}
+
+	op.cmd.buswidth = SPI_MEM_BUSWIDTH_1_LINE;
+	op.addr.val = reg;
+	op.addr.nbytes = 1U;
+	op.addr.buswidth = SPI_MEM_BUSWIDTH_1_LINE;
+	op.data.buswidth = SPI_MEM_BUSWIDTH_1_LINE;
+	op.data.dir = dir;
+	op.data.nbytes = 1U;
+	op.data.buf = val;
+
+	return spi_mem_exec_op(&op);
+}
+
+static int spi_nand_read_reg(uint8_t reg, uint8_t *val)
+{
+	return spi_nand_reg(true, reg, val, SPI_MEM_DATA_IN);
+}
+
+static int spi_nand_write_reg(uint8_t reg, uint8_t val)
+{
+	return spi_nand_reg(false, reg, &val, SPI_MEM_DATA_OUT);
+}
+
+static int spi_nand_update_cfg(uint8_t mask, uint8_t val)
+{
+	int ret;
+	uint8_t cfg = spinand_dev.cfg_cache;
+
+	cfg &= ~mask;
+	cfg |= val;
+
+	if (cfg == spinand_dev.cfg_cache) {
+		return 0;
+	}
+
+	ret = spi_nand_write_reg(SPI_NAND_REG_CFG, cfg);
+	if (ret == 0) {
+		spinand_dev.cfg_cache = cfg;
+	}
+
+	return ret;
+}
+
+static int spi_nand_ecc_enable(bool enable)
+{
+	return spi_nand_update_cfg(SPI_NAND_CFG_ECC_EN,
+				   enable ? SPI_NAND_CFG_ECC_EN : 0U);
+}
+
+static int spi_nand_quad_enable(uint8_t manufacturer_id)
+{
+	bool enable = false;
+
+	if (manufacturer_id != MACRONIX_ID) {
+		return 0;
+	}
+
+	if (spinand_dev.spi_read_cache_op.data.buswidth ==
+	    SPI_MEM_BUSWIDTH_4_LINE) {
+		enable = true;
+	}
+
+	return spi_nand_update_cfg(SPI_NAND_CFG_QE,
+				   enable ? SPI_NAND_CFG_QE : 0U);
+}
+
+static int spi_nand_wait_ready(uint8_t *status)
+{
+	int ret;
+	uint64_t timeout = timeout_init_us(DELAY_US_400MS);
+
+	while (!timeout_elapsed(timeout)) {
+		ret = spi_nand_read_reg(SPI_NAND_REG_STATUS, status);
+		if (ret != 0) {
+			return ret;
+		}
+
+		VERBOSE("%s Status %x\n", __func__, *status);
+		if ((*status & SPI_NAND_STATUS_BUSY) == 0U) {
+			return 0;
+		}
+	}
+
+	return -ETIMEDOUT;
+}
+
+static int spi_nand_reset(void)
+{
+	struct spi_mem_op op;
+	uint8_t status;
+	int ret;
+
+	zeromem(&op, sizeof(struct spi_mem_op));
+	op.cmd.opcode = SPI_NAND_OP_RESET;
+	op.cmd.buswidth = SPI_MEM_BUSWIDTH_1_LINE;
+
+	ret = spi_mem_exec_op(&op);
+	if (ret != 0) {
+		return ret;
+	}
+
+	return spi_nand_wait_ready(&status);
+}
+
+static int spi_nand_read_id(uint8_t *id)
+{
+	struct spi_mem_op op;
+
+	zeromem(&op, sizeof(struct spi_mem_op));
+	op.cmd.opcode = SPI_NAND_OP_READ_ID;
+	op.cmd.buswidth = SPI_MEM_BUSWIDTH_1_LINE;
+	op.data.dir = SPI_MEM_DATA_IN;
+	op.data.nbytes = SPI_NAND_MAX_ID_LEN;
+	op.data.buf = id;
+	op.data.buswidth = SPI_MEM_BUSWIDTH_1_LINE;
+
+	return spi_mem_exec_op(&op);
+}
+
+static int spi_nand_load_page(unsigned int page)
+{
+	struct spi_mem_op op;
+	uint32_t block_nb = page / spinand_dev.nand_dev->block_size;
+	uint32_t page_nb = page - (block_nb * spinand_dev.nand_dev->page_size);
+	uint32_t nbpages_per_block = spinand_dev.nand_dev->block_size /
+				     spinand_dev.nand_dev->page_size;
+	uint32_t block_sh = __builtin_ctz(nbpages_per_block) + 1U;
+
+	zeromem(&op, sizeof(struct spi_mem_op));
+	op.cmd.opcode = SPI_NAND_OP_LOAD_PAGE;
+	op.cmd.buswidth = SPI_MEM_BUSWIDTH_1_LINE;
+	op.addr.val = (block_nb << block_sh) | page_nb;
+	op.addr.nbytes = 3U;
+	op.addr.buswidth = SPI_MEM_BUSWIDTH_1_LINE;
+
+	return spi_mem_exec_op(&op);
+}
+
+static int spi_nand_read_from_cache(unsigned int page, unsigned int offset,
+				    uint8_t *buffer, unsigned int len)
+{
+	uint32_t nbpages_per_block = spinand_dev.nand_dev->block_size /
+				     spinand_dev.nand_dev->page_size;
+	uint32_t block_nb = page / nbpages_per_block;
+	uint32_t page_sh = __builtin_ctz(spinand_dev.nand_dev->page_size) + 1U;
+
+	spinand_dev.spi_read_cache_op.addr.val = offset;
+
+	if ((spinand_dev.nand_dev->nb_planes > 1U) && ((block_nb % 2U) == 1U)) {
+		spinand_dev.spi_read_cache_op.addr.val |= 1U << page_sh;
+	}
+
+	spinand_dev.spi_read_cache_op.data.buf = buffer;
+	spinand_dev.spi_read_cache_op.data.nbytes = len;
+
+	return spi_mem_exec_op(&spinand_dev.spi_read_cache_op);
+}
+
+static int spi_nand_read_page(unsigned int page, unsigned int offset,
+			      uint8_t *buffer, unsigned int len,
+			      bool ecc_enabled)
+{
+	uint8_t status;
+	int ret;
+
+	ret = spi_nand_ecc_enable(ecc_enabled);
+	if (ret != 0) {
+		return ret;
+	}
+
+	ret = spi_nand_load_page(page);
+	if (ret != 0) {
+		return ret;
+	}
+
+	ret = spi_nand_wait_ready(&status);
+	if (ret != 0) {
+		return ret;
+	}
+
+	ret = spi_nand_read_from_cache(page, offset, buffer, len);
+	if (ret != 0) {
+		return ret;
+	}
+
+	if (ecc_enabled && ((status & SPI_NAND_STATUS_ECC_UNCOR) != 0U)) {
+		return -EBADMSG;
+	}
+
+	return 0;
+}
+
+static int spi_nand_mtd_block_is_bad(unsigned int block)
+{
+	unsigned int nbpages_per_block = spinand_dev.nand_dev->block_size /
+					 spinand_dev.nand_dev->page_size;
+	uint8_t bbm_marker[2];
+	int ret;
+
+	ret = spi_nand_read_page(block * nbpages_per_block,
+				 spinand_dev.nand_dev->page_size,
+				 bbm_marker, sizeof(bbm_marker), false);
+	if (ret != 0) {
+		return ret;
+	}
+
+	if ((bbm_marker[0] != GENMASK_32(7, 0)) ||
+	    (bbm_marker[1] != GENMASK_32(7, 0))) {
+		WARN("Block %i is bad\n", block);
+		return 1;
+	}
+
+	return 0;
+}
+
+static int spi_nand_mtd_read_page(struct nand_device *nand, unsigned int page,
+				  uintptr_t buffer)
+{
+	return spi_nand_read_page(page, 0, (uint8_t *)buffer,
+				  spinand_dev.nand_dev->page_size, true);
+}
+
+int spi_nand_init(unsigned long long *size, unsigned int *erase_size)
+{
+	uint8_t id[SPI_NAND_MAX_ID_LEN];
+	int ret;
+
+	spinand_dev.nand_dev = get_nand_device();
+	if (spinand_dev.nand_dev == NULL) {
+		return -EINVAL;
+	}
+
+	spinand_dev.nand_dev->mtd_block_is_bad = spi_nand_mtd_block_is_bad;
+	spinand_dev.nand_dev->mtd_read_page = spi_nand_mtd_read_page;
+	spinand_dev.nand_dev->nb_planes = 1;
+
+	spinand_dev.spi_read_cache_op.cmd.opcode = SPI_NAND_OP_READ_FROM_CACHE;
+	spinand_dev.spi_read_cache_op.cmd.buswidth = SPI_MEM_BUSWIDTH_1_LINE;
+	spinand_dev.spi_read_cache_op.addr.nbytes = 2U;
+	spinand_dev.spi_read_cache_op.addr.buswidth = SPI_MEM_BUSWIDTH_1_LINE;
+	spinand_dev.spi_read_cache_op.dummy.nbytes = 1U;
+	spinand_dev.spi_read_cache_op.dummy.buswidth = SPI_MEM_BUSWIDTH_1_LINE;
+	spinand_dev.spi_read_cache_op.data.buswidth = SPI_MEM_BUSWIDTH_1_LINE;
+
+	if (plat_get_spi_nand_data(&spinand_dev) != 0) {
+		return -EINVAL;
+	}
+
+	ret = spi_nand_reset();
+	if (ret != 0) {
+		return ret;
+	}
+
+	ret = spi_nand_read_id(id);
+	if (ret != 0) {
+		return ret;
+	}
+
+	ret = spi_nand_read_reg(SPI_NAND_REG_CFG, &spinand_dev.cfg_cache);
+	if (ret != 0) {
+		return ret;
+	}
+
+	ret = spi_nand_quad_enable(id[0]);
+	if (ret != 0) {
+		return ret;
+	}
+
+	VERBOSE("SPI_NAND Detected ID 0x%x 0x%x\n", id[0], id[1]);
+
+	VERBOSE("Page size %i, Block size %i, size %lli\n",
+		spinand_dev.nand_dev->page_size,
+		spinand_dev.nand_dev->block_size,
+		spinand_dev.nand_dev->size);
+
+	*size = spinand_dev.nand_dev->size;
+	*erase_size = spinand_dev.nand_dev->block_size;
+
+	return 0;
+}
diff --git a/drivers/mtd/nor/spi_nor.c b/drivers/mtd/nor/spi_nor.c
new file mode 100644
index 000000000..22d3ae3d9
--- /dev/null
+++ b/drivers/mtd/nor/spi_nor.c
@@ -0,0 +1,387 @@
+/*
+ * Copyright (c) 2019, STMicroelectronics - All Rights Reserved
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <assert.h>
+#include <errno.h>
+#include <stddef.h>
+
+#include <common/debug.h>
+#include <drivers/delay_timer.h>
+#include <drivers/spi_nor.h>
+#include <lib/utils.h>
+
+#define SR_WIP			BIT(0)	/* Write in progress */
+#define CR_QUAD_EN_SPAN		BIT(1)	/* Spansion Quad I/O */
+#define SR_QUAD_EN_MX		BIT(6)	/* Macronix Quad I/O */
+#define FSR_READY		BIT(7)	/* Device status, 0 = Busy, 1 = Ready */
+
+/* Defined IDs for supported memories */
+#define SPANSION_ID		0x01U
+#define MACRONIX_ID		0xC2U
+#define MICRON_ID		0x2CU
+
+#define BANK_SIZE		0x1000000U
+
+#define SPI_READY_TIMEOUT_US	40000U
+
+static struct nor_device nor_dev;
+
+#pragma weak plat_get_nor_data
+int plat_get_nor_data(struct nor_device *device)
+{
+	return 0;
+}
+
+static int spi_nor_reg(uint8_t reg, uint8_t *buf, size_t len,
+		       enum spi_mem_data_dir dir)
+{
+	struct spi_mem_op op;
+
+	zeromem(&op, sizeof(struct spi_mem_op));
+	op.cmd.opcode = reg;
+	op.cmd.buswidth = SPI_MEM_BUSWIDTH_1_LINE;
+	op.data.buswidth = SPI_MEM_BUSWIDTH_1_LINE;
+	op.data.dir = dir;
+	op.data.nbytes = len;
+	op.data.buf = buf;
+
+	return spi_mem_exec_op(&op);
+}
+
+static inline int spi_nor_read_id(uint8_t *id)
+{
+	return spi_nor_reg(SPI_NOR_OP_READ_ID, id, 1U, SPI_MEM_DATA_IN);
+}
+
+static inline int spi_nor_read_cr(uint8_t *cr)
+{
+	return spi_nor_reg(SPI_NOR_OP_READ_CR, cr, 1U, SPI_MEM_DATA_IN);
+}
+
+static inline int spi_nor_read_sr(uint8_t *sr)
+{
+	return spi_nor_reg(SPI_NOR_OP_READ_SR, sr, 1U, SPI_MEM_DATA_IN);
+}
+
+static inline int spi_nor_read_fsr(uint8_t *fsr)
+{
+	return spi_nor_reg(SPI_NOR_OP_READ_FSR, fsr, 1U, SPI_MEM_DATA_IN);
+}
+
+static inline int spi_nor_write_en(void)
+{
+	return spi_nor_reg(SPI_NOR_OP_WREN, NULL, 0U, SPI_MEM_DATA_OUT);
+}
+
+/*
+ * Check if device is ready.
+ *
+ * Return 0 if ready, 1 if busy or a negative error code otherwise
+ */
+static int spi_nor_ready(void)
+{
+	uint8_t sr;
+	int ret;
+
+	ret = spi_nor_read_sr(&sr);
+	if (ret != 0) {
+		return ret;
+	}
+
+	if ((nor_dev.flags & SPI_NOR_USE_FSR) != 0U) {
+		uint8_t fsr;
+
+		ret = spi_nor_read_fsr(&fsr);
+		if (ret != 0) {
+			return ret;
+		}
+
+		return (((fsr & FSR_READY) != 0U) && ((sr & SR_WIP) == 0U)) ?
+			0 : 1;
+	}
+
+	return (((sr & SR_WIP) != 0U) ? 1 : 0);
+}
+
+static int spi_nor_wait_ready(void)
+{
+	int ret;
+	uint64_t timeout = timeout_init_us(SPI_READY_TIMEOUT_US);
+
+	while (!timeout_elapsed(timeout)) {
+		ret = spi_nor_ready();
+		if (ret <= 0) {
+			return ret;
+		}
+	}
+
+	return -ETIMEDOUT;
+}
+
+static int spi_nor_macronix_quad_enable(void)
+{
+	uint8_t sr;
+	int ret;
+
+	ret = spi_nor_read_sr(&sr);
+	if (ret != 0) {
+		return ret;
+	}
+
+	if ((sr & SR_QUAD_EN_MX) == 0U) {
+		return 0;
+	}
+
+	ret = spi_nor_write_en();
+	if (ret != 0) {
+		return ret;
+	}
+
+	sr |= SR_QUAD_EN_MX;
+	ret = spi_nor_reg(SPI_NOR_OP_WRSR, &sr, 1, SPI_MEM_DATA_OUT);
+	if (ret != 0) {
+		return ret;
+	}
+
+	ret = spi_nor_wait_ready();
+	if (ret != 0) {
+		return ret;
+	}
+
+	ret = spi_nor_read_sr(&sr);
+	if ((ret != 0) || ((sr & SR_QUAD_EN_MX) == 0U)) {
+		return -EINVAL;
+	}
+
+	return 0;
+}
+
+static int spi_nor_write_sr_cr(uint8_t *sr_cr)
+{
+	int ret;
+
+	ret = spi_nor_write_en();
+	if (ret != 0) {
+		return ret;
+	}
+
+	ret = spi_nor_reg(SPI_NOR_OP_WRSR, sr_cr, 2, SPI_MEM_DATA_OUT);
+	if (ret != 0) {
+		return -EINVAL;
+	}
+
+	ret = spi_nor_wait_ready();
+	if (ret != 0) {
+		return ret;
+	}
+
+	return 0;
+}
+
+static int spi_nor_quad_enable(void)
+{
+	uint8_t sr_cr[2];
+	int ret;
+
+	ret = spi_nor_read_cr(&sr_cr[1]);
+	if (ret != 0) {
+		return ret;
+	}
+
+	if ((sr_cr[1] & CR_QUAD_EN_SPAN) != 0U) {
+		return 0;
+	}
+
+	sr_cr[1] |= CR_QUAD_EN_SPAN;
+	ret = spi_nor_read_sr(&sr_cr[0]);
+	if (ret != 0) {
+		return ret;
+	}
+
+	ret = spi_nor_write_sr_cr(sr_cr);
+	if (ret != 0) {
+		return ret;
+	}
+
+	ret = spi_nor_read_cr(&sr_cr[1]);
+	if ((ret != 0) || ((sr_cr[1] & CR_QUAD_EN_SPAN) == 0U)) {
+		return -EINVAL;
+	}
+
+	return 0;
+}
+
+static int spi_nor_clean_bar(void)
+{
+	int ret;
+
+	if (nor_dev.selected_bank == 0U) {
+		return 0;
+	}
+
+	nor_dev.selected_bank = 0U;
+
+	ret = spi_nor_write_en();
+	if (ret != 0) {
+		return ret;
+	}
+
+	return spi_nor_reg(nor_dev.bank_write_cmd, &nor_dev.selected_bank,
+			   1, SPI_MEM_DATA_OUT);
+}
+
+static int spi_nor_write_bar(uint32_t offset)
+{
+	uint8_t selected_bank = offset / BANK_SIZE;
+	int ret;
+
+	if (selected_bank == nor_dev.selected_bank) {
+		return 0;
+	}
+
+	ret = spi_nor_write_en();
+	if (ret != 0) {
+		return ret;
+	}
+
+	ret = spi_nor_reg(nor_dev.bank_write_cmd, &selected_bank,
+			  1, SPI_MEM_DATA_OUT);
+	if (ret != 0) {
+		return ret;
+	}
+
+	nor_dev.selected_bank = selected_bank;
+
+	return 0;
+}
+
+static int spi_nor_read_bar(void)
+{
+	uint8_t selected_bank = 0;
+	int ret;
+
+	ret = spi_nor_reg(nor_dev.bank_read_cmd, &selected_bank,
+			  1, SPI_MEM_DATA_IN);
+	if (ret != 0) {
+		return ret;
+	}
+
+	nor_dev.selected_bank = selected_bank;
+
+	return 0;
+}
+
+int spi_nor_read(unsigned int offset, uintptr_t buffer, size_t length,
+		 size_t *length_read)
+{
+	size_t remain_len;
+	int ret;
+
+	*length_read = 0;
+	nor_dev.read_op.addr.val = offset;
+	nor_dev.read_op.data.buf = (void *)buffer;
+
+	VERBOSE("%s offset %i length %zu\n", __func__, offset, length);
+
+	while (length != 0U) {
+		if ((nor_dev.flags & SPI_NOR_USE_BANK) != 0U) {
+			ret = spi_nor_write_bar(nor_dev.read_op.addr.val);
+			if (ret != 0) {
+				return ret;
+			}
+
+			remain_len = (BANK_SIZE * (nor_dev.selected_bank + 1)) -
+				nor_dev.read_op.addr.val;
+			nor_dev.read_op.data.nbytes = MIN(length, remain_len);
+		} else {
+			nor_dev.read_op.data.nbytes = length;
+		}
+
+		ret = spi_mem_exec_op(&nor_dev.read_op);
+		if (ret != 0) {
+			spi_nor_clean_bar();
+			return ret;
+		}
+
+		length -= nor_dev.read_op.data.nbytes;
+		nor_dev.read_op.addr.val += nor_dev.read_op.data.nbytes;
+		nor_dev.read_op.data.buf += nor_dev.read_op.data.nbytes;
+		*length_read += nor_dev.read_op.data.nbytes;
+	}
+
+	if ((nor_dev.flags & SPI_NOR_USE_BANK) != 0U) {
+		ret = spi_nor_clean_bar();
+		if (ret != 0) {
+			return ret;
+		}
+	}
+
+	return 0;
+}
+
+int spi_nor_init(unsigned long long *size, unsigned int *erase_size)
+{
+	int ret = 0;
+	uint8_t id;
+
+	/* Default read command used */
+	nor_dev.read_op.cmd.opcode = SPI_NOR_OP_READ;
+	nor_dev.read_op.cmd.buswidth = SPI_MEM_BUSWIDTH_1_LINE;
+	nor_dev.read_op.addr.nbytes = 3U;
+	nor_dev.read_op.addr.buswidth = SPI_MEM_BUSWIDTH_1_LINE;
+	nor_dev.read_op.data.buswidth = SPI_MEM_BUSWIDTH_1_LINE;
+	nor_dev.read_op.data.dir = SPI_MEM_DATA_IN;
+
+	if (plat_get_nor_data(&nor_dev) != 0) {
+		return -EINVAL;
+	}
+
+	assert(nor_dev.size != 0);
+
+	if (nor_dev.size > BANK_SIZE) {
+		nor_dev.flags |= SPI_NOR_USE_BANK;
+	}
+
+	*size = nor_dev.size;
+
+	ret = spi_nor_read_id(&id);
+	if (ret != 0) {
+		return ret;
+	}
+
+	if ((nor_dev.flags & SPI_NOR_USE_BANK) != 0U) {
+		switch (id) {
+		case SPANSION_ID:
+			nor_dev.bank_read_cmd = SPINOR_OP_BRRD;
+			nor_dev.bank_write_cmd = SPINOR_OP_BRWR;
+			break;
+		default:
+			nor_dev.bank_read_cmd = SPINOR_OP_RDEAR;
+			nor_dev.bank_write_cmd = SPINOR_OP_WREAR;
+			break;
+		}
+	}
+
+	if (nor_dev.read_op.data.buswidth == 4U) {
+		switch (id) {
+		case MACRONIX_ID:
+			WARN("Enable Macronix quad support\n");
+			ret = spi_nor_macronix_quad_enable();
+			break;
+		case MICRON_ID:
+			break;
+		default:
+			ret = spi_nor_quad_enable();
+			break;
+		}
+	}
+
+	if ((ret == 0) && ((nor_dev.flags & SPI_NOR_USE_BANK) != 0U)) {
+		ret = spi_nor_read_bar();
+	}
+
+	return ret;
+}
diff --git a/drivers/mtd/spi-mem/spi_mem.c b/drivers/mtd/spi-mem/spi_mem.c
new file mode 100644
index 000000000..63ea7699b
--- /dev/null
+++ b/drivers/mtd/spi-mem/spi_mem.c
@@ -0,0 +1,288 @@
+/*
+ * Copyright (c) 2019, STMicroelectronics - All Rights Reserved
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <assert.h>
+
+#include <libfdt.h>
+
+#include <drivers/spi_mem.h>
+#include <lib/utils_def.h>
+
+#define SPI_MEM_DEFAULT_SPEED_HZ 100000U
+
+/*
+ * struct spi_slave - Representation of a SPI slave.
+ *
+ * @max_hz:		Maximum speed for this slave in Hertz.
+ * @cs:			ID of the chip select connected to the slave.
+ * @mode:		SPI mode to use for this slave (see SPI mode flags).
+ * @ops:		Ops defined by the bus.
+ */
+struct spi_slave {
+	unsigned int max_hz;
+	unsigned int cs;
+	unsigned int mode;
+	const struct spi_bus_ops *ops;
+};
+
+static struct spi_slave spi_slave;
+
+static bool spi_mem_check_buswidth_req(uint8_t buswidth, bool tx)
+{
+	switch (buswidth) {
+	case 1U:
+		return true;
+
+	case 2U:
+		if ((tx && (spi_slave.mode & (SPI_TX_DUAL | SPI_TX_QUAD)) !=
+		     0U) ||
+		    (!tx && (spi_slave.mode & (SPI_RX_DUAL | SPI_RX_QUAD)) !=
+		     0U)) {
+			return true;
+		}
+		break;
+
+	case 4U:
+		if ((tx && (spi_slave.mode & SPI_TX_QUAD) != 0U) ||
+		    (!tx && (spi_slave.mode & SPI_RX_QUAD) != 0U)) {
+			return true;
+		}
+		break;
+
+	default:
+		break;
+	}
+
+	return false;
+}
+
+static bool spi_mem_supports_op(const struct spi_mem_op *op)
+{
+	if (!spi_mem_check_buswidth_req(op->cmd.buswidth, true)) {
+		return false;
+	}
+
+	if ((op->addr.nbytes != 0U) &&
+	    !spi_mem_check_buswidth_req(op->addr.buswidth, true)) {
+		return false;
+	}
+
+	if ((op->dummy.nbytes != 0U) &&
+	    !spi_mem_check_buswidth_req(op->dummy.buswidth, true)) {
+		return false;
+	}
+
+	if ((op->data.nbytes != 0U) &&
+	    !spi_mem_check_buswidth_req(op->data.buswidth,
+				       op->data.dir == SPI_MEM_DATA_OUT)) {
+		return false;
+	}
+
+	return true;
+}
+
+static int spi_mem_set_speed_mode(void)
+{
+	const struct spi_bus_ops *ops = spi_slave.ops;
+	int ret;
+
+	ret = ops->set_speed(spi_slave.max_hz);
+	if (ret != 0) {
+		VERBOSE("Cannot set speed (err=%d)\n", ret);
+		return ret;
+	}
+
+	ret = ops->set_mode(spi_slave.mode);
+	if (ret != 0) {
+		VERBOSE("Cannot set mode (err=%d)\n", ret);
+		return ret;
+	}
+
+	return 0;
+}
+
+static int spi_mem_check_bus_ops(const struct spi_bus_ops *ops)
+{
+	bool error = false;
+
+	if (ops->claim_bus == NULL) {
+		VERBOSE("Ops claim bus is not defined\n");
+		error = true;
+	}
+
+	if (ops->release_bus == NULL) {
+		VERBOSE("Ops release bus is not defined\n");
+		error = true;
+	}
+
+	if (ops->exec_op == NULL) {
+		VERBOSE("Ops exec op is not defined\n");
+		error = true;
+	}
+
+	if (ops->set_speed == NULL) {
+		VERBOSE("Ops set speed is not defined\n");
+		error = true;
+	}
+
+	if (ops->set_mode == NULL) {
+		VERBOSE("Ops set mode is not defined\n");
+		error = true;
+	}
+
+	return error ? -EINVAL : 0;
+}
+
+/*
+ * spi_mem_exec_op() - Execute a memory operation.
+ * @op: The memory operation to execute.
+ *
+ * This function first checks that @op is supported and then tries to execute
+ * it.
+ *
+ * Return: 0 in case of success, a negative error code otherwise.
+ */
+int spi_mem_exec_op(const struct spi_mem_op *op)
+{
+	const struct spi_bus_ops *ops = spi_slave.ops;
+	int ret;
+
+	VERBOSE("%s: cmd:%x mode:%d.%d.%d.%d addqr:%llx len:%x\n",
+		__func__, op->cmd.opcode, op->cmd.buswidth, op->addr.buswidth,
+		op->dummy.buswidth, op->data.buswidth,
+		op->addr.val, op->data.nbytes);
+
+	if (!spi_mem_supports_op(op)) {
+		WARN("Error in spi_mem_support\n");
+		return -ENOTSUP;
+	}
+
+	ret = ops->claim_bus(spi_slave.cs);
+	if (ret != 0) {
+		WARN("Error claim_bus\n");
+		return ret;
+	}
+
+	ret = ops->exec_op(op);
+
+	ops->release_bus();
+
+	return ret;
+}
+
+/*
+ * spi_mem_init_slave() - SPI slave device initialization.
+ * @fdt: Pointer to the device tree blob.
+ * @bus_node: Offset of the bus node.
+ * @ops: The SPI bus ops defined.
+ *
+ * This function first checks that @ops are supported and then tries to find
+ * a SPI slave device.
+ *
+ * Return: 0 in case of success, a negative error code otherwise.
+ */
+int spi_mem_init_slave(void *fdt, int bus_node, const struct spi_bus_ops *ops)
+{
+	int ret;
+	int mode = 0;
+	int nchips = 0;
+	int bus_subnode = 0;
+	const fdt32_t *cuint = NULL;
+
+	ret = spi_mem_check_bus_ops(ops);
+	if (ret != 0) {
+		return ret;
+	}
+
+	fdt_for_each_subnode(bus_subnode, fdt, bus_node) {
+		nchips++;
+	}
+
+	if (nchips != 1) {
+		ERROR("Only one SPI device is currently supported\n");
+		return -EINVAL;
+	}
+
+	fdt_for_each_subnode(bus_subnode, fdt, bus_node) {
+		/* Get chip select */
+		cuint = fdt_getprop(fdt, bus_subnode, "reg", NULL);
+		if (cuint == NULL) {
+			ERROR("Chip select not well defined\n");
+			return -EINVAL;
+		}
+		spi_slave.cs = fdt32_to_cpu(*cuint);
+
+		/* Get max slave frequency */
+		spi_slave.max_hz = SPI_MEM_DEFAULT_SPEED_HZ;
+		cuint = fdt_getprop(fdt, bus_subnode,
+				    "spi-max-frequency", NULL);
+		if (cuint != NULL) {
+			spi_slave.max_hz = fdt32_to_cpu(*cuint);
+		}
+
+		/* Get mode */
+		if ((fdt_getprop(fdt, bus_subnode, "spi-cpol", NULL)) != NULL) {
+			mode |= SPI_CPOL;
+		}
+		if ((fdt_getprop(fdt, bus_subnode, "spi-cpha", NULL)) != NULL) {
+			mode |= SPI_CPHA;
+		}
+		if ((fdt_getprop(fdt, bus_subnode, "spi-cs-high", NULL)) !=
+		    NULL) {
+			mode |= SPI_CS_HIGH;
+		}
+		if ((fdt_getprop(fdt, bus_subnode, "spi-3wire", NULL)) !=
+		    NULL) {
+			mode |= SPI_3WIRE;
+		}
+		if ((fdt_getprop(fdt, bus_subnode, "spi-half-duplex", NULL)) !=
+		    NULL) {
+			mode |= SPI_PREAMBLE;
+		}
+
+		/* Get dual/quad mode */
+		cuint = fdt_getprop(fdt, bus_subnode, "spi-tx-bus-width", NULL);
+		if (cuint != NULL) {
+			switch (fdt32_to_cpu(*cuint)) {
+			case 1U:
+				break;
+			case 2U:
+				mode |= SPI_TX_DUAL;
+				break;
+			case 4U:
+				mode |= SPI_TX_QUAD;
+				break;
+			default:
+				WARN("spi-tx-bus-width %d not supported\n",
+				     fdt32_to_cpu(*cuint));
+				return -EINVAL;
+			}
+		}
+
+		cuint = fdt_getprop(fdt, bus_subnode, "spi-rx-bus-width", NULL);
+		if (cuint != NULL) {
+			switch (fdt32_to_cpu(*cuint)) {
+			case 1U:
+				break;
+			case 2U:
+				mode |= SPI_RX_DUAL;
+				break;
+			case 4U:
+				mode |= SPI_RX_QUAD;
+				break;
+			default:
+				WARN("spi-rx-bus-width %d not supported\n",
+				     fdt32_to_cpu(*cuint));
+				return -EINVAL;
+			}
+		}
+
+		spi_slave.mode = mode;
+		spi_slave.ops = ops;
+	}
+
+	return spi_mem_set_speed_mode();
+}
diff --git a/drivers/partition/gpt.c b/drivers/partition/gpt.c
index 4577f06a2..1b804deef 100644
--- a/drivers/partition/gpt.c
+++ b/drivers/partition/gpt.c
@@ -52,9 +52,10 @@ int parse_gpt_entry(gpt_entry_t *gpt_entry, partition_entry_t *entry)
 	if (result != 0) {
 		return result;
 	}
-	entry->start = (uint64_t)gpt_entry->first_lba * PARTITION_BLOCK_SIZE;
+	entry->start = (uint64_t)gpt_entry->first_lba *
+		       PLAT_PARTITION_BLOCK_SIZE;
 	entry->length = (uint64_t)(gpt_entry->last_lba -
 				   gpt_entry->first_lba + 1) *
-			PARTITION_BLOCK_SIZE;
+			PLAT_PARTITION_BLOCK_SIZE;
 	return 0;
 }
diff --git a/drivers/partition/partition.c b/drivers/partition/partition.c
index 7fdbf5385..68133eaf4 100644
--- a/drivers/partition/partition.c
+++ b/drivers/partition/partition.c
@@ -15,7 +15,7 @@
 #include <drivers/partition/mbr.h>
 #include <plat/common/platform.h>
 
-static uint8_t mbr_sector[PARTITION_BLOCK_SIZE];
+static uint8_t mbr_sector[PLAT_PARTITION_BLOCK_SIZE];
 static partition_entry_list_t list;
 
 #if LOG_LEVEL >= LOG_LEVEL_VERBOSE
@@ -57,15 +57,15 @@ static int load_mbr_header(uintptr_t image_handle, mbr_entry_t *mbr_entry)
 		return result;
 	}
 	result = io_read(image_handle, (uintptr_t)&mbr_sector,
-			 PARTITION_BLOCK_SIZE, &bytes_read);
+			 PLAT_PARTITION_BLOCK_SIZE, &bytes_read);
 	if (result != 0) {
 		WARN("Failed to read data (%i)\n", result);
 		return result;
 	}
 
 	/* Check MBR boot signature. */
-	if ((mbr_sector[PARTITION_BLOCK_SIZE - 2] != MBR_SIGNATURE_FIRST) ||
-	    (mbr_sector[PARTITION_BLOCK_SIZE - 1] != MBR_SIGNATURE_SECOND)) {
+	if ((mbr_sector[LEGACY_PARTITION_BLOCK_SIZE - 2] != MBR_SIGNATURE_FIRST) ||
+	    (mbr_sector[LEGACY_PARTITION_BLOCK_SIZE - 1] != MBR_SIGNATURE_SECOND)) {
 		return -ENOENT;
 	}
 	offset = (uintptr_t)&mbr_sector + MBR_PRIMARY_ENTRY_OFFSET;
@@ -120,15 +120,15 @@ static int load_mbr_entry(uintptr_t image_handle, mbr_entry_t *mbr_entry,
 		return result;
 	}
 	result = io_read(image_handle, (uintptr_t)&mbr_sector,
-			 PARTITION_BLOCK_SIZE, &bytes_read);
+			 PLAT_PARTITION_BLOCK_SIZE, &bytes_read);
 	if (result != 0) {
 		WARN("Failed to read data (%i)\n", result);
 		return result;
 	}
 
 	/* Check MBR boot signature. */
-	if ((mbr_sector[PARTITION_BLOCK_SIZE - 2] != MBR_SIGNATURE_FIRST) ||
-	    (mbr_sector[PARTITION_BLOCK_SIZE - 1] != MBR_SIGNATURE_SECOND)) {
+	if ((mbr_sector[LEGACY_PARTITION_BLOCK_SIZE - 2] != MBR_SIGNATURE_FIRST) ||
+	    (mbr_sector[LEGACY_PARTITION_BLOCK_SIZE - 1] != MBR_SIGNATURE_SECOND)) {
 		return -ENOENT;
 	}
 	offset = (uintptr_t)&mbr_sector +
diff --git a/drivers/renesas/rcar/ddr/boot_init_dram.h b/drivers/renesas/rcar/ddr/boot_init_dram.h
new file mode 100644
index 000000000..ac237b2ef
--- /dev/null
+++ b/drivers/renesas/rcar/ddr/boot_init_dram.h
@@ -0,0 +1,18 @@
+/*
+ * Copyright (c) 2018-2019, Renesas Electronics Corporation. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef BOOT_INIT_DRAM_H
+#define BOOT_INIT_DRAM_H
+
+extern int32_t rcar_dram_init(void);
+
+#define INITDRAM_OK		0
+#define INITDRAM_NG		0xffffffff
+#define INITDRAM_ERR_I		0xffffffff
+#define INITDRAM_ERR_O		0xfffffffe
+#define INITDRAM_ERR_T		0xfffffff0
+
+#endif /* BOOT_INIT_DRAM_H */
diff --git a/drivers/renesas/rcar/ddr/ddr.mk b/drivers/renesas/rcar/ddr/ddr.mk
new file mode 100644
index 000000000..c26993d00
--- /dev/null
+++ b/drivers/renesas/rcar/ddr/ddr.mk
@@ -0,0 +1,17 @@
+#
+# Copyright (c) 2015-2018, Renesas Electronics Corporation. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+
+ifeq (${RCAR_LSI},${RCAR_E3})
+    include drivers/renesas/rcar/ddr/ddr_a/ddr_a.mk
+    BL2_SOURCES += drivers/renesas/rcar/ddr/dram_sub_func.c
+else ifeq (${RCAR_LSI},${RCAR_D3})
+    include drivers/renesas/rcar/ddr/ddr_a/ddr_a.mk
+else ifeq (${RCAR_LSI},${RCAR_V3M})
+    include drivers/renesas/rcar/ddr/ddr_a/ddr_a.mk
+else
+    include drivers/renesas/rcar/ddr/ddr_b/ddr_b.mk
+    BL2_SOURCES += drivers/renesas/rcar/ddr/dram_sub_func.c
+endif
diff --git a/drivers/renesas/rcar/ddr/ddr_a/boot_init_dram_regdef.h b/drivers/renesas/rcar/ddr/ddr_a/boot_init_dram_regdef.h
new file mode 100644
index 000000000..0f89b4350
--- /dev/null
+++ b/drivers/renesas/rcar/ddr/ddr_a/boot_init_dram_regdef.h
@@ -0,0 +1,8 @@
+/*
+ * Copyright (c) 2015-2019, Renesas Electronics Corporation
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include "../ddr_regs.h"
diff --git a/drivers/renesas/rcar/ddr/ddr_a/ddr_a.mk b/drivers/renesas/rcar/ddr/ddr_a/ddr_a.mk
new file mode 100644
index 000000000..7882558d0
--- /dev/null
+++ b/drivers/renesas/rcar/ddr/ddr_a/ddr_a.mk
@@ -0,0 +1,13 @@
+#
+# Copyright (c) 2015-2018, Renesas Electronics Corporation. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+
+ifeq (${RCAR_LSI},${RCAR_E3})
+BL2_SOURCES += drivers/renesas/rcar/ddr/ddr_a/ddr_init_e3.c
+else ifeq (${RCAR_LSI},${RCAR_D3})
+BL2_SOURCES += drivers/renesas/rcar/ddr/ddr_a/ddr_init_d3.c
+else
+BL2_SOURCES += drivers/renesas/rcar/ddr/ddr_a/ddr_init_v3m.c
+endif
diff --git a/drivers/renesas/rcar/ddr/ddr_a/ddr_init_d3.c b/drivers/renesas/rcar/ddr/ddr_a/ddr_init_d3.c
new file mode 100644
index 000000000..a49510ed5
--- /dev/null
+++ b/drivers/renesas/rcar/ddr/ddr_a/ddr_init_d3.c
@@ -0,0 +1,699 @@
+/*
+ * Copyright (c) 2015-2019, Renesas Electronics Corporation.
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <stdint.h>
+#include <lib/mmio.h>
+#include <common/debug.h>
+#include "rcar_def.h"
+#include "../ddr_regs.h"
+
+#define RCAR_DDR_VERSION	"rev.0.01"
+
+#if RCAR_LSI != RCAR_D3
+#error "Don't have DDR initialize routine."
+#endif
+
+static void init_ddr_d3_1866(void)
+{
+	uint32_t i, r2, r3, r5, r6, r7, r12;
+
+	mmio_write_32(DBSC_DBSYSCNT0, 0x00001234);
+	mmio_write_32(DBSC_DBKIND, 0x00000007);
+	mmio_write_32(DBSC_DBMEMCONF_0_0, 0x0f030a01);
+	mmio_write_32(DBSC_DBPHYCONF0, 0x00000001);
+	mmio_write_32(DBSC_DBTR0, 0x0000000D);
+	mmio_write_32(DBSC_DBTR1, 0x00000009);
+	mmio_write_32(DBSC_DBTR2, 0x00000000);
+	mmio_write_32(DBSC_DBTR3, 0x0000000D);
+	mmio_write_32(DBSC_DBTR4, 0x000D000D);
+	mmio_write_32(DBSC_DBTR5, 0x0000002D);
+	mmio_write_32(DBSC_DBTR6, 0x00000020);
+	mmio_write_32(DBSC_DBTR7, 0x00060006);
+	mmio_write_32(DBSC_DBTR8, 0x00000021);
+	mmio_write_32(DBSC_DBTR9, 0x00000007);
+	mmio_write_32(DBSC_DBTR10, 0x0000000E);
+	mmio_write_32(DBSC_DBTR11, 0x0000000C);
+	mmio_write_32(DBSC_DBTR12, 0x00140014);
+	mmio_write_32(DBSC_DBTR13, 0x000000F2);
+	mmio_write_32(DBSC_DBTR14, 0x00170006);
+	mmio_write_32(DBSC_DBTR15, 0x00060005);
+	mmio_write_32(DBSC_DBTR16, 0x09210507);
+	mmio_write_32(DBSC_DBTR17, 0x040E0000);
+	mmio_write_32(DBSC_DBTR18, 0x00000200);
+	mmio_write_32(DBSC_DBTR19, 0x012B004B);
+	mmio_write_32(DBSC_DBTR20, 0x020000FB);
+	mmio_write_32(DBSC_DBTR21, 0x00040004);
+	mmio_write_32(DBSC_DBBL, 0x00000000);
+	mmio_write_32(DBSC_DBODT0, 0x00000001);
+	mmio_write_32(DBSC_DBADJ0, 0x00000001);
+	mmio_write_32(DBSC_DBSYSCONF1, 0x00000002);
+	mmio_write_32(DBSC_DBDFICNT_0, 0x00000010);
+	mmio_write_32(DBSC_DBBCAMDIS, 0x00000001);
+	mmio_write_32(DBSC_DBSCHRW1, 0x00000046);
+	mmio_write_32(DBSC_SCFCTST0, 0x0D020D04);
+	mmio_write_32(DBSC_SCFCTST1, 0x0306040C);
+
+	mmio_write_32(DBSC_DBPDLK_0, 0x0000A55A);
+	mmio_write_32(DBSC_DBCMD, 0x01000001);
+	mmio_write_32(DBSC_DBCMD, 0x08000000);
+	mmio_write_32(DBSC_DBPDRGA_0, 0x00000001);
+	mmio_write_32(DBSC_DBPDRGD_0, 0x80010000);
+	mmio_write_32(DBSC_DBPDRGA_0, 0x00000006);
+	while (!(mmio_read_32(DBSC_DBPDRGD_0) & BIT(0)))
+		;
+
+	mmio_write_32(DBSC_DBPDRGA_0, 0x00000008);
+	mmio_write_32(DBSC_DBPDRGD_0, 0x000B8000);
+	mmio_write_32(DBSC_DBPDRGA_0, 0x00000090);
+	mmio_write_32(DBSC_DBPDRGD_0, 0x04058A04);
+	mmio_write_32(DBSC_DBPDRGA_0, 0x00000091);
+	mmio_write_32(DBSC_DBPDRGD_0, 0x0007BB6B);
+	mmio_write_32(DBSC_DBPDRGA_0, 0x00000095);
+	mmio_write_32(DBSC_DBPDRGD_0, 0x0007BBAD);
+	mmio_write_32(DBSC_DBPDRGA_0, 0x00000099);
+	mmio_write_32(DBSC_DBPDRGD_0, 0x0007BB6B);
+	mmio_write_32(DBSC_DBPDRGA_0, 0x00000090);
+	mmio_write_32(DBSC_DBPDRGD_0, 0x04058A00);
+	mmio_write_32(DBSC_DBPDRGA_0, 0x00000021);
+	mmio_write_32(DBSC_DBPDRGD_0, 0x0024641E);
+	mmio_write_32(DBSC_DBPDRGA_0, 0x00000001);
+	mmio_write_32(DBSC_DBPDRGD_0, 0x00010073);
+	mmio_write_32(DBSC_DBPDRGA_0, 0x00000006);
+	while (!(mmio_read_32(DBSC_DBPDRGD_0) & BIT(0)))
+		;
+
+	mmio_write_32(DBSC_DBPDRGA_0, 0x00000090);
+	mmio_write_32(DBSC_DBPDRGD_0, 0x0C058A00);
+	mmio_write_32(DBSC_DBPDRGA_0, 0x00000090);
+	mmio_write_32(DBSC_DBPDRGD_0, 0x04058A00);
+	mmio_write_32(DBSC_DBPDRGA_0, 0x00000006);
+	while (!(mmio_read_32(DBSC_DBPDRGD_0) & BIT(0)))
+		;
+
+	mmio_write_32(DBSC_DBPDRGA_0, 0x00000003);
+	mmio_write_32(DBSC_DBPDRGD_0, 0x0780C700);
+	mmio_write_32(DBSC_DBPDRGA_0, 0x00000007);
+	while (!(mmio_read_32(DBSC_DBPDRGD_0) & BIT(30)))
+		;
+
+	mmio_write_32(DBSC_DBPDRGA_0, 0x00000004);
+	mmio_write_32(DBSC_DBPDRGD_0, 0x0A206F89);
+	mmio_write_32(DBSC_DBPDRGA_0, 0x00000022);
+	mmio_write_32(DBSC_DBPDRGD_0, 0x1000040B);
+	mmio_write_32(DBSC_DBPDRGA_0, 0x00000023);
+	mmio_write_32(DBSC_DBPDRGD_0, 0x35A00D77);
+	mmio_write_32(DBSC_DBPDRGA_0, 0x00000024);
+	mmio_write_32(DBSC_DBPDRGD_0, 0x2A8A2C28);
+	mmio_write_32(DBSC_DBPDRGA_0, 0x00000025);
+	mmio_write_32(DBSC_DBPDRGD_0, 0x30005E00);
+	mmio_write_32(DBSC_DBPDRGA_0, 0x00000026);
+	mmio_write_32(DBSC_DBPDRGD_0, 0x0014CB49);
+	mmio_write_32(DBSC_DBPDRGA_0, 0x00000027);
+	mmio_write_32(DBSC_DBPDRGD_0, 0x00000F14);
+	mmio_write_32(DBSC_DBPDRGA_0, 0x00000028);
+	mmio_write_32(DBSC_DBPDRGD_0, 0x00000046);
+	mmio_write_32(DBSC_DBPDRGA_0, 0x00000029);
+	mmio_write_32(DBSC_DBPDRGD_0, 0x000000A0);
+	mmio_write_32(DBSC_DBPDRGA_0, 0x0000002C);
+	mmio_write_32(DBSC_DBPDRGD_0, 0x81003047);
+	mmio_write_32(DBSC_DBPDRGA_0, 0x00000020);
+	mmio_write_32(DBSC_DBPDRGD_0, 0x00181884);
+	mmio_write_32(DBSC_DBPDRGA_0, 0x0000001A);
+	mmio_write_32(DBSC_DBPDRGD_0, 0x33C03C10);
+	mmio_write_32(DBSC_DBPDRGA_0, 0x00000006);
+	while (!(mmio_read_32(DBSC_DBPDRGD_0) & BIT(0)))
+		;
+
+	mmio_write_32(DBSC_DBPDRGA_0, 0x000000A7);
+	mmio_write_32(DBSC_DBPDRGD_0, 0x0D0D0D0D);
+	mmio_write_32(DBSC_DBPDRGA_0, 0x000000A8);
+	mmio_write_32(DBSC_DBPDRGD_0, 0x0D0D0D0D);
+	mmio_write_32(DBSC_DBPDRGA_0, 0x000000A9);
+	mmio_write_32(DBSC_DBPDRGD_0, 0x000D0D0D);
+	mmio_write_32(DBSC_DBPDRGA_0, 0x000000C7);
+	mmio_write_32(DBSC_DBPDRGD_0, 0x0D0D0D0D);
+	mmio_write_32(DBSC_DBPDRGA_0, 0x000000C8);
+	mmio_write_32(DBSC_DBPDRGD_0, 0x0D0D0D0D);
+	mmio_write_32(DBSC_DBPDRGA_0, 0x000000C9);
+	mmio_write_32(DBSC_DBPDRGD_0, 0x000D0D0D);
+
+	mmio_write_32(DBSC_DBPDRGA_0, 0x0000000E);
+	r2 = (mmio_read_32(DBSC_DBPDRGD_0) & 0x0000FF00) >> 0x9;
+	r3 = (r2 << 16) + (r2 << 8) + r2;
+	r6 = (r2 << 24) + (r2 << 16) + (r2 << 8) + r2;
+	mmio_write_32(DBSC_DBPDRGA_0, 0x00000011);
+	mmio_write_32(DBSC_DBPDRGD_0, r3);
+	mmio_write_32(DBSC_DBPDRGA_0, 0x00000012);
+	mmio_write_32(DBSC_DBPDRGD_0, r3);
+	mmio_write_32(DBSC_DBPDRGA_0, 0x00000016);
+	mmio_write_32(DBSC_DBPDRGD_0, r6);
+	mmio_write_32(DBSC_DBPDRGA_0, 0x00000017);
+	mmio_write_32(DBSC_DBPDRGD_0, r6);
+	mmio_write_32(DBSC_DBPDRGA_0, 0x00000018);
+	mmio_write_32(DBSC_DBPDRGD_0, r6);
+	mmio_write_32(DBSC_DBPDRGA_0, 0x00000019);
+	mmio_write_32(DBSC_DBPDRGD_0, r6);
+
+	mmio_write_32(DBSC_DBPDRGA_0, 0x00000001);
+	mmio_write_32(DBSC_DBPDRGD_0, 0x00010181);
+	mmio_write_32(DBSC_DBCMD, 0x08000001);
+	mmio_write_32(DBSC_DBPDRGA_0, 0x00000006);
+	while (!(mmio_read_32(DBSC_DBPDRGD_0) & BIT(0)))
+		;
+
+	mmio_write_32(DBSC_DBPDRGA_0, 0x00000001);
+	mmio_write_32(DBSC_DBPDRGD_0, 0x00010601);
+	mmio_write_32(DBSC_DBPDRGA_0, 0x00000006);
+	while (!(mmio_read_32(DBSC_DBPDRGD_0) & BIT(0)))
+		;
+
+	for (i = 0; i < 2; i++) {
+		mmio_write_32(DBSC_DBPDRGA_0, 0xB1 + i * 0x20);
+		r5 = (mmio_read_32(DBSC_DBPDRGD_0) & 0xFF00) >> 0x8;
+		mmio_write_32(DBSC_DBPDRGA_0, 0xB4 + i * 0x20);
+		r6 = mmio_read_32(DBSC_DBPDRGD_0) & 0xFF;
+		mmio_write_32(DBSC_DBPDRGA_0, 0xB3 + i * 0x20);
+		r7 = mmio_read_32(DBSC_DBPDRGD_0) & 0x7;
+
+		if (r6 > 0) {
+			mmio_write_32(DBSC_DBPDRGA_0, 0xB2 + i * 0x20);
+			r2 = mmio_read_32(DBSC_DBPDRGD_0) & 0xFFFFFFF8;
+
+			mmio_write_32(DBSC_DBPDRGA_0, 0xB2 + i * 0x20);
+			mmio_write_32(DBSC_DBPDRGD_0, r2 | ((r7 + 0x1) & 0x7));
+			mmio_write_32(DBSC_DBPDRGA_0, 0xB0 + i * 0x20);
+			r2 = mmio_read_32(DBSC_DBPDRGD_0) & 0xFFFFFF00;
+			mmio_write_32(DBSC_DBPDRGA_0, 0xB0 + i * 0x20);
+			mmio_write_32(DBSC_DBPDRGD_0, r2 | r6);
+		} else {
+			mmio_write_32(DBSC_DBPDRGA_0, 0xB2 + i * 0x20);
+			r2 = mmio_read_32(DBSC_DBPDRGD_0) & 0xFFFFFFF8;
+			mmio_write_32(DBSC_DBPDRGA_0, 0xB2 + i * 0x20);
+			mmio_write_32(DBSC_DBPDRGD_0, r2 | r7);
+
+			mmio_write_32(DBSC_DBPDRGA_0, 0xB0 + i * 0x20);
+			r2 = mmio_read_32(DBSC_DBPDRGD_0) & 0xFFFFFF00;
+			mmio_write_32(DBSC_DBPDRGA_0, 0xB0 + i * 0x20);
+			mmio_write_32(DBSC_DBPDRGD_0, r2 |
+						     ((r6 + (r5 << 1)) & 0xFF));
+		}
+	}
+
+	mmio_write_32(DBSC_DBPDRGA_0, 0x00000005);
+	mmio_write_32(DBSC_DBPDRGD_0, 0xC1AA00C0);
+	mmio_write_32(DBSC_DBPDRGA_0, 0x000000A0);
+	mmio_write_32(DBSC_DBPDRGD_0, 0x7C0002C5);
+	mmio_write_32(DBSC_DBPDRGA_0, 0x000000C0);
+	mmio_write_32(DBSC_DBPDRGD_0, 0x7C0002C5);
+	mmio_write_32(DBSC_DBPDRGA_0, 0x00000001);
+	mmio_write_32(DBSC_DBPDRGD_0, 0x00010801);
+	mmio_write_32(DBSC_DBPDRGA_0, 0x00000006);
+	while (!(mmio_read_32(DBSC_DBPDRGD_0) & BIT(0)))
+		;
+
+	mmio_write_32(DBSC_DBPDRGA_0, 0x00000005);
+	mmio_write_32(DBSC_DBPDRGD_0, 0xC1AA00D8);
+	mmio_write_32(DBSC_DBPDRGA_0, 0x00000001);
+	mmio_write_32(DBSC_DBPDRGD_0, 0x0001F001);
+	mmio_write_32(DBSC_DBPDRGA_0, 0x00000006);
+	while (!(mmio_read_32(DBSC_DBPDRGD_0) & BIT(0)))
+		;
+
+	mmio_write_32(DBSC_DBPDRGA_0, 0x000000AF);
+	r2 = mmio_read_32(DBSC_DBPDRGD_0);
+	mmio_write_32(DBSC_DBPDRGD_0, ((r2 + 0x1) & 0xFF) | (r2 & 0xFFFFFF00));
+	mmio_write_32(DBSC_DBPDRGA_0, 0x000000CF);
+	r2 = mmio_read_32(DBSC_DBPDRGD_0);
+	mmio_write_32(DBSC_DBPDRGD_0, ((r2 + 0x1) & 0xFF) | (r2 & 0xFFFFFF00));
+
+	mmio_write_32(DBSC_DBPDRGA_0, 0x000000A0);
+	mmio_write_32(DBSC_DBPDRGD_0, 0x7C000285);
+	mmio_write_32(DBSC_DBPDRGA_0, 0x000000C0);
+	mmio_write_32(DBSC_DBPDRGD_0, 0x7C000285);
+	mmio_write_32(DBSC_DBPDRGA_0, 0x0000002C);
+	mmio_write_32(DBSC_DBPDRGD_0, 0x81003087);
+	mmio_write_32(DBSC_DBPDRGA_0, 0x00000001);
+	mmio_write_32(DBSC_DBPDRGD_0, 0x00010401);
+	mmio_write_32(DBSC_DBPDRGA_0, 0x00000006);
+	while (!(mmio_read_32(DBSC_DBPDRGD_0) & BIT(0)))
+		;
+
+	for (i = 0; i < 2; i++) {
+		mmio_write_32(DBSC_DBPDRGA_0, 0xB1 + i * 0x20);
+		r5 = ((mmio_read_32(DBSC_DBPDRGD_0) & 0xFF00) >> 0x8);
+		mmio_write_32(DBSC_DBPDRGA_0, 0xB4 + i * 0x20);
+		r6 = mmio_read_32(DBSC_DBPDRGD_0) & 0xFF;
+
+		mmio_write_32(DBSC_DBPDRGA_0, 0xB3 + i * 0x20);
+		r7 = mmio_read_32(DBSC_DBPDRGD_0) & 0x7;
+		r12 = (r5 >> 0x2);
+
+		if (r12 < r6) {
+			mmio_write_32(DBSC_DBPDRGA_0, 0xB2 + i * 0x20);
+			r2 = mmio_read_32(DBSC_DBPDRGD_0) & 0xFFFFFFF8;
+
+			mmio_write_32(DBSC_DBPDRGA_0, 0xB2 + i * 0x20);
+			mmio_write_32(DBSC_DBPDRGD_0, r2 | ((r7 + 0x1) & 0x7));
+			mmio_write_32(DBSC_DBPDRGA_0, 0xB0 + i * 0x20);
+			r2 = mmio_read_32(DBSC_DBPDRGD_0) & 0xFFFFFF00;
+
+			mmio_write_32(DBSC_DBPDRGA_0, 0xB0 + i * 0x20);
+			mmio_write_32(DBSC_DBPDRGD_0, r2 | ((r6 - r12) & 0xFF));
+		} else {
+			mmio_write_32(DBSC_DBPDRGA_0, 0xB2 + i * 0x20);
+			r2 = mmio_read_32(DBSC_DBPDRGD_0) & 0xFFFFFFF8;
+			mmio_write_32(DBSC_DBPDRGA_0, 0xB2 + i * 0x20);
+			mmio_write_32(DBSC_DBPDRGD_0, r2 | (r7 & 0x7));
+			mmio_write_32(DBSC_DBPDRGA_0, 0xB0 + i * 0x20);
+			r2 = mmio_read_32(DBSC_DBPDRGD_0) & 0xFFFFFF00;
+			mmio_write_32(DBSC_DBPDRGA_0, 0xB0 + i * 0x20);
+			mmio_write_32(DBSC_DBPDRGD_0, r2 |
+						     ((r6 + r5 +
+						      (r5 >> 1) + r12) & 0xFF));
+		}
+	}
+
+	mmio_write_32(DBSC_DBPDRGA_0, 0x000000A0);
+	mmio_write_32(DBSC_DBPDRGD_0, 0x7C0002C5);
+	mmio_write_32(DBSC_DBPDRGA_0, 0x000000C0);
+	mmio_write_32(DBSC_DBPDRGD_0, 0x7C0002C5);
+	mmio_write_32(DBSC_DBPDRGA_0, 0x00000001);
+	mmio_write_32(DBSC_DBPDRGD_0, 0x00015001);
+	mmio_write_32(DBSC_DBPDRGA_0, 0x00000006);
+	while (!(mmio_read_32(DBSC_DBPDRGD_0) & BIT(0)))
+		;
+
+	mmio_write_32(DBSC_DBPDRGA_0, 0x00000003);
+	mmio_write_32(DBSC_DBPDRGD_0, 0x0380C700);
+	mmio_write_32(DBSC_DBPDRGA_0, 0x00000007);
+	while (mmio_read_32(DBSC_DBPDRGD_0) & BIT(30))
+		;
+	mmio_write_32(DBSC_DBPDRGA_0, 0x00000021);
+	mmio_write_32(DBSC_DBPDRGD_0, 0x0024643E);
+
+	mmio_write_32(DBSC_DBBUS0CNF1, 0x00000010);
+	mmio_write_32(DBSC_DBCALCNF, 0x0100401B);
+	mmio_write_32(DBSC_DBRFCNF1, 0x00080E23);
+	mmio_write_32(DBSC_DBRFCNF2, 0x00010000);
+	mmio_write_32(DBSC_DBDFICUPDCNF, 0x40100001);
+	mmio_write_32(DBSC_DBRFEN, 0x00000001);
+	mmio_write_32(DBSC_DBACEN, 0x00000001);
+	mmio_write_32(DBSC_DBPDLK_0, 0x00000000);
+	mmio_write_32(DBSC_DBSYSCNT0, 0x00000000);
+
+#ifdef ddr_qos_init_setting // only for non qos_init
+	mmio_write_32(DBSC_DBSYSCNT0, 0x00001234);
+	mmio_write_32(DBSC_DBCAM0CNF1, 0x00043218);
+	mmio_write_32(DBSC_DBCAM0CNF2, 0x000000F4);
+	mmio_write_32(DBSC_DBSCHCNT0, 0x000f0037);
+	mmio_write_32(DBSC_DBSCHSZ0, 0x00000001);
+	mmio_write_32(DBSC_DBSCHRW0, 0x22421111);
+	mmio_write_32(DBSC_SCFCTST2, 0x012F1123);
+	mmio_write_32(DBSC_DBSCHQOS00, 0x00000F00);
+	mmio_write_32(DBSC_DBSCHQOS01, 0x00000B00);
+	mmio_write_32(DBSC_DBSCHQOS02, 0x00000000);
+	mmio_write_32(DBSC_DBSCHQOS03, 0x00000000);
+	mmio_write_32(DBSC_DBSCHQOS40, 0x00000300);
+	mmio_write_32(DBSC_DBSCHQOS41, 0x000002F0);
+	mmio_write_32(DBSC_DBSCHQOS42, 0x00000200);
+	mmio_write_32(DBSC_DBSCHQOS43, 0x00000100);
+	mmio_write_32(DBSC_DBSCHQOS90, 0x00000300);
+	mmio_write_32(DBSC_DBSCHQOS91, 0x000002F0);
+	mmio_write_32(DBSC_DBSCHQOS92, 0x00000200);
+	mmio_write_32(DBSC_DBSCHQOS93, 0x00000100);
+	mmio_write_32(DBSC_DBSCHQOS130, 0x00000100);
+	mmio_write_32(DBSC_DBSCHQOS131, 0x000000F0);
+	mmio_write_32(DBSC_DBSCHQOS132, 0x000000A0);
+	mmio_write_32(DBSC_DBSCHQOS133, 0x00000040);
+	mmio_write_32(DBSC_DBSCHQOS140, 0x000000C0);
+	mmio_write_32(DBSC_DBSCHQOS141, 0x000000B0);
+	mmio_write_32(DBSC_DBSCHQOS142, 0x00000080);
+	mmio_write_32(DBSC_DBSCHQOS143, 0x00000040);
+	mmio_write_32(DBSC_DBSCHQOS150, 0x00000040);
+	mmio_write_32(DBSC_DBSCHQOS151, 0x00000030);
+	mmio_write_32(DBSC_DBSCHQOS152, 0x00000020);
+	mmio_write_32(DBSC_DBSCHQOS153, 0x00000010);
+	mmio_write_32(0xE67F0018, 0x00000001);
+	mmio_write_32(DBSC_DBSYSCNT0, 0x00000000);
+#endif
+}
+
+static void init_ddr_d3_1600(void)
+{
+	uint32_t i, r2, r3, r5, r6, r7, r12;
+
+	mmio_write_32(DBSC_DBSYSCNT0, 0x00001234);
+	mmio_write_32(DBSC_DBKIND, 0x00000007);
+	mmio_write_32(DBSC_DBMEMCONF_0_0, 0x0f030a01);
+	mmio_write_32(DBSC_DBPHYCONF0, 0x00000001);
+	mmio_write_32(DBSC_DBTR0, 0x0000000B);
+	mmio_write_32(DBSC_DBTR1, 0x00000008);
+	mmio_write_32(DBSC_DBTR2, 0x00000000);
+	mmio_write_32(DBSC_DBTR3, 0x0000000B);
+	mmio_write_32(DBSC_DBTR4, 0x000B000B);
+	mmio_write_32(DBSC_DBTR5, 0x00000027);
+	mmio_write_32(DBSC_DBTR6, 0x0000001C);
+	mmio_write_32(DBSC_DBTR7, 0x00060006);
+	mmio_write_32(DBSC_DBTR8, 0x00000020);
+	mmio_write_32(DBSC_DBTR9, 0x00000006);
+	mmio_write_32(DBSC_DBTR10, 0x0000000C);
+	mmio_write_32(DBSC_DBTR11, 0x0000000A);
+	mmio_write_32(DBSC_DBTR12, 0x00120012);
+	mmio_write_32(DBSC_DBTR13, 0x000000D0);
+	mmio_write_32(DBSC_DBTR14, 0x00140005);
+	mmio_write_32(DBSC_DBTR15, 0x00050004);
+	mmio_write_32(DBSC_DBTR16, 0x071F0305);
+	mmio_write_32(DBSC_DBTR17, 0x040C0000);
+	mmio_write_32(DBSC_DBTR18, 0x00000200);
+	mmio_write_32(DBSC_DBTR19, 0x01000040);
+	mmio_write_32(DBSC_DBTR20, 0x020000D8);
+	mmio_write_32(DBSC_DBTR21, 0x00040004);
+	mmio_write_32(DBSC_DBBL, 0x00000000);
+	mmio_write_32(DBSC_DBODT0, 0x00000001);
+	mmio_write_32(DBSC_DBADJ0, 0x00000001);
+	mmio_write_32(DBSC_DBSYSCONF1, 0x00000002);
+	mmio_write_32(DBSC_DBDFICNT_0, 0x00000010);
+	mmio_write_32(DBSC_DBBCAMDIS, 0x00000001);
+	mmio_write_32(DBSC_DBSCHRW1, 0x00000046);
+	mmio_write_32(DBSC_SCFCTST0, 0x0D020C04);
+	mmio_write_32(DBSC_SCFCTST1, 0x0305040C);
+
+	mmio_write_32(DBSC_DBPDLK_0, 0x0000A55A);
+	mmio_write_32(DBSC_DBCMD, 0x01000001);
+	mmio_write_32(DBSC_DBCMD, 0x08000000);
+	mmio_write_32(DBSC_DBPDRGA_0, 0x00000001);
+	mmio_write_32(DBSC_DBPDRGD_0, 0x80010000);
+	mmio_write_32(DBSC_DBPDRGA_0, 0x00000006);
+	while (!(mmio_read_32(DBSC_DBPDRGD_0) & BIT(0)))
+		;
+
+	mmio_write_32(DBSC_DBPDRGA_0, 0x00000008);
+	mmio_write_32(DBSC_DBPDRGD_0, 0x000B8000);
+	mmio_write_32(DBSC_DBPDRGA_0, 0x00000090);
+	mmio_write_32(DBSC_DBPDRGD_0, 0x04058904);
+	mmio_write_32(DBSC_DBPDRGA_0, 0x00000091);
+	mmio_write_32(DBSC_DBPDRGD_0, 0x0007BB6B);
+	mmio_write_32(DBSC_DBPDRGA_0, 0x00000095);
+	mmio_write_32(DBSC_DBPDRGD_0, 0x0007BBAD);
+	mmio_write_32(DBSC_DBPDRGA_0, 0x00000099);
+	mmio_write_32(DBSC_DBPDRGD_0, 0x0007BB6B);
+	mmio_write_32(DBSC_DBPDRGA_0, 0x00000090);
+	mmio_write_32(DBSC_DBPDRGD_0, 0x04058900);
+	mmio_write_32(DBSC_DBPDRGA_0, 0x00000021);
+	mmio_write_32(DBSC_DBPDRGD_0, 0x0024641E);
+	mmio_write_32(DBSC_DBPDRGA_0, 0x00000001);
+	mmio_write_32(DBSC_DBPDRGD_0, 0x00010073);
+	mmio_write_32(DBSC_DBPDRGA_0, 0x00000006);
+	while (!(mmio_read_32(DBSC_DBPDRGD_0) & BIT(0)))
+		;
+
+	mmio_write_32(DBSC_DBPDRGA_0, 0x00000090);
+	mmio_write_32(DBSC_DBPDRGD_0, 0x0C058900);
+	mmio_write_32(DBSC_DBPDRGA_0, 0x00000090);
+	mmio_write_32(DBSC_DBPDRGD_0, 0x04058900);
+	mmio_write_32(DBSC_DBPDRGA_0, 0x00000006);
+	while (!(mmio_read_32(DBSC_DBPDRGD_0) & BIT(0)))
+		;
+
+	mmio_write_32(DBSC_DBPDRGA_0, 0x00000003);
+	mmio_write_32(DBSC_DBPDRGD_0, 0x0780C700);
+	mmio_write_32(DBSC_DBPDRGA_0, 0x00000007);
+	while (!(mmio_read_32(DBSC_DBPDRGD_0) & BIT(30)))
+		;
+
+	mmio_write_32(DBSC_DBPDRGA_0, 0x00000004);
+	mmio_write_32(DBSC_DBPDRGD_0, 0x08C05FF0);
+	mmio_write_32(DBSC_DBPDRGA_0, 0x00000022);
+	mmio_write_32(DBSC_DBPDRGD_0, 0x1000040B);
+	mmio_write_32(DBSC_DBPDRGA_0, 0x00000023);
+	mmio_write_32(DBSC_DBPDRGD_0, 0x2D9C0B66);
+	mmio_write_32(DBSC_DBPDRGA_0, 0x00000024);
+	mmio_write_32(DBSC_DBPDRGD_0, 0x2A88C400);
+	mmio_write_32(DBSC_DBPDRGA_0, 0x00000025);
+	mmio_write_32(DBSC_DBPDRGD_0, 0x30005200);
+	mmio_write_32(DBSC_DBPDRGA_0, 0x00000026);
+	mmio_write_32(DBSC_DBPDRGD_0, 0x0014A9C9);
+	mmio_write_32(DBSC_DBPDRGA_0, 0x00000027);
+	mmio_write_32(DBSC_DBPDRGD_0, 0x00000D70);
+	mmio_write_32(DBSC_DBPDRGA_0, 0x00000028);
+	mmio_write_32(DBSC_DBPDRGD_0, 0x00000046);
+	mmio_write_32(DBSC_DBPDRGA_0, 0x00000029);
+	mmio_write_32(DBSC_DBPDRGD_0, 0x00000098);
+	mmio_write_32(DBSC_DBPDRGA_0, 0x0000002C);
+	mmio_write_32(DBSC_DBPDRGD_0, 0x81003047);
+	mmio_write_32(DBSC_DBPDRGA_0, 0x00000020);
+	mmio_write_32(DBSC_DBPDRGD_0, 0x00181884);
+	mmio_write_32(DBSC_DBPDRGA_0, 0x0000001A);
+	mmio_write_32(DBSC_DBPDRGD_0, 0x33C03C10);
+	mmio_write_32(DBSC_DBPDRGA_0, 0x00000006);
+	while (!(mmio_read_32(DBSC_DBPDRGD_0) & BIT(0)))
+		;
+
+	mmio_write_32(DBSC_DBPDRGA_0, 0x000000A7);
+	mmio_write_32(DBSC_DBPDRGD_0, 0x0D0D0D0D);
+	mmio_write_32(DBSC_DBPDRGA_0, 0x000000A8);
+	mmio_write_32(DBSC_DBPDRGD_0, 0x0D0D0D0D);
+	mmio_write_32(DBSC_DBPDRGA_0, 0x000000A9);
+	mmio_write_32(DBSC_DBPDRGD_0, 0x000D0D0D);
+	mmio_write_32(DBSC_DBPDRGA_0, 0x000000C7);
+	mmio_write_32(DBSC_DBPDRGD_0, 0x0D0D0D0D);
+	mmio_write_32(DBSC_DBPDRGA_0, 0x000000C8);
+	mmio_write_32(DBSC_DBPDRGD_0, 0x0D0D0D0D);
+	mmio_write_32(DBSC_DBPDRGA_0, 0x000000C9);
+	mmio_write_32(DBSC_DBPDRGD_0, 0x000D0D0D);
+
+	mmio_write_32(DBSC_DBPDRGA_0, 0x0000000E);
+	r2 = (mmio_read_32(DBSC_DBPDRGD_0) & 0x0000FF00) >> 0x9;
+	r3 = (r2 << 16) + (r2 << 8) + r2;
+	r6 = (r2 << 24) + (r2 << 16) + (r2 << 8) + r2;
+	mmio_write_32(DBSC_DBPDRGA_0, 0x00000011);
+	mmio_write_32(DBSC_DBPDRGD_0, r3);
+	mmio_write_32(DBSC_DBPDRGA_0, 0x00000012);
+	mmio_write_32(DBSC_DBPDRGD_0, r3);
+	mmio_write_32(DBSC_DBPDRGA_0, 0x00000016);
+	mmio_write_32(DBSC_DBPDRGD_0, r6);
+	mmio_write_32(DBSC_DBPDRGA_0, 0x00000017);
+	mmio_write_32(DBSC_DBPDRGD_0, r6);
+	mmio_write_32(DBSC_DBPDRGA_0, 0x00000018);
+	mmio_write_32(DBSC_DBPDRGD_0, r6);
+	mmio_write_32(DBSC_DBPDRGA_0, 0x00000019);
+	mmio_write_32(DBSC_DBPDRGD_0, r6);
+
+	mmio_write_32(DBSC_DBPDRGA_0, 0x00000001);
+	mmio_write_32(DBSC_DBPDRGD_0, 0x00010181);
+	mmio_write_32(DBSC_DBCMD, 0x08000001);
+	mmio_write_32(DBSC_DBPDRGA_0, 0x00000006);
+	while (!(mmio_read_32(DBSC_DBPDRGD_0) & BIT(0)))
+		;
+
+	mmio_write_32(DBSC_DBPDRGA_0, 0x00000001);
+	mmio_write_32(DBSC_DBPDRGD_0, 0x00010601);
+	mmio_write_32(DBSC_DBPDRGA_0, 0x00000006);
+	while (!(mmio_read_32(DBSC_DBPDRGD_0) & BIT(0)))
+		;
+
+	for (i = 0; i < 2; i++) {
+		mmio_write_32(DBSC_DBPDRGA_0, 0xB1 + i * 0x20);
+		r5 = (mmio_read_32(DBSC_DBPDRGD_0) & 0xFF00) >> 0x8;
+		mmio_write_32(DBSC_DBPDRGA_0, 0xB4 + i * 0x20);
+		r6 = mmio_read_32(DBSC_DBPDRGD_0) & 0xFF;
+		mmio_write_32(DBSC_DBPDRGA_0, 0xB3 + i * 0x20);
+		r7 = mmio_read_32(DBSC_DBPDRGD_0) & 0x7;
+		if (r6 > 0) {
+			mmio_write_32(DBSC_DBPDRGA_0, 0xB2 + i * 0x20);
+			r2 = mmio_read_32(DBSC_DBPDRGD_0) & 0xFFFFFFF8;
+
+			mmio_write_32(DBSC_DBPDRGA_0, 0xB2 + i * 0x20);
+			mmio_write_32(DBSC_DBPDRGD_0, r2 | ((r7 + 0x1) & 0x7));
+			mmio_write_32(DBSC_DBPDRGA_0, 0xB0 + i * 0x20);
+			r2 = mmio_read_32(DBSC_DBPDRGD_0) & 0xFFFFFF00;
+			mmio_write_32(DBSC_DBPDRGA_0, 0xB0 + i * 0x20);
+			mmio_write_32(DBSC_DBPDRGD_0, r2 | r6);
+		} else {
+			mmio_write_32(DBSC_DBPDRGA_0, 0xB2 + i * 0x20);
+			r2 = mmio_read_32(DBSC_DBPDRGD_0) & 0xFFFFFFF8;
+			mmio_write_32(DBSC_DBPDRGA_0, 0xB2 + i * 0x20);
+			mmio_write_32(DBSC_DBPDRGD_0, r2 | r7);
+
+			mmio_write_32(DBSC_DBPDRGA_0, 0xB0 + i * 0x20);
+			r2 = mmio_read_32(DBSC_DBPDRGD_0) & 0xFFFFFF00;
+			mmio_write_32(DBSC_DBPDRGA_0, 0xB0 + i * 0x20);
+			mmio_write_32(DBSC_DBPDRGD_0, r2 |
+						     ((r6 + (r5 << 1)) & 0xFF));
+		}
+	}
+
+	mmio_write_32(DBSC_DBPDRGA_0, 0x00000005);
+	mmio_write_32(DBSC_DBPDRGD_0, 0xC1AA00C0);
+	mmio_write_32(DBSC_DBPDRGA_0, 0x000000A0);
+	mmio_write_32(DBSC_DBPDRGD_0, 0x7C0002C5);
+	mmio_write_32(DBSC_DBPDRGA_0, 0x000000C0);
+	mmio_write_32(DBSC_DBPDRGD_0, 0x7C0002C5);
+	mmio_write_32(DBSC_DBPDRGA_0, 0x00000001);
+	mmio_write_32(DBSC_DBPDRGD_0, 0x00010801);
+	mmio_write_32(DBSC_DBPDRGA_0, 0x00000006);
+	while (!(mmio_read_32(DBSC_DBPDRGD_0) & BIT(0)))
+		;
+
+	mmio_write_32(DBSC_DBPDRGA_0, 0x00000005);
+	mmio_write_32(DBSC_DBPDRGD_0, 0xC1AA00D8);
+	mmio_write_32(DBSC_DBPDRGA_0, 0x00000001);
+	mmio_write_32(DBSC_DBPDRGD_0, 0x0001F001);
+	mmio_write_32(DBSC_DBPDRGA_0, 0x00000006);
+	while (!(mmio_read_32(DBSC_DBPDRGD_0) & BIT(0)))
+		;
+
+	mmio_write_32(DBSC_DBPDRGA_0, 0x000000AF);
+	r2 = mmio_read_32(DBSC_DBPDRGD_0);
+	mmio_write_32(DBSC_DBPDRGD_0, ((r2 + 0x1) & 0xFF) | (r2 & 0xFFFFFF00));
+	mmio_write_32(DBSC_DBPDRGA_0, 0x000000CF);
+	r2 = mmio_read_32(DBSC_DBPDRGD_0);
+	mmio_write_32(DBSC_DBPDRGD_0, ((r2 + 0x1) & 0xFF) | (r2 & 0xFFFFFF00));
+
+	mmio_write_32(DBSC_DBPDRGA_0, 0x000000A0);
+	mmio_write_32(DBSC_DBPDRGD_0, 0x7C000285);
+	mmio_write_32(DBSC_DBPDRGA_0, 0x000000C0);
+	mmio_write_32(DBSC_DBPDRGD_0, 0x7C000285);
+	mmio_write_32(DBSC_DBPDRGA_0, 0x0000002C);
+	mmio_write_32(DBSC_DBPDRGD_0, 0x81003087);
+	mmio_write_32(DBSC_DBPDRGA_0, 0x00000001);
+	mmio_write_32(DBSC_DBPDRGD_0, 0x00010401);
+	mmio_write_32(DBSC_DBPDRGA_0, 0x00000006);
+	while (!(mmio_read_32(DBSC_DBPDRGD_0) & BIT(0)))
+		;
+
+	for (i = 0; i < 2; i++) {
+		mmio_write_32(DBSC_DBPDRGA_0, 0xB1 + i * 0x20);
+		r5 = (mmio_read_32(DBSC_DBPDRGD_0) & 0xFF00) >> 0x8;
+		mmio_write_32(DBSC_DBPDRGA_0, 0xB4 + i * 0x20);
+		r6 = mmio_read_32(DBSC_DBPDRGD_0) & 0xFF;
+
+		mmio_write_32(DBSC_DBPDRGA_0, 0xB3 + i * 0x20);
+		r7 = mmio_read_32(DBSC_DBPDRGD_0) & 0x7;
+		r12 = (r5 >> 0x2);
+
+		if (r12 < r6) {
+			mmio_write_32(DBSC_DBPDRGA_0, 0xB2 + i * 0x20);
+			r2 = mmio_read_32(DBSC_DBPDRGD_0) & 0xFFFFFFF8;
+
+			mmio_write_32(DBSC_DBPDRGA_0, 0xB2 + i * 0x20);
+			mmio_write_32(DBSC_DBPDRGD_0, r2 | ((r7 + 0x1) & 0x7));
+			mmio_write_32(DBSC_DBPDRGA_0, 0xB0 + i * 0x20);
+			r2 = mmio_read_32(DBSC_DBPDRGD_0) & 0xFFFFFF00;
+
+			mmio_write_32(DBSC_DBPDRGA_0, 0xB0 + i * 0x20);
+			mmio_write_32(DBSC_DBPDRGD_0, r2 | ((r6 - r12) & 0xFF));
+		} else {
+			mmio_write_32(DBSC_DBPDRGA_0, 0xB2 + i * 0x20);
+			r2 = mmio_read_32(DBSC_DBPDRGD_0) & 0xFFFFFFF8;
+			mmio_write_32(DBSC_DBPDRGA_0, 0xB2 + i * 0x20);
+			mmio_write_32(DBSC_DBPDRGD_0, r2 | (r7 & 0x7));
+			mmio_write_32(DBSC_DBPDRGA_0, 0xB0 + i * 0x20);
+			r2 = mmio_read_32(DBSC_DBPDRGD_0) & 0xFFFFFF00;
+			mmio_write_32(DBSC_DBPDRGA_0, 0xB0 + i * 0x20);
+			mmio_write_32(DBSC_DBPDRGD_0, r2 |
+						     ((r6 + r5 +
+						      (r5 >> 1) + r12) & 0xFF));
+		}
+	}
+
+	mmio_write_32(DBSC_DBPDRGA_0, 0x000000A0);
+	mmio_write_32(DBSC_DBPDRGD_0, 0x7C0002C5);
+	mmio_write_32(DBSC_DBPDRGA_0, 0x000000C0);
+	mmio_write_32(DBSC_DBPDRGD_0, 0x7C0002C5);
+	mmio_write_32(DBSC_DBPDRGA_0, 0x00000001);
+	mmio_write_32(DBSC_DBPDRGD_0, 0x00015001);
+	mmio_write_32(DBSC_DBPDRGA_0, 0x00000006);
+	while (!(mmio_read_32(DBSC_DBPDRGD_0) & BIT(0)))
+		;
+
+	mmio_write_32(DBSC_DBPDRGA_0, 0x00000003);
+	mmio_write_32(DBSC_DBPDRGD_0, 0x0380C700);
+	mmio_write_32(DBSC_DBPDRGA_0, 0x00000007);
+	while (mmio_read_32(DBSC_DBPDRGD_0) & BIT(30))
+		;
+	mmio_write_32(DBSC_DBPDRGA_0, 0x00000021);
+	mmio_write_32(DBSC_DBPDRGD_0, 0x0024643E);
+
+	mmio_write_32(DBSC_DBBUS0CNF1, 0x00000010);
+	mmio_write_32(DBSC_DBCALCNF, 0x0100401B);
+	mmio_write_32(DBSC_DBRFCNF1, 0x00080C30);
+	mmio_write_32(DBSC_DBRFCNF2, 0x00010000);
+	mmio_write_32(DBSC_DBDFICUPDCNF, 0x40100001);
+	mmio_write_32(DBSC_DBRFEN, 0x00000001);
+	mmio_write_32(DBSC_DBACEN, 0x00000001);
+	mmio_write_32(DBSC_DBPDLK_0, 0x00000000);
+	mmio_write_32(DBSC_DBSYSCNT0, 0x00000000);
+
+#ifdef ddr_qos_init_setting // only for non qos_init
+	mmio_write_32(DBSC_DBSYSCNT0, 0x00001234);
+	mmio_write_32(DBSC_DBCAM0CNF1, 0x00043218);
+	mmio_write_32(DBSC_DBCAM0CNF2, 0x000000F4);
+	mmio_write_32(DBSC_DBSCHCNT0, 0x000f0037);
+	mmio_write_32(DBSC_DBSCHSZ0, 0x00000001);
+	mmio_write_32(DBSC_DBSCHRW0, 0x22421111);
+	mmio_write_32(DBSC_SCFCTST2, 0x012F1123);
+	mmio_write_32(DBSC_DBSCHQOS00, 0x00000F00);
+	mmio_write_32(DBSC_DBSCHQOS01, 0x00000B00);
+	mmio_write_32(DBSC_DBSCHQOS02, 0x00000000);
+	mmio_write_32(DBSC_DBSCHQOS03, 0x00000000);
+	mmio_write_32(DBSC_DBSCHQOS40, 0x00000300);
+	mmio_write_32(DBSC_DBSCHQOS41, 0x000002F0);
+	mmio_write_32(DBSC_DBSCHQOS42, 0x00000200);
+	mmio_write_32(DBSC_DBSCHQOS43, 0x00000100);
+	mmio_write_32(DBSC_DBSCHQOS90, 0x00000300);
+	mmio_write_32(DBSC_DBSCHQOS91, 0x000002F0);
+	mmio_write_32(DBSC_DBSCHQOS92, 0x00000200);
+	mmio_write_32(DBSC_DBSCHQOS93, 0x00000100);
+	mmio_write_32(DBSC_DBSCHQOS130, 0x00000100);
+	mmio_write_32(DBSC_DBSCHQOS131, 0x000000F0);
+	mmio_write_32(DBSC_DBSCHQOS132, 0x000000A0);
+	mmio_write_32(DBSC_DBSCHQOS133, 0x00000040);
+	mmio_write_32(DBSC_DBSCHQOS140, 0x000000C0);
+	mmio_write_32(DBSC_DBSCHQOS141, 0x000000B0);
+	mmio_write_32(DBSC_DBSCHQOS142, 0x00000080);
+	mmio_write_32(DBSC_DBSCHQOS143, 0x00000040);
+	mmio_write_32(DBSC_DBSCHQOS150, 0x00000040);
+	mmio_write_32(DBSC_DBSCHQOS151, 0x00000030);
+	mmio_write_32(DBSC_DBSCHQOS152, 0x00000020);
+	mmio_write_32(DBSC_DBSCHQOS153, 0x00000010);
+	mmio_write_32(0xE67F0018, 0x00000001);
+	mmio_write_32(DBSC_DBSYSCNT0, 0x00000000);
+#endif
+}
+
+#define PRR			0xFFF00044U
+#define PRR_PRODUCT_MASK	0x00007F00U
+#define PRR_PRODUCT_D3		0x00005800U
+
+#define	MODEMR_MD19		BIT(19)
+
+int32_t rcar_dram_init(void)
+{
+	uint32_t reg;
+	uint32_t ddr_mbps;
+
+	reg = mmio_read_32(PRR);
+	if ((reg & PRR_PRODUCT_MASK) != PRR_PRODUCT_D3) {
+		ERROR("LSI Product ID (PRR=0x%x) DDR initialize not supported.\n",
+		      reg);
+		panic();
+	}
+
+	reg = mmio_read_32(RST_MODEMR);
+	if (reg & MODEMR_MD19) {
+		init_ddr_d3_1866();
+		ddr_mbps = 1866;
+	} else {
+		init_ddr_d3_1600();
+		ddr_mbps = 1600;
+	}
+
+	NOTICE("BL2: DDR%d\n", ddr_mbps);
+
+	return 0;
+}
diff --git a/drivers/renesas/rcar/ddr/ddr_a/ddr_init_e3.c b/drivers/renesas/rcar/ddr/ddr_a/ddr_init_e3.c
new file mode 100644
index 000000000..fc278ef57
--- /dev/null
+++ b/drivers/renesas/rcar/ddr/ddr_a/ddr_init_e3.c
@@ -0,0 +1,1712 @@
+/*
+ * Copyright (c) 2015-2019, Renesas Electronics Corporation.
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <lib/mmio.h>
+#include <stdint.h>
+
+#include <common/debug.h>
+
+#include "boot_init_dram.h"
+#include "rcar_def.h"
+#include "../ddr_regs.h"
+
+#include "../dram_sub_func.h"
+
+#define RCAR_E3_DDR_VERSION    "rev.0.12"
+
+/* Average periodic refresh interval[ns]. Support 3900,7800 */
+#ifdef ddr_qos_init_setting
+#define REFRESH_RATE	3900U
+#else
+#if RCAR_REF_INT == 1
+#define REFRESH_RATE	7800U
+#else
+#define REFRESH_RATE	3900U
+#endif
+#endif
+
+/*
+ *  Initialize ddr
+ */
+uint32_t init_ddr(void)
+{
+	uint32_t i, r2, r5, r6, r7, r12;
+	uint32_t ddr_md;
+	uint32_t regval, j;
+	uint32_t dqsgd_0c, bdlcount_0c, bdlcount_0c_div2, bdlcount_0c_div4;
+	uint32_t bdlcount_0c_div8, bdlcount_0c_div16;
+	uint32_t gatesl_0c, rdqsd_0c, rdqsnd_0c, rbd_0c[4];
+	uint32_t pdqsr_ctl, lcdl_ctl, lcdl_judge1, lcdl_judge2;
+	uint32_t pdr_ctl;
+	uint32_t byp_ctl;
+
+	if ((mmio_read_32(0xFFF00044) & 0x000000FF) == 0x00000000) {
+		pdqsr_ctl = 1;
+		lcdl_ctl = 1;
+		pdr_ctl = 1;
+		byp_ctl = 1;
+	} else {
+		pdqsr_ctl = 0;
+		lcdl_ctl = 0;
+		pdr_ctl = 0;
+		byp_ctl = 0;
+	}
+
+	/* Judge the DDR bit rate (ddr_md : 0 = 1584Mbps, 1 = 1856Mbps) */
+	ddr_md = (mmio_read_32(RST_MODEMR) >> 19) & BIT(0);
+
+	/* 1584Mbps setting */
+	if (ddr_md == 0) {
+		mmio_write_32(CPG_CPGWPR, 0x5A5AFFFF);
+		mmio_write_32(CPG_CPGWPCR, 0xA5A50000);
+
+		mmio_write_32(CPG_SRCR4, 0x20000000);
+
+		mmio_write_32(0xE61500DC, 0xe2200000);	/* Change to 1584Mbps */
+		while (!(mmio_read_32(CPG_PLLECR) & BIT(11)))
+			;
+
+		mmio_write_32(CPG_SRSTCLR4, 0x20000000);
+
+		mmio_write_32(CPG_CPGWPCR, 0xA5A50001);
+	}
+
+	mmio_write_32(DBSC_DBSYSCNT0, 0x00001234);
+	mmio_write_32(DBSC_DBKIND, 0x00000007);
+
+#if RCAR_DRAM_DDR3L_MEMCONF == 0
+	mmio_write_32(DBSC_DBMEMCONF_0_0, 0x0f030a02);	/* 1GB */
+#else
+	mmio_write_32(DBSC_DBMEMCONF_0_0, 0x10030a02);	/* 2GB(default) */
+#endif
+
+#if RCAR_DRAM_DDR3L_MEMDUAL == 1
+	r2 = mmio_read_32(0xE6790614);
+	mmio_write_32(0xE6790614, r2 | 0x3); /* MCS1_N/MODT1 are activated. */
+#endif
+
+	mmio_write_32(DBSC_DBPHYCONF0, 0x1);
+
+	/* Select setting value in bps */
+	if (ddr_md == 0) {	/* 1584Mbps */
+		mmio_write_32(DBSC_DBTR0, 0xB);
+		mmio_write_32(DBSC_DBTR1, 0x8);
+	} else {		/* 1856Mbps */
+		mmio_write_32(DBSC_DBTR0, 0xD);
+		mmio_write_32(DBSC_DBTR1, 0x9);
+	}
+
+	mmio_write_32(DBSC_DBTR2, 0x00000000);
+
+	/* Select setting value in bps */
+	if (ddr_md == 0) {	/* 1584Mbps */
+		mmio_write_32(DBSC_DBTR3, 0x0000000B);
+		mmio_write_32(DBSC_DBTR4, 0x000B000B);
+		mmio_write_32(DBSC_DBTR5, 0x00000027);
+		mmio_write_32(DBSC_DBTR6, 0x0000001C);
+	} else {		/* 1856Mbps */
+		mmio_write_32(DBSC_DBTR3, 0x0000000D);
+		mmio_write_32(DBSC_DBTR4, 0x000D000D);
+		mmio_write_32(DBSC_DBTR5, 0x0000002D);
+		mmio_write_32(DBSC_DBTR6, 0x00000020);
+	}
+
+	mmio_write_32(DBSC_DBTR7, 0x00060006);
+
+	/* Select setting value in bps */
+	if (ddr_md == 0) {	/* 1584Mbps */
+		mmio_write_32(DBSC_DBTR8, 0x00000020);
+		mmio_write_32(DBSC_DBTR9, 0x00000006);
+		mmio_write_32(DBSC_DBTR10, 0x0000000C);
+		mmio_write_32(DBSC_DBTR11, 0x0000000A);
+		mmio_write_32(DBSC_DBTR12, 0x00120012);
+		mmio_write_32(DBSC_DBTR13, 0x000000CE);
+		mmio_write_32(DBSC_DBTR14, 0x00140005);
+		mmio_write_32(DBSC_DBTR15, 0x00050004);
+		mmio_write_32(DBSC_DBTR16, 0x071F0305);
+		mmio_write_32(DBSC_DBTR17, 0x040C0000);
+	} else {		/* 1856Mbps */
+		mmio_write_32(DBSC_DBTR8, 0x00000021);
+		mmio_write_32(DBSC_DBTR9, 0x00000007);
+		mmio_write_32(DBSC_DBTR10, 0x0000000E);
+		mmio_write_32(DBSC_DBTR11, 0x0000000C);
+		mmio_write_32(DBSC_DBTR12, 0x00140014);
+		mmio_write_32(DBSC_DBTR13, 0x000000F2);
+		mmio_write_32(DBSC_DBTR14, 0x00170006);
+		mmio_write_32(DBSC_DBTR15, 0x00060005);
+		mmio_write_32(DBSC_DBTR16, 0x09210507);
+		mmio_write_32(DBSC_DBTR17, 0x040E0000);
+	}
+
+	mmio_write_32(DBSC_DBTR18, 0x00000200);
+
+	/* Select setting value in bps */
+	if (ddr_md == 0) {	/* 1584Mbps */
+		mmio_write_32(DBSC_DBTR19, 0x01000040);
+		mmio_write_32(DBSC_DBTR20, 0x020000D6);
+	} else {		/* 1856Mbps */
+		mmio_write_32(DBSC_DBTR19, 0x0129004B);
+		mmio_write_32(DBSC_DBTR20, 0x020000FB);
+	}
+
+	mmio_write_32(DBSC_DBTR21, 0x00040004);
+	mmio_write_32(DBSC_DBBL, 0x00000000);
+	mmio_write_32(DBSC_DBODT0, 0x00000001);
+	mmio_write_32(DBSC_DBADJ0, 0x00000001);
+	mmio_write_32(DBSC_DBSYSCONF1, 0x00000002);
+	mmio_write_32(DBSC_DBDFICNT_0, 0x00000010);
+	mmio_write_32(DBSC_DBBCAMDIS, 0x00000001);
+	mmio_write_32(DBSC_DBSCHRW1, 0x00000046);
+
+	/* Select setting value in bps */
+	if (ddr_md == 0) {	/* 1584Mbps */
+		mmio_write_32(DBSC_SCFCTST0, 0x0D050B03);
+		mmio_write_32(DBSC_SCFCTST1, 0x0306030C);
+	} else {		/* 1856Mbps */
+		mmio_write_32(DBSC_SCFCTST0, 0x0C050B03);
+		mmio_write_32(DBSC_SCFCTST1, 0x0305030C);
+	}
+
+	/*
+	 * Initial_Step0( INITBYP )
+	 */
+	mmio_write_32(DBSC_DBPDLK_0, 0x0000A55A);
+	mmio_write_32(DBSC_DBCMD, 0x01840001);
+	mmio_write_32(DBSC_DBCMD, 0x08840000);
+	NOTICE("BL2: [COLD_BOOT]\n");
+	mmio_write_32(DBSC_DBPDRGA_0, 0x00000001);
+	mmio_write_32(DBSC_DBPDRGD_0, 0x80010000);
+	mmio_write_32(DBSC_DBPDRGA_0, 0x00000006);
+	while (!(mmio_read_32(DBSC_DBPDRGD_0) & BIT(0)))
+		;
+
+	/*
+	 * Initial_Step1( ZCAL,PLLINIT,DCAL,PHYRST training )
+	 */
+	mmio_write_32(DBSC_DBPDRGA_0, 0x00000008);
+	mmio_write_32(DBSC_DBPDRGD_0, 0x000B8000);
+	mmio_write_32(DBSC_DBPDRGA_0, 0x00000090);
+
+	/* Select setting value in bps */
+	if (ddr_md == 0)	/* 1584Mbps */
+		mmio_write_32(DBSC_DBPDRGD_0, 0x04058904);
+	else			/* 1856Mbps */
+		mmio_write_32(DBSC_DBPDRGD_0, 0x04058A04);
+
+	mmio_write_32(DBSC_DBPDRGA_0, 0x00000091);
+	mmio_write_32(DBSC_DBPDRGD_0, 0x0007BB6B);
+	mmio_write_32(DBSC_DBPDRGA_0, 0x00000095);
+	mmio_write_32(DBSC_DBPDRGD_0, 0x0007BBAD);
+	mmio_write_32(DBSC_DBPDRGA_0, 0x00000099);
+	mmio_write_32(DBSC_DBPDRGD_0, 0x0007BB6B);
+	mmio_write_32(DBSC_DBPDRGA_0, 0x00000090);
+
+	/* Select setting value in bps */
+	if (ddr_md == 0)	/* 1584Mbps */
+		mmio_write_32(DBSC_DBPDRGD_0, 0x04058900);
+	else			/* 1856Mbps */
+		mmio_write_32(DBSC_DBPDRGD_0, 0x04058A00);
+
+	mmio_write_32(DBSC_DBPDRGA_0, 0x00000021);
+	mmio_write_32(DBSC_DBPDRGD_0, 0x0024641E);
+	mmio_write_32(DBSC_DBPDRGA_0, 0x00000001);
+	mmio_write_32(DBSC_DBPDRGD_0, 0x00010073);
+	mmio_write_32(DBSC_DBPDRGA_0, 0x00000006);
+	while (!(mmio_read_32(DBSC_DBPDRGD_0) & BIT(0)))
+		;
+
+	/*
+	 * Initial_Step2( DRAMRST/DRAMINT training )
+	 */
+	mmio_write_32(DBSC_DBPDRGA_0, 0x00000090);
+
+	/* Select setting value in bps */
+	if (ddr_md == 0)	/* 1584Mbps */
+		mmio_write_32(DBSC_DBPDRGD_0, 0x0C058900);
+	else			/* 1856Mbps */
+		mmio_write_32(DBSC_DBPDRGD_0, 0x0C058A00);
+
+	mmio_write_32(DBSC_DBPDRGA_0, 0x00000090);
+
+	/* Select setting value in bps */
+	if (ddr_md == 0)	/* 1584Mbps */
+		mmio_write_32(DBSC_DBPDRGD_0, 0x04058900);
+	else			/* 1856Mbps */
+		mmio_write_32(DBSC_DBPDRGD_0, 0x04058A00);
+
+	mmio_write_32(DBSC_DBPDRGA_0, 0x00000006);
+	while (!(mmio_read_32(DBSC_DBPDRGD_0) & BIT(0)))
+		;
+
+	mmio_write_32(DBSC_DBPDRGA_0, 0x00000003);
+	if (byp_ctl == 1)
+		mmio_write_32(DBSC_DBPDRGD_0, 0x0780C720);
+	else
+		mmio_write_32(DBSC_DBPDRGD_0, 0x0780C700);
+
+	mmio_write_32(DBSC_DBPDRGA_0, 0x00000007);
+	while (!(mmio_read_32(DBSC_DBPDRGD_0) & BIT(30)))
+		;
+
+	mmio_write_32(DBSC_DBPDRGA_0, 0x00000004);
+
+	/* Select setting value in bps */
+	if (ddr_md == 0) {	/* 1584Mbps */
+		mmio_write_32(DBSC_DBPDRGD_0, (REFRESH_RATE * 792 / 125) -
+					     400 + 0x08B00000);
+	} else {		/* 1856Mbps */
+		mmio_write_32(DBSC_DBPDRGD_0, (REFRESH_RATE * 928 / 125) -
+					     400 + 0x0A300000);
+	}
+
+	mmio_write_32(DBSC_DBPDRGA_0, 0x00000022);
+	mmio_write_32(DBSC_DBPDRGD_0, 0x1000040B);
+	mmio_write_32(DBSC_DBPDRGA_0, 0x00000023);
+
+	/* Select setting value in bps */
+	if (ddr_md == 0)	/* 1584Mbps */
+		mmio_write_32(DBSC_DBPDRGD_0, 0x2D9C0B66);
+	else			/* 1856Mbps */
+		mmio_write_32(DBSC_DBPDRGD_0, 0x35A00D77);
+
+	mmio_write_32(DBSC_DBPDRGA_0, 0x00000024);
+
+	/* Select setting value in bps */
+	if (ddr_md == 0)	/* 1584Mbps */
+		mmio_write_32(DBSC_DBPDRGD_0, 0x2A88B400);
+	else			/* 1856Mbps */
+		mmio_write_32(DBSC_DBPDRGD_0, 0x2A8A2C28);
+
+	mmio_write_32(DBSC_DBPDRGA_0, 0x00000025);
+
+	/* Select setting value in bps */
+	if (ddr_md == 0)	/* 1584Mbps */
+		mmio_write_32(DBSC_DBPDRGD_0, 0x30005200);
+	else			/* 1856Mbps */
+		mmio_write_32(DBSC_DBPDRGD_0, 0x30005E00);
+
+	mmio_write_32(DBSC_DBPDRGA_0, 0x00000026);
+
+	/* Select setting value in bps */
+	if (ddr_md == 0)	/* 1584Mbps */
+		mmio_write_32(DBSC_DBPDRGD_0, 0x0014A9C9);
+	else			/* 1856Mbps */
+		mmio_write_32(DBSC_DBPDRGD_0, 0x0014CB49);
+
+	mmio_write_32(DBSC_DBPDRGA_0, 0x00000027);
+
+	/* Select setting value in bps */
+	if (ddr_md == 0)	/* 1584Mbps */
+		mmio_write_32(DBSC_DBPDRGD_0, 0x00000D70);
+	else			/* 1856Mbps */
+		mmio_write_32(DBSC_DBPDRGD_0, 0x00000F14);
+
+	mmio_write_32(DBSC_DBPDRGA_0, 0x00000028);
+	mmio_write_32(DBSC_DBPDRGD_0, 0x00000046);
+	mmio_write_32(DBSC_DBPDRGA_0, 0x00000029);
+
+	/* Select setting value in bps */
+	if (ddr_md == 0) {	/* 1584Mbps */
+		if (REFRESH_RATE > 3900)	/* [7]SRT=0 */
+			mmio_write_32(DBSC_DBPDRGD_0, 0x18);
+		else				/* [7]SRT=1 */
+			mmio_write_32(DBSC_DBPDRGD_0, 0x98);
+	} else {		/* 1856Mbps */
+		if (REFRESH_RATE > 3900)	/* [7]SRT=0 */
+			mmio_write_32(DBSC_DBPDRGD_0, 0x20);
+		else				/* [7]SRT=1 */
+			mmio_write_32(DBSC_DBPDRGD_0, 0xA0);
+	}
+
+	mmio_write_32(DBSC_DBPDRGA_0, 0x0000002C);
+	mmio_write_32(DBSC_DBPDRGD_0, 0x81003047);
+	mmio_write_32(DBSC_DBPDRGA_0, 0x00000020);
+	mmio_write_32(DBSC_DBPDRGD_0, 0x00181884);
+	mmio_write_32(DBSC_DBPDRGA_0, 0x0000001A);
+	mmio_write_32(DBSC_DBPDRGD_0, 0x33C03C10);
+	mmio_write_32(DBSC_DBPDRGA_0, 0x00000006);
+	while (!(mmio_read_32(DBSC_DBPDRGD_0) & BIT(0)))
+		;
+
+	mmio_write_32(DBSC_DBPDRGA_0, 0x000000A7);
+	mmio_write_32(DBSC_DBPDRGD_0, 0x0D0D0D0D);
+	mmio_write_32(DBSC_DBPDRGA_0, 0x000000A8);
+	mmio_write_32(DBSC_DBPDRGD_0, 0x0D0D0D0D);
+	mmio_write_32(DBSC_DBPDRGA_0, 0x000000A9);
+	mmio_write_32(DBSC_DBPDRGD_0, 0x000D0D0D);
+	mmio_write_32(DBSC_DBPDRGA_0, 0x000000C7);
+	mmio_write_32(DBSC_DBPDRGD_0, 0x0D0D0D0D);
+	mmio_write_32(DBSC_DBPDRGA_0, 0x000000C8);
+	mmio_write_32(DBSC_DBPDRGD_0, 0x0D0D0D0D);
+	mmio_write_32(DBSC_DBPDRGA_0, 0x000000C9);
+	mmio_write_32(DBSC_DBPDRGD_0, 0x000D0D0D);
+	mmio_write_32(DBSC_DBPDRGA_0, 0x000000E7);
+	mmio_write_32(DBSC_DBPDRGD_0, 0x0D0D0D0D);
+	mmio_write_32(DBSC_DBPDRGA_0, 0x000000E8);
+	mmio_write_32(DBSC_DBPDRGD_0, 0x0D0D0D0D);
+	mmio_write_32(DBSC_DBPDRGA_0, 0x000000E9);
+	mmio_write_32(DBSC_DBPDRGD_0, 0x000D0D0D);
+	mmio_write_32(DBSC_DBPDRGA_0, 0x00000107);
+	mmio_write_32(DBSC_DBPDRGD_0, 0x0D0D0D0D);
+	mmio_write_32(DBSC_DBPDRGA_0, 0x00000108);
+	mmio_write_32(DBSC_DBPDRGD_0, 0x0D0D0D0D);
+	mmio_write_32(DBSC_DBPDRGA_0, 0x00000109);
+	mmio_write_32(DBSC_DBPDRGD_0, 0x000D0D0D);
+
+	mmio_write_32(DBSC_DBPDRGA_0, 0x00000001);
+	mmio_write_32(DBSC_DBPDRGD_0, 0x00010181);
+	mmio_write_32(DBSC_DBCMD, 0x08840001);
+	mmio_write_32(DBSC_DBPDRGA_0, 0x00000006);
+	while (!(mmio_read_32(DBSC_DBPDRGD_0) & BIT(0)))
+		;
+
+	/*
+	 * Initial_Step3( WL/QSG training )
+	 */
+	mmio_write_32(DBSC_DBPDRGA_0, 0x00000001);
+	mmio_write_32(DBSC_DBPDRGD_0, 0x00010601);
+	mmio_write_32(DBSC_DBPDRGA_0, 0x00000006);
+	while (!(mmio_read_32(DBSC_DBPDRGD_0) & BIT(0)))
+		;
+
+	for (i = 0; i < 4; i++) {
+		mmio_write_32(DBSC_DBPDRGA_0, 0xB1 + i * 0x20);
+		r5 = (mmio_read_32(DBSC_DBPDRGD_0) & 0xFF00) >> 0x8;
+		mmio_write_32(DBSC_DBPDRGA_0, 0xB4 + i * 0x20);
+		r6 = mmio_read_32(DBSC_DBPDRGD_0) & 0xFF;
+		mmio_write_32(DBSC_DBPDRGA_0, 0xB3 + i * 0x20);
+		r7 = mmio_read_32(DBSC_DBPDRGD_0) & 0x7;
+
+		if (r6 > 0) {
+			mmio_write_32(DBSC_DBPDRGA_0, 0xB2 + i * 0x20);
+			r2 = mmio_read_32(DBSC_DBPDRGD_0) & 0xFFFFFFF8;
+			mmio_write_32(DBSC_DBPDRGA_0, 0xB2 + i * 0x20);
+			mmio_write_32(DBSC_DBPDRGD_0, r2 | ((r7 + 0x1) & 0x7));
+			mmio_write_32(DBSC_DBPDRGA_0, 0xB0 + i * 0x20);
+			r2 = mmio_read_32(DBSC_DBPDRGD_0) & 0xFFFFFF00;
+			mmio_write_32(DBSC_DBPDRGA_0, 0xB0 + i * 0x20);
+			mmio_write_32(DBSC_DBPDRGD_0, r2 | r6);
+		} else {
+			mmio_write_32(DBSC_DBPDRGA_0, 0xB2 + i * 0x20);
+			r2 = mmio_read_32(DBSC_DBPDRGD_0) & 0xFFFFFFF8;
+			mmio_write_32(DBSC_DBPDRGA_0, 0xB2 + i * 0x20);
+			mmio_write_32(DBSC_DBPDRGD_0, r2 | r7);
+			mmio_write_32(DBSC_DBPDRGA_0, 0xB0 + i * 0x20);
+			r2 = mmio_read_32(DBSC_DBPDRGD_0) & 0xFFFFFF00;
+			mmio_write_32(DBSC_DBPDRGA_0, 0xB0 + i * 0x20);
+			mmio_write_32(DBSC_DBPDRGD_0, r2 |
+						     ((r6 + ((r5) << 1)) &
+						     0xFF));
+		}
+	}
+
+	/*
+	 * Initial_Step4( WLADJ training )
+	 */
+	mmio_write_32(DBSC_DBPDRGA_0, 0x00000005);
+	mmio_write_32(DBSC_DBPDRGD_0, 0xC1AA00C0);
+
+	if (pdqsr_ctl == 0) {
+		mmio_write_32(DBSC_DBPDRGA_0, 0x000000A0);
+		mmio_write_32(DBSC_DBPDRGD_0, 0x7C0002C5);
+		mmio_write_32(DBSC_DBPDRGA_0, 0x000000C0);
+		mmio_write_32(DBSC_DBPDRGD_0, 0x7C0002C5);
+		mmio_write_32(DBSC_DBPDRGA_0, 0x000000E0);
+		mmio_write_32(DBSC_DBPDRGD_0, 0x7C0002C5);
+		mmio_write_32(DBSC_DBPDRGA_0, 0x00000100);
+		mmio_write_32(DBSC_DBPDRGD_0, 0x7C0002C5);
+	}
+
+	/* PDR always off */
+	if (pdr_ctl == 1) {
+		mmio_write_32(DBSC_DBPDRGA_0, 0x000000A3);
+		mmio_write_32(DBSC_DBPDRGD_0, 0x00000008);
+		mmio_write_32(DBSC_DBPDRGA_0, 0x000000C3);
+		mmio_write_32(DBSC_DBPDRGD_0, 0x00000008);
+		mmio_write_32(DBSC_DBPDRGA_0, 0x000000E3);
+		mmio_write_32(DBSC_DBPDRGD_0, 0x00000008);
+		mmio_write_32(DBSC_DBPDRGA_0, 0x00000103);
+		mmio_write_32(DBSC_DBPDRGD_0, 0x00000008);
+	}
+
+	mmio_write_32(DBSC_DBPDRGA_0, 0x00000001);
+	mmio_write_32(DBSC_DBPDRGD_0, 0x00010801);
+	mmio_write_32(DBSC_DBPDRGA_0, 0x00000006);
+	while (!(mmio_read_32(DBSC_DBPDRGD_0) & BIT(0)))
+		;
+
+	/*
+	 * Initial_Step5(Read Data Bit Deskew)
+	 */
+	mmio_write_32(DBSC_DBPDRGA_0, 0x00000005);
+	mmio_write_32(DBSC_DBPDRGD_0, 0xC1AA00D8);
+
+	mmio_write_32(DBSC_DBPDRGA_0, 0x00000001);
+	mmio_write_32(DBSC_DBPDRGD_0, 0x00011001);
+	mmio_write_32(DBSC_DBPDRGA_0, 0x00000006);
+	while (!(mmio_read_32(DBSC_DBPDRGD_0) & BIT(0)))
+		;
+
+	if (pdqsr_ctl == 1) {
+		mmio_write_32(DBSC_DBPDRGA_0, 0x000000A0);
+		mmio_write_32(DBSC_DBPDRGD_0, 0x7C0002C5);
+		mmio_write_32(DBSC_DBPDRGA_0, 0x000000C0);
+		mmio_write_32(DBSC_DBPDRGD_0, 0x7C0002C5);
+		mmio_write_32(DBSC_DBPDRGA_0, 0x000000E0);
+		mmio_write_32(DBSC_DBPDRGD_0, 0x7C0002C5);
+		mmio_write_32(DBSC_DBPDRGA_0, 0x00000100);
+		mmio_write_32(DBSC_DBPDRGD_0, 0x7C0002C5);
+	}
+
+	/* PDR dynamic */
+	if (pdr_ctl == 1) {
+		mmio_write_32(DBSC_DBPDRGA_0, 0x000000A3);
+		mmio_write_32(DBSC_DBPDRGD_0, 0x00000000);
+		mmio_write_32(DBSC_DBPDRGA_0, 0x000000C3);
+		mmio_write_32(DBSC_DBPDRGD_0, 0x00000000);
+		mmio_write_32(DBSC_DBPDRGA_0, 0x000000E3);
+		mmio_write_32(DBSC_DBPDRGD_0, 0x00000000);
+		mmio_write_32(DBSC_DBPDRGA_0, 0x00000103);
+		mmio_write_32(DBSC_DBPDRGD_0, 0x00000000);
+	}
+
+	/*
+	 * Initial_Step6(Write Data Bit Deskew)
+	 */
+	mmio_write_32(DBSC_DBPDRGA_0, 0x00000001);
+	mmio_write_32(DBSC_DBPDRGD_0, 0x00012001);
+	mmio_write_32(DBSC_DBPDRGA_0, 0x00000006);
+	while (!(mmio_read_32(DBSC_DBPDRGD_0) & BIT(0)))
+		;
+
+	/*
+	 * Initial_Step7(Read Data Eye Training)
+	 */
+	if (pdqsr_ctl == 1) {
+		mmio_write_32(DBSC_DBPDRGA_0, 0x000000A0);
+		mmio_write_32(DBSC_DBPDRGD_0, 0x7C000285);
+		mmio_write_32(DBSC_DBPDRGA_0, 0x000000C0);
+		mmio_write_32(DBSC_DBPDRGD_0, 0x7C000285);
+		mmio_write_32(DBSC_DBPDRGA_0, 0x000000E0);
+		mmio_write_32(DBSC_DBPDRGD_0, 0x7C000285);
+		mmio_write_32(DBSC_DBPDRGA_0, 0x00000100);
+		mmio_write_32(DBSC_DBPDRGD_0, 0x7C000285);
+	}
+
+	/* PDR always off */
+	if (pdr_ctl == 1) {
+		mmio_write_32(DBSC_DBPDRGA_0, 0x000000A3);
+		mmio_write_32(DBSC_DBPDRGD_0, 0x00000008);
+		mmio_write_32(DBSC_DBPDRGA_0, 0x000000C3);
+		mmio_write_32(DBSC_DBPDRGD_0, 0x00000008);
+		mmio_write_32(DBSC_DBPDRGA_0, 0x000000E3);
+		mmio_write_32(DBSC_DBPDRGD_0, 0x00000008);
+		mmio_write_32(DBSC_DBPDRGA_0, 0x00000103);
+		mmio_write_32(DBSC_DBPDRGD_0, 0x00000008);
+	}
+
+	mmio_write_32(DBSC_DBPDRGA_0, 0x00000001);
+	mmio_write_32(DBSC_DBPDRGD_0, 0x00014001);
+	mmio_write_32(DBSC_DBPDRGA_0, 0x00000006);
+	while (!(mmio_read_32(DBSC_DBPDRGD_0) & BIT(0)))
+		;
+
+	if (pdqsr_ctl == 1) {
+		mmio_write_32(DBSC_DBPDRGA_0, 0x000000A0);
+		mmio_write_32(DBSC_DBPDRGD_0, 0x7C0002C5);
+		mmio_write_32(DBSC_DBPDRGA_0, 0x000000C0);
+		mmio_write_32(DBSC_DBPDRGD_0, 0x7C0002C5);
+		mmio_write_32(DBSC_DBPDRGA_0, 0x000000E0);
+		mmio_write_32(DBSC_DBPDRGD_0, 0x7C0002C5);
+		mmio_write_32(DBSC_DBPDRGA_0, 0x00000100);
+		mmio_write_32(DBSC_DBPDRGD_0, 0x7C0002C5);
+	}
+
+	/* PDR dynamic */
+	if (pdr_ctl == 1) {
+		mmio_write_32(DBSC_DBPDRGA_0, 0x000000A3);
+		mmio_write_32(DBSC_DBPDRGD_0, 0x00000000);
+		mmio_write_32(DBSC_DBPDRGA_0, 0x000000C3);
+		mmio_write_32(DBSC_DBPDRGD_0, 0x00000000);
+		mmio_write_32(DBSC_DBPDRGA_0, 0x000000E3);
+		mmio_write_32(DBSC_DBPDRGD_0, 0x00000000);
+		mmio_write_32(DBSC_DBPDRGA_0, 0x00000103);
+		mmio_write_32(DBSC_DBPDRGD_0, 0x00000000);
+	}
+
+	/*
+	 * Initial_Step8(Write Data Eye Training)
+	 */
+	mmio_write_32(DBSC_DBPDRGA_0, 0x00000001);
+	mmio_write_32(DBSC_DBPDRGD_0, 0x00018001);
+	mmio_write_32(DBSC_DBPDRGA_0, 0x00000006);
+	while (!(mmio_read_32(DBSC_DBPDRGD_0) & BIT(0)))
+		;
+
+	/*
+	 * Initial_Step3_2( DQS Gate Training )
+	 */
+	mmio_write_32(DBSC_DBPDRGA_0, 0x000000A0);
+	mmio_write_32(DBSC_DBPDRGD_0, 0x7C000285);
+	mmio_write_32(DBSC_DBPDRGA_0, 0x000000C0);
+	mmio_write_32(DBSC_DBPDRGD_0, 0x7C000285);
+	mmio_write_32(DBSC_DBPDRGA_0, 0x000000E0);
+	mmio_write_32(DBSC_DBPDRGD_0, 0x7C000285);
+	mmio_write_32(DBSC_DBPDRGA_0, 0x00000100);
+	mmio_write_32(DBSC_DBPDRGD_0, 0x7C000285);
+	mmio_write_32(DBSC_DBPDRGA_0, 0x0000002C);
+	mmio_write_32(DBSC_DBPDRGD_0, 0x81003087);
+	mmio_write_32(DBSC_DBPDRGA_0, 0x00000001);
+	mmio_write_32(DBSC_DBPDRGD_0, 0x00010401);
+	mmio_write_32(DBSC_DBPDRGA_0, 0x00000006);
+	while (!(mmio_read_32(DBSC_DBPDRGD_0) & BIT(0)))
+		;
+
+	for (i = 0; i < 4; i++) {
+		mmio_write_32(DBSC_DBPDRGA_0, 0xB1 + i * 0x20);
+		r5 = ((mmio_read_32(DBSC_DBPDRGD_0) & 0xFF00) >> 0x8);
+		mmio_write_32(DBSC_DBPDRGA_0, 0xB4 + i * 0x20);
+		r6 = mmio_read_32(DBSC_DBPDRGD_0) & 0xFF;
+		mmio_write_32(DBSC_DBPDRGA_0, 0xB3 + i * 0x20);
+		r7 = mmio_read_32(DBSC_DBPDRGD_0) & 0x7;
+		r12 = (r5 >> 0x2);
+		if (r12 < r6) {
+			mmio_write_32(DBSC_DBPDRGA_0, 0xB2 + i * 0x20);
+			r2 = mmio_read_32(DBSC_DBPDRGD_0) & 0xFFFFFFF8;
+			mmio_write_32(DBSC_DBPDRGA_0, 0xB2 + i * 0x20);
+			mmio_write_32(DBSC_DBPDRGD_0, r2 | ((r7 + 0x1) & 0x7));
+			mmio_write_32(DBSC_DBPDRGA_0, 0xB0 + i * 0x20);
+			r2 = mmio_read_32(DBSC_DBPDRGD_0) & 0xFFFFFF00;
+			mmio_write_32(DBSC_DBPDRGA_0, 0xB0 + i * 0x20);
+			mmio_write_32(DBSC_DBPDRGD_0, r2 | ((r6 - r12) & 0xFF));
+		} else {
+			mmio_write_32(DBSC_DBPDRGA_0, 0xB2 + i * 0x20);
+			r2 = mmio_read_32(DBSC_DBPDRGD_0) & 0xFFFFFFF8;
+			mmio_write_32(DBSC_DBPDRGA_0, 0xB2 + i * 0x20);
+			mmio_write_32(DBSC_DBPDRGD_0, r2 | (r7 & 0x7));
+			mmio_write_32(DBSC_DBPDRGA_0, 0xB0 + i * 0x20);
+			r2 = mmio_read_32(DBSC_DBPDRGD_0) & 0xFFFFFF00;
+			mmio_write_32(DBSC_DBPDRGA_0, 0xB0 + i * 0x20);
+			mmio_write_32(DBSC_DBPDRGD_0, r2 | ((r6 + r5 +
+						     (r5 >> 1) + r12) & 0xFF));
+		}
+	}
+
+	/*
+	 * Initial_Step5-2_7-2( Rd bit Rd eye )
+	 */
+	if (pdqsr_ctl == 0) {
+		mmio_write_32(DBSC_DBPDRGA_0, 0x000000A0);
+		mmio_write_32(DBSC_DBPDRGD_0, 0x7C0002C5);
+		mmio_write_32(DBSC_DBPDRGA_0, 0x000000C0);
+		mmio_write_32(DBSC_DBPDRGD_0, 0x7C0002C5);
+		mmio_write_32(DBSC_DBPDRGA_0, 0x000000E0);
+		mmio_write_32(DBSC_DBPDRGD_0, 0x7C0002C5);
+		mmio_write_32(DBSC_DBPDRGA_0, 0x00000100);
+		mmio_write_32(DBSC_DBPDRGD_0, 0x7C0002C5);
+	}
+
+	/* PDR always off */
+	if (pdr_ctl == 1) {
+		mmio_write_32(DBSC_DBPDRGA_0, 0x000000A3);
+		mmio_write_32(DBSC_DBPDRGD_0, 0x00000008);
+		mmio_write_32(DBSC_DBPDRGA_0, 0x000000C3);
+		mmio_write_32(DBSC_DBPDRGD_0, 0x00000008);
+		mmio_write_32(DBSC_DBPDRGA_0, 0x000000E3);
+		mmio_write_32(DBSC_DBPDRGD_0, 0x00000008);
+		mmio_write_32(DBSC_DBPDRGA_0, 0x00000103);
+		mmio_write_32(DBSC_DBPDRGD_0, 0x00000008);
+	}
+
+	mmio_write_32(DBSC_DBPDRGA_0, 0x00000001);
+	mmio_write_32(DBSC_DBPDRGD_0, 0x00015001);
+	mmio_write_32(DBSC_DBPDRGA_0, 0x00000006);
+	while (!(mmio_read_32(DBSC_DBPDRGD_0) & BIT(0)))
+		;
+
+	if (lcdl_ctl == 1) {
+		for (i = 0; i < 4; i++) {
+			mmio_write_32(DBSC_DBPDRGA_0, 0xB0 + i * 0x20);
+			dqsgd_0c = mmio_read_32(DBSC_DBPDRGD_0) & 0xFF;
+			mmio_write_32(DBSC_DBPDRGA_0, 0xB1 + i * 0x20);
+			bdlcount_0c = (mmio_read_32(DBSC_DBPDRGD_0) & 0xFF00) >>
+					8;
+			bdlcount_0c_div2 = bdlcount_0c >> 1;
+			bdlcount_0c_div4 = bdlcount_0c >> 2;
+			bdlcount_0c_div8 = bdlcount_0c >> 3;
+			bdlcount_0c_div16 = bdlcount_0c >> 4;
+
+			if (ddr_md == 0) {	/* 1584Mbps */
+				lcdl_judge1 = bdlcount_0c_div2 +
+					      bdlcount_0c_div4 +
+					      bdlcount_0c_div8;
+				lcdl_judge2 = bdlcount_0c +
+					      bdlcount_0c_div4 +
+					      bdlcount_0c_div16;
+			} else {		/* 1856Mbps */
+				lcdl_judge1 = bdlcount_0c_div2 +
+					      bdlcount_0c_div4;
+				lcdl_judge2 = bdlcount_0c +
+					      bdlcount_0c_div4;
+			}
+
+			if (dqsgd_0c <= lcdl_judge1)
+				continue;
+
+			if (dqsgd_0c <= lcdl_judge2) {
+				mmio_write_32(DBSC_DBPDRGA_0, 0xB0 + i * 0x20);
+				regval = mmio_read_32(DBSC_DBPDRGD_0) &
+						0xFFFFFF00;
+				mmio_write_32(DBSC_DBPDRGD_0,
+					      (dqsgd_0c - bdlcount_0c_div8) |
+					      regval);
+			} else {
+				mmio_write_32(DBSC_DBPDRGA_0, 0xB0 + i * 0x20);
+				regval = mmio_read_32(DBSC_DBPDRGD_0) &
+						0xFFFFFF00;
+				mmio_write_32(DBSC_DBPDRGD_0, regval);
+				mmio_write_32(DBSC_DBPDRGA_0, 0xB2 + i * 0x20);
+				gatesl_0c = mmio_read_32(DBSC_DBPDRGD_0) & 0x7;
+				mmio_write_32(DBSC_DBPDRGA_0, 0xB2 + i * 0x20);
+				regval = mmio_read_32(DBSC_DBPDRGD_0) &
+						0xFFFFFFF8;
+				mmio_write_32(DBSC_DBPDRGD_0, regval |
+							     (gatesl_0c + 1));
+				mmio_write_32(DBSC_DBPDRGA_0, 0xAF + i * 0x20);
+				regval = (mmio_read_32(DBSC_DBPDRGD_0));
+				rdqsd_0c = (regval & 0xFF00) >> 8;
+				rdqsnd_0c = (regval & 0xFF0000) >> 16;
+				mmio_write_32(DBSC_DBPDRGA_0, 0xAF + i * 0x20);
+				mmio_write_32(DBSC_DBPDRGD_0,
+					      (regval & 0xFF0000FF) |
+					      ((rdqsd_0c +
+						bdlcount_0c_div4) << 8) |
+					      ((rdqsnd_0c +
+						bdlcount_0c_div4) << 16));
+				mmio_write_32(DBSC_DBPDRGA_0, 0xAA + i * 0x20);
+				regval = (mmio_read_32(DBSC_DBPDRGD_0));
+				rbd_0c[0] = (regval) & 0x1f;
+				rbd_0c[1] = (regval >> 8) & 0x1f;
+				rbd_0c[2] = (regval >> 16) & 0x1f;
+				rbd_0c[3] = (regval >> 24) & 0x1f;
+				mmio_write_32(DBSC_DBPDRGA_0, 0xAA + i * 0x20);
+				regval = mmio_read_32(DBSC_DBPDRGD_0) &
+					0xE0E0E0E0;
+				for (j = 0; j < 4; j++) {
+					rbd_0c[j] = rbd_0c[j] +
+						    bdlcount_0c_div4;
+					if (rbd_0c[j] > 0x1F)
+						rbd_0c[j] = 0x1F;
+					regval = regval | (rbd_0c[j] << 8 * j);
+				}
+				mmio_write_32(DBSC_DBPDRGD_0, regval);
+				mmio_write_32(DBSC_DBPDRGA_0, 0xAB + i * 0x20);
+				regval = (mmio_read_32(DBSC_DBPDRGD_0));
+				rbd_0c[0] = (regval) & 0x1f;
+				rbd_0c[1] = (regval >> 8) & 0x1f;
+				rbd_0c[2] = (regval >> 16) & 0x1f;
+				rbd_0c[3] = (regval >> 24) & 0x1f;
+				mmio_write_32(DBSC_DBPDRGA_0, 0xAB + i * 0x20);
+				regval = mmio_read_32(DBSC_DBPDRGD_0) &
+					0xE0E0E0E0;
+				for (j = 0; j < 4; j++) {
+					rbd_0c[j] = rbd_0c[j] +
+						    bdlcount_0c_div4;
+					if (rbd_0c[j] > 0x1F)
+						rbd_0c[j] = 0x1F;
+					regval = regval | (rbd_0c[j] << 8 * j);
+				}
+				mmio_write_32(DBSC_DBPDRGD_0, regval);
+			}
+		}
+		mmio_write_32(DBSC_DBPDRGA_0, 0x2);
+		mmio_write_32(DBSC_DBPDRGD_0, 0x7D81E37);
+	}
+
+	mmio_write_32(DBSC_DBPDRGA_0, 0x00000003);
+	if (byp_ctl == 1)
+		mmio_write_32(DBSC_DBPDRGD_0, 0x0380C720);
+	else
+		mmio_write_32(DBSC_DBPDRGD_0, 0x0380C700);
+
+	mmio_write_32(DBSC_DBPDRGA_0, 0x00000007);
+	while (mmio_read_32(DBSC_DBPDRGD_0) & BIT(30))
+		;
+
+	mmio_write_32(DBSC_DBPDRGA_0, 0x00000021);
+	mmio_write_32(DBSC_DBPDRGD_0, 0x0024643E);
+
+	mmio_write_32(DBSC_DBBUS0CNF1, 0x00000010);
+	mmio_write_32(DBSC_DBCALCNF, (64000000 / REFRESH_RATE) + 0x01000000);
+	/* Select setting value in bps */
+	if (ddr_md == 0) {	/* 1584Mbps */
+		mmio_write_32(DBSC_DBRFCNF1,
+			      (REFRESH_RATE * 99 / 125) + 0x00080000);
+	} else {		/* 1856Mbps */
+		mmio_write_32(DBSC_DBRFCNF1,
+			      (REFRESH_RATE * 116 / 125) + 0x00080000);
+	}
+
+	mmio_write_32(DBSC_DBRFCNF2, 0x00010000);
+	mmio_write_32(DBSC_DBDFICUPDCNF, 0x40100001);
+	mmio_write_32(DBSC_DBRFEN, 0x00000001);
+	mmio_write_32(DBSC_DBACEN, 0x00000001);
+
+	if (pdqsr_ctl == 1) {
+		mmio_write_32(0xE67F0018, 0x00000001);
+		regval = mmio_read_32(0x40000000);
+		mmio_write_32(DBSC_DBPDRGA_0, 0x00000000);
+		mmio_write_32(DBSC_DBPDRGD_0, regval);
+		mmio_write_32(DBSC_DBPDRGA_0, 0x000000A0);
+		mmio_write_32(DBSC_DBPDRGD_0, 0x7C0002C5);
+		mmio_write_32(DBSC_DBPDRGA_0, 0x000000C0);
+		mmio_write_32(DBSC_DBPDRGD_0, 0x7C0002C5);
+		mmio_write_32(DBSC_DBPDRGA_0, 0x000000E0);
+		mmio_write_32(DBSC_DBPDRGD_0, 0x7C0002C5);
+		mmio_write_32(DBSC_DBPDRGA_0, 0x00000100);
+		mmio_write_32(DBSC_DBPDRGD_0, 0x7C0002C5);
+	}
+
+	/* PDR dynamic */
+	if (pdr_ctl == 1) {
+		mmio_write_32(DBSC_DBPDRGA_0, 0x000000A3);
+		mmio_write_32(DBSC_DBPDRGD_0, 0x00000000);
+		mmio_write_32(DBSC_DBPDRGA_0, 0x000000C3);
+		mmio_write_32(DBSC_DBPDRGD_0, 0x00000000);
+		mmio_write_32(DBSC_DBPDRGA_0, 0x000000E3);
+		mmio_write_32(DBSC_DBPDRGD_0, 0x00000000);
+		mmio_write_32(DBSC_DBPDRGA_0, 0x00000103);
+		mmio_write_32(DBSC_DBPDRGD_0, 0x00000000);
+	}
+
+	/*
+	 * Initial_Step9( Initial End )
+	 */
+	mmio_write_32(DBSC_DBPDLK_0, 0x00000000);
+	mmio_write_32(DBSC_DBSYSCNT0, 0x00000000);
+
+#ifdef ddr_qos_init_setting /* only for non qos_init */
+	mmio_write_32(DBSC_DBSYSCNT0, 0x00001234);
+	mmio_write_32(DBSC_DBCAM0CNF1, 0x00043218);
+	mmio_write_32(DBSC_DBCAM0CNF2, 0x000000F4);
+	mmio_write_32(DBSC_DBSCHCNT0, 0x000f0037);
+	mmio_write_32(DBSC_DBSCHSZ0, 0x00000001);
+	mmio_write_32(DBSC_DBSCHRW0, 0x22421111);
+	mmio_write_32(DBSC_SCFCTST2, 0x012F1123);
+	mmio_write_32(DBSC_DBSCHQOS00, 0x00000F00);
+	mmio_write_32(DBSC_DBSCHQOS01, 0x00000B00);
+	mmio_write_32(DBSC_DBSCHQOS02, 0x00000000);
+	mmio_write_32(DBSC_DBSCHQOS03, 0x00000000);
+	mmio_write_32(DBSC_DBSCHQOS40, 0x00000300);
+	mmio_write_32(DBSC_DBSCHQOS41, 0x000002F0);
+	mmio_write_32(DBSC_DBSCHQOS42, 0x00000200);
+	mmio_write_32(DBSC_DBSCHQOS43, 0x00000100);
+	mmio_write_32(DBSC_DBSCHQOS90, 0x00000100);
+	mmio_write_32(DBSC_DBSCHQOS91, 0x000000F0);
+	mmio_write_32(DBSC_DBSCHQOS92, 0x000000A0);
+	mmio_write_32(DBSC_DBSCHQOS93, 0x00000040);
+	mmio_write_32(DBSC_DBSCHQOS130, 0x00000100);
+	mmio_write_32(DBSC_DBSCHQOS131, 0x000000F0);
+	mmio_write_32(DBSC_DBSCHQOS132, 0x000000A0);
+	mmio_write_32(DBSC_DBSCHQOS133, 0x00000040);
+	mmio_write_32(DBSC_DBSCHQOS140, 0x000000C0);
+	mmio_write_32(DBSC_DBSCHQOS141, 0x000000B0);
+	mmio_write_32(DBSC_DBSCHQOS142, 0x00000080);
+	mmio_write_32(DBSC_DBSCHQOS143, 0x00000040);
+	mmio_write_32(DBSC_DBSCHQOS150, 0x00000040);
+	mmio_write_32(DBSC_DBSCHQOS151, 0x00000030);
+	mmio_write_32(DBSC_DBSCHQOS152, 0x00000020);
+	mmio_write_32(DBSC_DBSCHQOS153, 0x00000010);
+
+	if (pdqsr_ctl == 0)
+		mmio_write_32(0xE67F0018, 0x00000001);
+
+	mmio_write_32(DBSC_DBSYSCNT0, 0x00000000);
+#endif
+
+	return 1;
+}
+
+static uint32_t recovery_from_backup_mode(uint32_t ddr_backup)
+{
+	/*
+	 * recovery_Step0(DBSC Setting 1) / same "init_ddr"
+	 */
+	uint32_t r2, r5, r6, r7, r12, i;
+	uint32_t ddr_md;
+	uint32_t err;
+	uint32_t regval, j;
+	uint32_t dqsgd_0c, bdlcount_0c, bdlcount_0c_div2, bdlcount_0c_div4;
+	uint32_t bdlcount_0c_div8, bdlcount_0c_div16;
+	uint32_t gatesl_0c, rdqsd_0c, rdqsnd_0c, rbd_0c[4];
+	uint32_t pdqsr_ctl, lcdl_ctl, lcdl_judge1, lcdl_judge2;
+	uint32_t pdr_ctl;
+	uint32_t byp_ctl;
+
+	if ((mmio_read_32(0xFFF00044) & 0x000000FF) == 0x00000000) {
+		pdqsr_ctl = 1;
+		lcdl_ctl = 1;
+		pdr_ctl = 1;
+		byp_ctl = 1;
+	} else {
+		pdqsr_ctl = 0;
+		lcdl_ctl = 0;
+		pdr_ctl = 0;
+		byp_ctl = 0;
+	}
+
+	/* Judge the DDR bit rate (ddr_md : 0 = 1584Mbps, 1 = 1856Mbps) */
+	ddr_md = (mmio_read_32(RST_MODEMR) >> 19) & BIT(0);
+
+	/* 1584Mbps setting */
+	if (ddr_md == 0) {
+		mmio_write_32(CPG_CPGWPR, 0x5A5AFFFF);
+		mmio_write_32(CPG_CPGWPCR, 0xA5A50000);
+
+		mmio_write_32(CPG_SRCR4, 0x20000000);
+
+		mmio_write_32(0xE61500DC, 0xe2200000);	/* Change to 1584Mbps */
+		while (!(mmio_read_32(CPG_PLLECR) & BIT(11)))
+			;
+
+		mmio_write_32(CPG_SRSTCLR4, 0x20000000);
+
+		mmio_write_32(CPG_CPGWPCR, 0xA5A50001);
+	}
+
+	mmio_write_32(DBSC_DBSYSCNT0, 0x00001234);
+	mmio_write_32(DBSC_DBKIND, 0x00000007);
+
+#if RCAR_DRAM_DDR3L_MEMCONF == 0
+	mmio_write_32(DBSC_DBMEMCONF_0_0, 0x0f030a02);
+#else
+	mmio_write_32(DBSC_DBMEMCONF_0_0, 0x10030a02);
+#endif
+
+#if RCAR_DRAM_DDR3L_MEMDUAL == 1
+	r2 = mmio_read_32(0xE6790614);
+	mmio_write_32(0xE6790614, r2 | 0x3); /* MCS1_N/MODT1 are activated. */
+#endif
+
+	mmio_write_32(DBSC_DBPHYCONF0, 0x00000001);
+
+	/* Select setting value in bps */
+	if (ddr_md == 0) {	/* 1584Mbps */
+		mmio_write_32(DBSC_DBTR0, 0x0000000B);
+		mmio_write_32(DBSC_DBTR1, 0x00000008);
+	} else {		/* 1856Mbps */
+		mmio_write_32(DBSC_DBTR0, 0x0000000D);
+		mmio_write_32(DBSC_DBTR1, 0x00000009);
+	}
+
+	mmio_write_32(DBSC_DBTR2, 0x00000000);
+
+	/* Select setting value in bps */
+	if (ddr_md == 0) {	/* 1584Mbps */
+		mmio_write_32(DBSC_DBTR3, 0x0000000B);
+		mmio_write_32(DBSC_DBTR4, 0x000B000B);
+		mmio_write_32(DBSC_DBTR5, 0x00000027);
+		mmio_write_32(DBSC_DBTR6, 0x0000001C);
+	} else {		/* 1856Mbps */
+		mmio_write_32(DBSC_DBTR3, 0x0000000D);
+		mmio_write_32(DBSC_DBTR4, 0x000D000D);
+		mmio_write_32(DBSC_DBTR5, 0x0000002D);
+		mmio_write_32(DBSC_DBTR6, 0x00000020);
+	}
+
+	mmio_write_32(DBSC_DBTR7, 0x00060006);
+
+	/* Select setting value in bps */
+	if (ddr_md == 0) {	/* 1584Mbps */
+		mmio_write_32(DBSC_DBTR8, 0x00000020);
+		mmio_write_32(DBSC_DBTR9, 0x00000006);
+		mmio_write_32(DBSC_DBTR10, 0x0000000C);
+		mmio_write_32(DBSC_DBTR11, 0x0000000A);
+		mmio_write_32(DBSC_DBTR12, 0x00120012);
+		mmio_write_32(DBSC_DBTR13, 0x000000CE);
+		mmio_write_32(DBSC_DBTR14, 0x00140005);
+		mmio_write_32(DBSC_DBTR15, 0x00050004);
+		mmio_write_32(DBSC_DBTR16, 0x071F0305);
+		mmio_write_32(DBSC_DBTR17, 0x040C0000);
+	} else {		/* 1856Mbps */
+		mmio_write_32(DBSC_DBTR8, 0x00000021);
+		mmio_write_32(DBSC_DBTR9, 0x00000007);
+		mmio_write_32(DBSC_DBTR10, 0x0000000E);
+		mmio_write_32(DBSC_DBTR11, 0x0000000C);
+		mmio_write_32(DBSC_DBTR12, 0x00140014);
+		mmio_write_32(DBSC_DBTR13, 0x000000F2);
+		mmio_write_32(DBSC_DBTR14, 0x00170006);
+		mmio_write_32(DBSC_DBTR15, 0x00060005);
+		mmio_write_32(DBSC_DBTR16, 0x09210507);
+		mmio_write_32(DBSC_DBTR17, 0x040E0000);
+	}
+
+	mmio_write_32(DBSC_DBTR18, 0x00000200);
+
+	/* Select setting value in bps */
+	if (ddr_md == 0) {	/* 1584Mbps */
+		mmio_write_32(DBSC_DBTR19, 0x01000040);
+		mmio_write_32(DBSC_DBTR20, 0x020000D6);
+	} else {		/* 1856Mbps */
+		mmio_write_32(DBSC_DBTR19, 0x0129004B);
+		mmio_write_32(DBSC_DBTR20, 0x020000FB);
+	}
+
+	mmio_write_32(DBSC_DBTR21, 0x00040004);
+	mmio_write_32(DBSC_DBBL, 0x00000000);
+	mmio_write_32(DBSC_DBODT0, 0x00000001);
+	mmio_write_32(DBSC_DBADJ0, 0x00000001);
+	mmio_write_32(DBSC_DBSYSCONF1, 0x00000002);
+	mmio_write_32(DBSC_DBDFICNT_0, 0x00000010);
+	mmio_write_32(DBSC_DBBCAMDIS, 0x00000001);
+	mmio_write_32(DBSC_DBSCHRW1, 0x00000046);
+
+	/* Select setting value in bps */
+	if (ddr_md == 0) {	/* 1584Mbps */
+		mmio_write_32(DBSC_SCFCTST0, 0x0D050B03);
+		mmio_write_32(DBSC_SCFCTST1, 0x0306030C);
+	} else {		/* 1856Mbps */
+		mmio_write_32(DBSC_SCFCTST0, 0x0C050B03);
+		mmio_write_32(DBSC_SCFCTST1, 0x0305030C);
+	}
+
+	/*
+	 * recovery_Step1(PHY setting 1)
+	 */
+	mmio_write_32(DBSC_DBPDLK_0, 0x0000A55A);
+	mmio_write_32(DBSC_DBCMD, 0x01840001);
+	mmio_write_32(DBSC_DBCMD, 0x0A840000);
+	mmio_write_32(DBSC_DBPDRGA_0, 0x00000008);	/* DDR_PLLCR */
+	mmio_write_32(DBSC_DBPDRGD_0, 0x000B8000);
+	mmio_write_32(DBSC_DBPDRGA_0, 0x00000003);	/* DDR_PGCR1 */
+	if (byp_ctl == 1)
+		mmio_write_32(DBSC_DBPDRGD_0, 0x0780C720);
+	else
+		mmio_write_32(DBSC_DBPDRGD_0, 0x0780C700);
+
+	mmio_write_32(DBSC_DBPDRGA_0, 0x00000020);	/* DDR_DXCCR */
+	mmio_write_32(DBSC_DBPDRGD_0, 0x00181884);
+	mmio_write_32(DBSC_DBPDRGA_0, 0x0000001A);	/* DDR_ACIOCR0 */
+	mmio_write_32(DBSC_DBPDRGD_0, 0x33C03C10);
+	mmio_write_32(DBSC_DBPDRGA_0, 0x00000007);
+	while (!(mmio_read_32(DBSC_DBPDRGD_0) & BIT(30)))
+		;
+
+	mmio_write_32(DBSC_DBPDRGA_0, 0x00000004);
+
+	/* Select setting value in bps */
+	if (ddr_md == 0) {	/* 1584Mbps */
+		mmio_write_32(DBSC_DBPDRGD_0, (REFRESH_RATE * 792 / 125) -
+					     400 + 0x08B00000);
+	} else {		/* 1856Mbps */
+		mmio_write_32(DBSC_DBPDRGD_0, (REFRESH_RATE * 928 / 125) -
+					     400 + 0x0A300000);
+	}
+
+	mmio_write_32(DBSC_DBPDRGA_0, 0x00000022);
+	mmio_write_32(DBSC_DBPDRGD_0, 0x1000040B);
+	mmio_write_32(DBSC_DBPDRGA_0, 0x00000023);
+
+	/* Select setting value in bps */
+	if (ddr_md == 0)	/* 1584Mbps */
+		mmio_write_32(DBSC_DBPDRGD_0, 0x2D9C0B66);
+	else			/* 1856Mbps */
+		mmio_write_32(DBSC_DBPDRGD_0, 0x35A00D77);
+
+	mmio_write_32(DBSC_DBPDRGA_0, 0x00000024);
+
+	/* Select setting value in bps */
+	if (ddr_md == 0)	/* 1584Mbps */
+		mmio_write_32(DBSC_DBPDRGD_0, 0x2A88B400);
+	else			/* 1856Mbps */
+		mmio_write_32(DBSC_DBPDRGD_0, 0x2A8A2C28);
+
+	mmio_write_32(DBSC_DBPDRGA_0, 0x00000025);
+
+	/* Select setting value in bps */
+	if (ddr_md == 0)	/* 1584Mbps */
+		mmio_write_32(DBSC_DBPDRGD_0, 0x30005200);
+	else			/* 1856Mbps */
+		mmio_write_32(DBSC_DBPDRGD_0, 0x30005E00);
+
+	mmio_write_32(DBSC_DBPDRGA_0, 0x00000026);
+
+	/* Select setting value in bps */
+	if (ddr_md == 0)	/* 1584Mbps */
+		mmio_write_32(DBSC_DBPDRGD_0, 0x0014A9C9);
+	else			/* 1856Mbps */
+		mmio_write_32(DBSC_DBPDRGD_0, 0x0014CB49);
+
+	mmio_write_32(DBSC_DBPDRGA_0, 0x00000027);
+
+	/* Select setting value in bps */
+	if (ddr_md == 0)	/* 1584Mbps */
+		mmio_write_32(DBSC_DBPDRGD_0, 0x00000D70);
+	else			/* 1856Mbps */
+		mmio_write_32(DBSC_DBPDRGD_0, 0x00000F14);
+
+	mmio_write_32(DBSC_DBPDRGA_0, 0x00000028);
+	mmio_write_32(DBSC_DBPDRGD_0, 0x00000046);
+	mmio_write_32(DBSC_DBPDRGA_0, 0x00000029);
+
+	/* Select setting value in bps */
+	if (ddr_md == 0) {	/* 1584Mbps */
+		if (REFRESH_RATE > 3900)
+			mmio_write_32(DBSC_DBPDRGD_0, 0x18);	/* [7]SRT=0 */
+		else
+			mmio_write_32(DBSC_DBPDRGD_0, 0x98);	/* [7]SRT=1 */
+	} else {	/* 1856Mbps */
+		if (REFRESH_RATE > 3900)
+			mmio_write_32(DBSC_DBPDRGD_0, 0x20);	/* [7]SRT=0 */
+		else
+			mmio_write_32(DBSC_DBPDRGD_0, 0xA0);	/* [7]SRT=1 */
+	}
+
+	mmio_write_32(DBSC_DBPDRGA_0, 0x0000002C);
+	mmio_write_32(DBSC_DBPDRGD_0, 0x81003047);
+	mmio_write_32(DBSC_DBPDRGA_0, 0x00000091);
+	mmio_write_32(DBSC_DBPDRGD_0, 0x0007BB6B);
+	mmio_write_32(DBSC_DBPDRGA_0, 0x00000095);
+	mmio_write_32(DBSC_DBPDRGD_0, 0x0007BBAD);
+	mmio_write_32(DBSC_DBPDRGA_0, 0x00000099);
+	mmio_write_32(DBSC_DBPDRGD_0, 0x0007BB6B);
+	mmio_write_32(DBSC_DBPDRGA_0, 0x00000021);	/* DDR_DSGCR */
+	mmio_write_32(DBSC_DBPDRGD_0, 0x0024641E);
+	mmio_write_32(DBSC_DBPDRGA_0, 0x00000006);	/* DDR_PGSR0 */
+	while (!(mmio_read_32(DBSC_DBPDRGD_0) & BIT(0)))
+		;
+
+	mmio_write_32(DBSC_DBPDRGA_0, 0x00000001);	/* DDR_PIR */
+	mmio_write_32(DBSC_DBPDRGD_0, 0x40010000);
+
+	mmio_write_32(DBSC_DBPDRGA_0, 0x00000006);	/* DDR_PGSR0 */
+	while (!(mmio_read_32(DBSC_DBPDRGD_0) & BIT(0)))
+		;
+
+	mmio_write_32(DBSC_DBPDRGA_0, 0x00000092);	/* DDR_ZQ0DR */
+	mmio_write_32(DBSC_DBPDRGD_0, 0xC2C59AB5);
+	mmio_write_32(DBSC_DBPDRGA_0, 0x00000096);	/* DDR_ZQ1DR */
+	mmio_write_32(DBSC_DBPDRGD_0, 0xC4285FBF);
+	mmio_write_32(DBSC_DBPDRGA_0, 0x0000009A);	/* DDR_ZQ2DR */
+	mmio_write_32(DBSC_DBPDRGD_0, 0xC2C59AB5);
+	mmio_write_32(DBSC_DBPDRGA_0, 0x00000090);	/* DDR_ZQCR */
+
+	/* Select setting value in bps */
+	if (ddr_md == 0)	/* 1584Mbps */
+		mmio_write_32(DBSC_DBPDRGD_0, 0x0C058900);
+	else			/* 1856Mbps */
+		mmio_write_32(DBSC_DBPDRGD_0, 0x0C058A00);
+
+	mmio_write_32(DBSC_DBPDRGA_0, 0x00000090);	/* DDR_ZQCR */
+
+	/* Select setting value in bps */
+	if (ddr_md == 0)	/* 1584Mbps */
+		mmio_write_32(DBSC_DBPDRGD_0, 0x04058900);
+	else			/* 1856Mbps */
+		mmio_write_32(DBSC_DBPDRGD_0, 0x04058A00);
+
+	mmio_write_32(DBSC_DBPDRGA_0, 0x00000001);	/* DDR_PIR */
+	mmio_write_32(DBSC_DBPDRGD_0, 0x00050001);
+
+	mmio_write_32(DBSC_DBPDRGA_0, 0x00000006);	/* DDR_PGSR0 */
+	while (!(mmio_read_32(DBSC_DBPDRGD_0) & BIT(0)))
+		;
+
+	/* ddr backupmode end */
+	if (ddr_backup)
+		NOTICE("BL2: [WARM_BOOT]\n");
+	else
+		NOTICE("BL2: [COLD_BOOT]\n");
+
+	err = rcar_dram_update_boot_status(ddr_backup);
+	if (err) {
+		NOTICE("BL2: [BOOT_STATUS_UPDATE_ERROR]\n");
+		return INITDRAM_ERR_I;
+	}
+
+	mmio_write_32(DBSC_DBPDRGA_0, 0x00000092);	/* DDR_ZQ0DR */
+	mmio_write_32(DBSC_DBPDRGD_0, 0x02C59AB5);
+	mmio_write_32(DBSC_DBPDRGA_0, 0x00000096);	/* DDR_ZQ1DR */
+	mmio_write_32(DBSC_DBPDRGD_0, 0x04285FBF);
+	mmio_write_32(DBSC_DBPDRGA_0, 0x0000009A);	/* DDR_ZQ2DR */
+	mmio_write_32(DBSC_DBPDRGD_0, 0x02C59AB5);
+
+	mmio_write_32(DBSC_DBPDRGA_0, 0x00000001);	/* DDR_PIR */
+	mmio_write_32(DBSC_DBPDRGD_0, 0x08000000);
+
+	mmio_write_32(DBSC_DBPDRGA_0, 0x00000001);	/* DDR_PIR */
+	mmio_write_32(DBSC_DBPDRGD_0, 0x00000003);
+
+	mmio_write_32(DBSC_DBPDRGA_0, 0x00000006);	/* DDR_PGSR0 */
+	while (!(mmio_read_32(DBSC_DBPDRGD_0) & BIT(0)))
+		;
+
+	mmio_write_32(DBSC_DBPDRGA_0, 0x00000001);	/* DDR_PIR */
+	mmio_write_32(DBSC_DBPDRGD_0, 0x80010000);
+
+	mmio_write_32(DBSC_DBPDRGA_0, 0x00000006);	/* DDR_PGSR0 */
+	while (!(mmio_read_32(DBSC_DBPDRGD_0) & BIT(0)))
+		;
+
+	mmio_write_32(DBSC_DBPDRGA_0, 0x00000001);	/* DDR_PIR */
+	mmio_write_32(DBSC_DBPDRGD_0, 0x00010073);
+
+	mmio_write_32(DBSC_DBPDRGA_0, 0x00000006);	/* DDR_PGSR0 */
+	while (!(mmio_read_32(DBSC_DBPDRGD_0) & BIT(0)))
+		;
+
+	mmio_write_32(DBSC_DBPDRGA_0, 0x00000090);	/* DDR_ZQCR */
+
+	/* Select setting value in bps */
+	if (ddr_md == 0)	/* 1584Mbps */
+		mmio_write_32(DBSC_DBPDRGD_0, 0x0C058900);
+	else			/* 1856Mbps */
+		mmio_write_32(DBSC_DBPDRGD_0, 0x0C058A00);
+
+	mmio_write_32(DBSC_DBPDRGA_0, 0x00000090);	/* DDR_ZQCR */
+
+	/* Select setting value in bps */
+	if (ddr_md == 0)	/* 1584Mbps */
+		mmio_write_32(DBSC_DBPDRGD_0, 0x04058900);
+	else			/* 1856Mbps */
+		mmio_write_32(DBSC_DBPDRGD_0, 0x04058A00);
+
+	mmio_write_32(DBSC_DBPDRGA_0, 0x0000000C);
+	mmio_write_32(DBSC_DBPDRGD_0, 0x18000040);
+
+	/*
+	 * recovery_Step2(PHY setting 2)
+	 */
+	mmio_write_32(DBSC_DBPDRGA_0, 0x00000006);
+	while (!(mmio_read_32(DBSC_DBPDRGD_0) & BIT(0)))
+		;
+
+	mmio_write_32(DBSC_DBPDRGA_0, 0x000000A7);
+	mmio_write_32(DBSC_DBPDRGD_0, 0x0D0D0D0D);
+	mmio_write_32(DBSC_DBPDRGA_0, 0x000000A8);
+	mmio_write_32(DBSC_DBPDRGD_0, 0x0D0D0D0D);
+	mmio_write_32(DBSC_DBPDRGA_0, 0x000000A9);
+	mmio_write_32(DBSC_DBPDRGD_0, 0x000D0D0D);
+	mmio_write_32(DBSC_DBPDRGA_0, 0x000000C7);
+	mmio_write_32(DBSC_DBPDRGD_0, 0x0D0D0D0D);
+	mmio_write_32(DBSC_DBPDRGA_0, 0x000000C8);
+	mmio_write_32(DBSC_DBPDRGD_0, 0x0D0D0D0D);
+	mmio_write_32(DBSC_DBPDRGA_0, 0x000000C9);
+	mmio_write_32(DBSC_DBPDRGD_0, 0x000D0D0D);
+	mmio_write_32(DBSC_DBPDRGA_0, 0x000000E7);
+	mmio_write_32(DBSC_DBPDRGD_0, 0x0D0D0D0D);
+	mmio_write_32(DBSC_DBPDRGA_0, 0x000000E8);
+	mmio_write_32(DBSC_DBPDRGD_0, 0x0D0D0D0D);
+	mmio_write_32(DBSC_DBPDRGA_0, 0x000000E9);
+	mmio_write_32(DBSC_DBPDRGD_0, 0x000D0D0D);
+	mmio_write_32(DBSC_DBPDRGA_0, 0x00000107);
+	mmio_write_32(DBSC_DBPDRGD_0, 0x0D0D0D0D);
+	mmio_write_32(DBSC_DBPDRGA_0, 0x00000108);
+	mmio_write_32(DBSC_DBPDRGD_0, 0x0D0D0D0D);
+	mmio_write_32(DBSC_DBPDRGA_0, 0x00000109);
+	mmio_write_32(DBSC_DBPDRGD_0, 0x000D0D0D);
+
+	mmio_write_32(DBSC_DBCALCNF, (64000000 / REFRESH_RATE) + 0x01000000);
+	mmio_write_32(DBSC_DBBUS0CNF1, 0x00000010);
+
+	/* Select setting value in bps */
+	if (ddr_md == 0) {	/* 1584Mbps */
+		mmio_write_32(DBSC_DBRFCNF1,
+			      (REFRESH_RATE * 99 / 125) + 0x00080000);
+	} else {			/* 1856Mbps */
+		mmio_write_32(DBSC_DBRFCNF1,
+			      (REFRESH_RATE * 116 / 125) + 0x00080000);
+	}
+
+	mmio_write_32(DBSC_DBRFCNF2, 0x00010000);
+	mmio_write_32(DBSC_DBRFEN, 0x00000001);
+	mmio_write_32(DBSC_DBCMD, 0x0A840001);
+	while (mmio_read_32(DBSC_DBWAIT) & BIT(0))
+		;
+
+	mmio_write_32(DBSC_DBCMD, 0x00000000);
+
+	mmio_write_32(DBSC_DBCMD, 0x04840010);
+	while (mmio_read_32(DBSC_DBWAIT) & BIT(0))
+		;
+
+	mmio_write_32(DBSC_DBPDRGA_0, 0x00000006);	/* DDR_PGSR0 */
+	while (!(mmio_read_32(DBSC_DBPDRGD_0) & BIT(0)))
+		;
+
+	mmio_write_32(DBSC_DBPDRGA_0, 0x00000001);	/* DDR_PIR */
+	mmio_write_32(DBSC_DBPDRGD_0, 0x00010701);
+
+	mmio_write_32(DBSC_DBPDRGA_0, 0x00000006);	/* DDR_PGSR0 */
+	while (!(mmio_read_32(DBSC_DBPDRGD_0) & BIT(0)))
+		;
+
+	for (i = 0; i < 4; i++) {
+		mmio_write_32(DBSC_DBPDRGA_0, 0xB1 + i * 0x20);
+		r5 = (mmio_read_32(DBSC_DBPDRGD_0) & 0xFF00) >> 0x8;
+		mmio_write_32(DBSC_DBPDRGA_0, 0xB4 + i * 0x20);
+		r6 = mmio_read_32(DBSC_DBPDRGD_0) & 0xFF;
+		mmio_write_32(DBSC_DBPDRGA_0, 0xB3 + i * 0x20);
+		r7 = mmio_read_32(DBSC_DBPDRGD_0) & 0x7;
+
+		if (r6 > 0) {
+			mmio_write_32(DBSC_DBPDRGA_0, 0xB2 + i * 0x20);
+			r2 = mmio_read_32(DBSC_DBPDRGD_0) & 0xFFFFFFF8;
+			mmio_write_32(DBSC_DBPDRGA_0, 0xB2 + i * 0x20);
+			mmio_write_32(DBSC_DBPDRGD_0, r2 | ((r7 + 0x1) & 0x7));
+			mmio_write_32(DBSC_DBPDRGA_0, 0xB0 + i * 0x20);
+			r2 = mmio_read_32(DBSC_DBPDRGD_0) & 0xFFFFFF00;
+			mmio_write_32(DBSC_DBPDRGA_0, 0xB0 + i * 0x20);
+			mmio_write_32(DBSC_DBPDRGD_0, r2 | r6);
+		} else {
+			mmio_write_32(DBSC_DBPDRGA_0, 0xB2 + i * 0x20);
+			r2 = mmio_read_32(DBSC_DBPDRGD_0) & 0xFFFFFFF8;
+			mmio_write_32(DBSC_DBPDRGA_0, 0xB2 + i * 0x20);
+			mmio_write_32(DBSC_DBPDRGD_0, r2 | r7);
+			mmio_write_32(DBSC_DBPDRGA_0, 0xB0 + i * 0x20);
+			r2 = mmio_read_32(DBSC_DBPDRGD_0) & 0xFFFFFF00;
+			mmio_write_32(DBSC_DBPDRGA_0, 0xB0 + i * 0x20);
+			mmio_write_32(DBSC_DBPDRGD_0,
+				      r2 | ((r6 + (r5 << 1)) & 0xFF));
+		}
+	}
+
+	mmio_write_32(DBSC_DBPDRGA_0, 0x00000005);
+	mmio_write_32(DBSC_DBPDRGD_0, 0xC1AA00C0);
+
+	if (pdqsr_ctl == 0) {
+		mmio_write_32(DBSC_DBPDRGA_0, 0x000000A0);
+		mmio_write_32(DBSC_DBPDRGD_0, 0x7C0002C5);
+		mmio_write_32(DBSC_DBPDRGA_0, 0x000000C0);
+		mmio_write_32(DBSC_DBPDRGD_0, 0x7C0002C5);
+		mmio_write_32(DBSC_DBPDRGA_0, 0x000000E0);
+		mmio_write_32(DBSC_DBPDRGD_0, 0x7C0002C5);
+		mmio_write_32(DBSC_DBPDRGA_0, 0x00000100);
+		mmio_write_32(DBSC_DBPDRGD_0, 0x7C0002C5);
+	}
+
+	/* PDR always off */
+	if (pdr_ctl == 1) {
+		mmio_write_32(DBSC_DBPDRGA_0, 0x000000A3);
+		mmio_write_32(DBSC_DBPDRGD_0, 0x00000008);
+		mmio_write_32(DBSC_DBPDRGA_0, 0x000000C3);
+		mmio_write_32(DBSC_DBPDRGD_0, 0x00000008);
+		mmio_write_32(DBSC_DBPDRGA_0, 0x000000E3);
+		mmio_write_32(DBSC_DBPDRGD_0, 0x00000008);
+		mmio_write_32(DBSC_DBPDRGA_0, 0x00000103);
+		mmio_write_32(DBSC_DBPDRGD_0, 0x00000008);
+	}
+
+	mmio_write_32(DBSC_DBPDRGA_0, 0x00000001);
+	mmio_write_32(DBSC_DBPDRGD_0, 0x00010801);
+	mmio_write_32(DBSC_DBPDRGA_0, 0x00000006);
+	while (!(mmio_read_32(DBSC_DBPDRGD_0) & BIT(0)))
+		;
+
+	mmio_write_32(DBSC_DBPDRGA_0, 0x00000005);
+	mmio_write_32(DBSC_DBPDRGD_0, 0xC1AA00D8);
+
+	mmio_write_32(DBSC_DBPDRGA_0, 0x00000001);
+	mmio_write_32(DBSC_DBPDRGD_0, 0x00011001);
+	mmio_write_32(DBSC_DBPDRGA_0, 0x00000006);
+	while (!(mmio_read_32(DBSC_DBPDRGD_0) & BIT(0)))
+		;
+
+	if (pdqsr_ctl == 1) {
+		mmio_write_32(DBSC_DBPDRGA_0, 0x000000A0);
+		mmio_write_32(DBSC_DBPDRGD_0, 0x7C0002C5);
+		mmio_write_32(DBSC_DBPDRGA_0, 0x000000C0);
+		mmio_write_32(DBSC_DBPDRGD_0, 0x7C0002C5);
+		mmio_write_32(DBSC_DBPDRGA_0, 0x000000E0);
+		mmio_write_32(DBSC_DBPDRGD_0, 0x7C0002C5);
+		mmio_write_32(DBSC_DBPDRGA_0, 0x00000100);
+		mmio_write_32(DBSC_DBPDRGD_0, 0x7C0002C5);
+	}
+
+	/* PDR dynamic */
+	if (pdr_ctl == 1) {
+		mmio_write_32(DBSC_DBPDRGA_0, 0x000000A3);
+		mmio_write_32(DBSC_DBPDRGD_0, 0x00000000);
+		mmio_write_32(DBSC_DBPDRGA_0, 0x000000C3);
+		mmio_write_32(DBSC_DBPDRGD_0, 0x00000000);
+		mmio_write_32(DBSC_DBPDRGA_0, 0x000000E3);
+		mmio_write_32(DBSC_DBPDRGD_0, 0x00000000);
+		mmio_write_32(DBSC_DBPDRGA_0, 0x00000103);
+		mmio_write_32(DBSC_DBPDRGD_0, 0x00000000);
+	}
+
+	mmio_write_32(DBSC_DBPDRGA_0, 0x00000001);
+	mmio_write_32(DBSC_DBPDRGD_0, 0x00012001);
+	mmio_write_32(DBSC_DBPDRGA_0, 0x00000006);
+	while (!(mmio_read_32(DBSC_DBPDRGD_0) & BIT(0)))
+		;
+
+	if (pdqsr_ctl == 1) {
+		mmio_write_32(DBSC_DBPDRGA_0, 0x000000A0);
+		mmio_write_32(DBSC_DBPDRGD_0, 0x7C000285);
+		mmio_write_32(DBSC_DBPDRGA_0, 0x000000C0);
+		mmio_write_32(DBSC_DBPDRGD_0, 0x7C000285);
+		mmio_write_32(DBSC_DBPDRGA_0, 0x000000E0);
+		mmio_write_32(DBSC_DBPDRGD_0, 0x7C000285);
+		mmio_write_32(DBSC_DBPDRGA_0, 0x00000100);
+		mmio_write_32(DBSC_DBPDRGD_0, 0x7C000285);
+	}
+
+	/* PDR always off */
+	if (pdr_ctl == 1) {
+		mmio_write_32(DBSC_DBPDRGA_0, 0x000000A3);
+		mmio_write_32(DBSC_DBPDRGD_0, 0x00000008);
+		mmio_write_32(DBSC_DBPDRGA_0, 0x000000C3);
+		mmio_write_32(DBSC_DBPDRGD_0, 0x00000008);
+		mmio_write_32(DBSC_DBPDRGA_0, 0x000000E3);
+		mmio_write_32(DBSC_DBPDRGD_0, 0x00000008);
+		mmio_write_32(DBSC_DBPDRGA_0, 0x00000103);
+		mmio_write_32(DBSC_DBPDRGD_0, 0x00000008);
+	}
+
+	mmio_write_32(DBSC_DBPDRGA_0, 0x00000001);
+	mmio_write_32(DBSC_DBPDRGD_0, 0x00014001);
+	mmio_write_32(DBSC_DBPDRGA_0, 0x00000006);
+	while (!(mmio_read_32(DBSC_DBPDRGD_0) & BIT(0)))
+		;
+
+	if (pdqsr_ctl == 1) {
+		mmio_write_32(DBSC_DBPDRGA_0, 0x000000A0);
+		mmio_write_32(DBSC_DBPDRGD_0, 0x7C0002C5);
+		mmio_write_32(DBSC_DBPDRGA_0, 0x000000C0);
+		mmio_write_32(DBSC_DBPDRGD_0, 0x7C0002C5);
+		mmio_write_32(DBSC_DBPDRGA_0, 0x000000E0);
+		mmio_write_32(DBSC_DBPDRGD_0, 0x7C0002C5);
+		mmio_write_32(DBSC_DBPDRGA_0, 0x00000100);
+		mmio_write_32(DBSC_DBPDRGD_0, 0x7C0002C5);
+	}
+
+	/* PDR dynamic */
+	if (pdr_ctl == 1) {
+		mmio_write_32(DBSC_DBPDRGA_0, 0x000000A3);
+		mmio_write_32(DBSC_DBPDRGD_0, 0x00000000);
+		mmio_write_32(DBSC_DBPDRGA_0, 0x000000C3);
+		mmio_write_32(DBSC_DBPDRGD_0, 0x00000000);
+		mmio_write_32(DBSC_DBPDRGA_0, 0x000000E3);
+		mmio_write_32(DBSC_DBPDRGD_0, 0x00000000);
+		mmio_write_32(DBSC_DBPDRGA_0, 0x00000103);
+		mmio_write_32(DBSC_DBPDRGD_0, 0x00000000);
+	}
+
+	mmio_write_32(DBSC_DBPDRGA_0, 0x00000001);
+	mmio_write_32(DBSC_DBPDRGD_0, 0x00018001);
+	mmio_write_32(DBSC_DBPDRGA_0, 0x00000006);
+	while (!(mmio_read_32(DBSC_DBPDRGD_0) & BIT(0)))
+		;
+
+	mmio_write_32(DBSC_DBPDRGA_0, 0x000000A0);
+	mmio_write_32(DBSC_DBPDRGD_0, 0x7C000285);
+	mmio_write_32(DBSC_DBPDRGA_0, 0x000000C0);
+	mmio_write_32(DBSC_DBPDRGD_0, 0x7C000285);
+	mmio_write_32(DBSC_DBPDRGA_0, 0x000000E0);
+	mmio_write_32(DBSC_DBPDRGD_0, 0x7C000285);
+	mmio_write_32(DBSC_DBPDRGA_0, 0x00000100);
+	mmio_write_32(DBSC_DBPDRGD_0, 0x7C000285);
+	mmio_write_32(DBSC_DBPDRGA_0, 0x0000002C);
+	mmio_write_32(DBSC_DBPDRGD_0, 0x81003087);
+	mmio_write_32(DBSC_DBPDRGA_0, 0x00000001);
+	mmio_write_32(DBSC_DBPDRGD_0, 0x00010401);
+	mmio_write_32(DBSC_DBPDRGA_0, 0x00000006);
+	while (!(mmio_read_32(DBSC_DBPDRGD_0) & BIT(0)))
+		;
+
+	for (i = 0; i < 4; i++) {
+		mmio_write_32(DBSC_DBPDRGA_0, 0xB1 + i * 0x20);
+		r5 = ((mmio_read_32(DBSC_DBPDRGD_0) & 0xFF00) >> 0x8);
+		mmio_write_32(DBSC_DBPDRGA_0, 0xB4 + i * 0x20);
+		r6 = mmio_read_32(DBSC_DBPDRGD_0) & 0xFF;
+		mmio_write_32(DBSC_DBPDRGA_0, 0xB3 + i * 0x20);
+		r7 = mmio_read_32(DBSC_DBPDRGD_0) & 0x7;
+		r12 = r5 >> 0x2;
+
+		if (r12 < r6) {
+			mmio_write_32(DBSC_DBPDRGA_0, 0xB2 + i * 0x20);
+			r2 = mmio_read_32(DBSC_DBPDRGD_0) & 0xFFFFFFF8;
+			mmio_write_32(DBSC_DBPDRGA_0, 0xB2 + i * 0x20);
+			mmio_write_32(DBSC_DBPDRGD_0, r2 | ((r7 + 0x1) & 0x7));
+			mmio_write_32(DBSC_DBPDRGA_0, 0xB0 + i * 0x20);
+			r2 = mmio_read_32(DBSC_DBPDRGD_0) & 0xFFFFFF00;
+			mmio_write_32(DBSC_DBPDRGA_0, 0xB0 + i * 0x20);
+			mmio_write_32(DBSC_DBPDRGD_0, r2 | ((r6 - r12) & 0xFF));
+		} else {
+			mmio_write_32(DBSC_DBPDRGA_0, 0xB2 + i * 0x20);
+			r2 = mmio_read_32(DBSC_DBPDRGD_0) & 0xFFFFFFF8;
+			mmio_write_32(DBSC_DBPDRGA_0, 0xB2 + i * 0x20);
+			mmio_write_32(DBSC_DBPDRGD_0, r2 | (r7 & 0x7));
+			mmio_write_32(DBSC_DBPDRGA_0, 0xB0 + i * 0x20);
+			r2 = mmio_read_32(DBSC_DBPDRGD_0) & 0xFFFFFF00;
+			mmio_write_32(DBSC_DBPDRGA_0, 0xB0 + i * 0x20);
+			mmio_write_32(DBSC_DBPDRGD_0,
+				      r2 |
+				      ((r6 + r5 + (r5 >> 1) + r12) & 0xFF));
+		}
+	}
+
+	if (pdqsr_ctl == 0) {
+		mmio_write_32(DBSC_DBPDRGA_0, 0x000000A0);
+		mmio_write_32(DBSC_DBPDRGD_0, 0x7C0002C5);
+		mmio_write_32(DBSC_DBPDRGA_0, 0x000000C0);
+		mmio_write_32(DBSC_DBPDRGD_0, 0x7C0002C5);
+		mmio_write_32(DBSC_DBPDRGA_0, 0x000000E0);
+		mmio_write_32(DBSC_DBPDRGD_0, 0x7C0002C5);
+		mmio_write_32(DBSC_DBPDRGA_0, 0x00000100);
+		mmio_write_32(DBSC_DBPDRGD_0, 0x7C0002C5);
+	}
+
+	/* PDR always off */
+	if (pdr_ctl == 1) {
+		mmio_write_32(DBSC_DBPDRGA_0, 0x000000A3);
+		mmio_write_32(DBSC_DBPDRGD_0, 0x00000008);
+		mmio_write_32(DBSC_DBPDRGA_0, 0x000000C3);
+		mmio_write_32(DBSC_DBPDRGD_0, 0x00000008);
+		mmio_write_32(DBSC_DBPDRGA_0, 0x000000E3);
+		mmio_write_32(DBSC_DBPDRGD_0, 0x00000008);
+		mmio_write_32(DBSC_DBPDRGA_0, 0x00000103);
+		mmio_write_32(DBSC_DBPDRGD_0, 0x00000008);
+	}
+
+	mmio_write_32(DBSC_DBPDRGA_0, 0x00000001);
+	mmio_write_32(DBSC_DBPDRGD_0, 0x00015001);
+	mmio_write_32(DBSC_DBPDRGA_0, 0x00000006);
+	while (!(mmio_read_32(DBSC_DBPDRGD_0) & BIT(0)))
+		;
+
+	if (lcdl_ctl == 1) {
+		for (i = 0; i < 4; i++) {
+			mmio_write_32(DBSC_DBPDRGA_0, 0x000000B0 + i * 0x20);
+			dqsgd_0c = mmio_read_32(DBSC_DBPDRGD_0) & 0x000000FF;
+			mmio_write_32(DBSC_DBPDRGA_0, 0x000000B1 + i * 0x20);
+			bdlcount_0c = (mmio_read_32(DBSC_DBPDRGD_0) &
+					0x0000FF00) >> 8;
+			bdlcount_0c_div2 = (bdlcount_0c >> 1);
+			bdlcount_0c_div4 = (bdlcount_0c >> 2);
+			bdlcount_0c_div8 = (bdlcount_0c >> 3);
+			bdlcount_0c_div16 = (bdlcount_0c >> 4);
+
+			if (ddr_md == 0) {	/* 1584Mbps */
+				lcdl_judge1 = bdlcount_0c_div2 +
+					      bdlcount_0c_div4 +
+					      bdlcount_0c_div8;
+				lcdl_judge2 = bdlcount_0c +
+					      bdlcount_0c_div4 +
+					      bdlcount_0c_div16;
+			} else {	/* 1856Mbps */
+				lcdl_judge1 = bdlcount_0c_div2 +
+					      bdlcount_0c_div4;
+				lcdl_judge2 = bdlcount_0c +
+					      bdlcount_0c_div4;
+			}
+
+			if (dqsgd_0c <= lcdl_judge1)
+				continue;
+
+			if (dqsgd_0c <= lcdl_judge2) {
+				mmio_write_32(DBSC_DBPDRGA_0, 0xB0 + i * 0x20);
+				regval = mmio_read_32(DBSC_DBPDRGD_0) &
+						0xFFFFFF00;
+				mmio_write_32(DBSC_DBPDRGD_0,
+					      (dqsgd_0c - bdlcount_0c_div8) |
+					      regval);
+			} else {
+				mmio_write_32(DBSC_DBPDRGA_0, 0xB0 + i * 0x20);
+				regval = mmio_read_32(DBSC_DBPDRGD_0) &
+						0xFFFFFF00;
+				mmio_write_32(DBSC_DBPDRGD_0, regval);
+				mmio_write_32(DBSC_DBPDRGA_0, 0xB2 + i * 0x20);
+				gatesl_0c = mmio_read_32(DBSC_DBPDRGD_0) & 0x7;
+				mmio_write_32(DBSC_DBPDRGA_0, 0xB2 + i * 0x20);
+				regval = mmio_read_32(DBSC_DBPDRGD_0) &
+						0xFFFFFFF8;
+				mmio_write_32(DBSC_DBPDRGD_0,
+					      regval | (gatesl_0c + 1));
+				mmio_write_32(DBSC_DBPDRGA_0, 0xAF + i * 0x20);
+				regval = mmio_read_32(DBSC_DBPDRGD_0);
+				rdqsd_0c = (regval & 0xFF00) >> 8;
+				rdqsnd_0c = (regval & 0xFF0000) >> 16;
+				mmio_write_32(DBSC_DBPDRGA_0, 0xAF + i * 0x20);
+				mmio_write_32(DBSC_DBPDRGD_0,
+					      (regval & 0xFF0000FF) |
+					      ((rdqsd_0c +
+						bdlcount_0c_div4) << 8) |
+					      ((rdqsnd_0c +
+						bdlcount_0c_div4) << 16));
+				mmio_write_32(DBSC_DBPDRGA_0, 0xAA + i * 0x20);
+				regval = (mmio_read_32(DBSC_DBPDRGD_0));
+				rbd_0c[0] = (regval) & 0x1f;
+				rbd_0c[1] = (regval >>  8) & 0x1f;
+				rbd_0c[2] = (regval >> 16) & 0x1f;
+				rbd_0c[3] = (regval >> 24) & 0x1f;
+				mmio_write_32(DBSC_DBPDRGA_0, 0xAA + i * 0x20);
+				regval = mmio_read_32(DBSC_DBPDRGD_0) &
+						0xE0E0E0E0;
+				for (j = 0; j < 4; j++) {
+					rbd_0c[j] = rbd_0c[j] +
+						    bdlcount_0c_div4;
+					if (rbd_0c[j] > 0x1F)
+						rbd_0c[j] = 0x1F;
+					regval = regval | (rbd_0c[j] << 8 * j);
+				}
+				mmio_write_32(DBSC_DBPDRGD_0, regval);
+				mmio_write_32(DBSC_DBPDRGA_0, 0xAB + i * 0x20);
+				regval = (mmio_read_32(DBSC_DBPDRGD_0));
+				rbd_0c[0] = regval & 0x1f;
+				rbd_0c[1] = (regval >> 8) & 0x1f;
+				rbd_0c[2] = (regval >> 16) & 0x1f;
+				rbd_0c[3] = (regval >> 24) & 0x1f;
+				mmio_write_32(DBSC_DBPDRGA_0, 0xAB + i * 0x20);
+				regval = mmio_read_32(DBSC_DBPDRGD_0) &
+						0xE0E0E0E0;
+				for (j = 0; j < 4; j++) {
+					rbd_0c[j] = rbd_0c[j] +
+						    bdlcount_0c_div4;
+					if (rbd_0c[j] > 0x1F)
+						rbd_0c[j] = 0x1F;
+					regval = regval | (rbd_0c[j] << 8 * j);
+				}
+				mmio_write_32(DBSC_DBPDRGD_0, regval);
+			}
+		}
+		mmio_write_32(DBSC_DBPDRGA_0, 0x00000002);
+		mmio_write_32(DBSC_DBPDRGD_0, 0x07D81E37);
+	}
+
+	mmio_write_32(DBSC_DBPDRGA_0, 0x00000003);
+	if (byp_ctl == 1)
+		mmio_write_32(DBSC_DBPDRGD_0, 0x0380C720);
+	else
+		mmio_write_32(DBSC_DBPDRGD_0, 0x0380C700);
+
+	mmio_write_32(DBSC_DBPDRGA_0, 0x00000007);
+	while (mmio_read_32(DBSC_DBPDRGD_0) & BIT(30))
+		;
+	mmio_write_32(DBSC_DBPDRGA_0, 0x00000021);
+	mmio_write_32(DBSC_DBPDRGD_0, 0x0024643E);
+
+	/*
+	 * recovery_Step3(DBSC Setting 2)
+	 */
+	mmio_write_32(DBSC_DBDFICUPDCNF, 0x40100001);
+	mmio_write_32(DBSC_DBACEN, 0x00000001);
+
+	if (pdqsr_ctl == 1) {
+		mmio_write_32(0xE67F0018, 0x00000001);
+		regval = mmio_read_32(0x40000000);
+		mmio_write_32(DBSC_DBPDRGA_0, 0x00000000);
+		mmio_write_32(DBSC_DBPDRGD_0, regval);
+		mmio_write_32(DBSC_DBPDRGA_0, 0x000000A0);
+		mmio_write_32(DBSC_DBPDRGD_0, 0x7C0002C5);
+		mmio_write_32(DBSC_DBPDRGA_0, 0x000000C0);
+		mmio_write_32(DBSC_DBPDRGD_0, 0x7C0002C5);
+		mmio_write_32(DBSC_DBPDRGA_0, 0x000000E0);
+		mmio_write_32(DBSC_DBPDRGD_0, 0x7C0002C5);
+		mmio_write_32(DBSC_DBPDRGA_0, 0x00000100);
+		mmio_write_32(DBSC_DBPDRGD_0, 0x7C0002C5);
+	}
+
+	/* PDR dynamic */
+	if (pdr_ctl == 1) {
+		mmio_write_32(DBSC_DBPDRGA_0, 0x000000A3);
+		mmio_write_32(DBSC_DBPDRGD_0, 0x00000000);
+		mmio_write_32(DBSC_DBPDRGA_0, 0x000000C3);
+		mmio_write_32(DBSC_DBPDRGD_0, 0x00000000);
+		mmio_write_32(DBSC_DBPDRGA_0, 0x000000E3);
+		mmio_write_32(DBSC_DBPDRGD_0, 0x00000000);
+		mmio_write_32(DBSC_DBPDRGA_0, 0x00000103);
+		mmio_write_32(DBSC_DBPDRGD_0, 0x00000000);
+	}
+
+	mmio_write_32(DBSC_DBPDLK_0, 0x00000000);
+	mmio_write_32(DBSC_DBSYSCNT0, 0x00000000);
+
+#ifdef ddr_qos_init_setting /* only for non qos_init */
+	mmio_write_32(DBSC_DBSYSCNT0, 0x00001234);
+	mmio_write_32(DBSC_DBCAM0CNF1, 0x00043218);
+	mmio_write_32(DBSC_DBCAM0CNF2, 0x000000F4);
+	mmio_write_32(DBSC_DBSCHCNT0, 0x000f0037);
+	mmio_write_32(DBSC_DBSCHSZ0, 0x00000001);
+	mmio_write_32(DBSC_DBSCHRW0, 0x22421111);
+	mmio_write_32(DBSC_SCFCTST2, 0x012F1123);
+	mmio_write_32(DBSC_DBSCHQOS00, 0x00000F00);
+	mmio_write_32(DBSC_DBSCHQOS01, 0x00000B00);
+	mmio_write_32(DBSC_DBSCHQOS02, 0x00000000);
+	mmio_write_32(DBSC_DBSCHQOS03, 0x00000000);
+	mmio_write_32(DBSC_DBSCHQOS40, 0x00000300);
+	mmio_write_32(DBSC_DBSCHQOS41, 0x000002F0);
+	mmio_write_32(DBSC_DBSCHQOS42, 0x00000200);
+	mmio_write_32(DBSC_DBSCHQOS43, 0x00000100);
+	mmio_write_32(DBSC_DBSCHQOS90, 0x00000100);
+	mmio_write_32(DBSC_DBSCHQOS91, 0x000000F0);
+	mmio_write_32(DBSC_DBSCHQOS92, 0x000000A0);
+	mmio_write_32(DBSC_DBSCHQOS93, 0x00000040);
+	mmio_write_32(DBSC_DBSCHQOS130, 0x00000100);
+	mmio_write_32(DBSC_DBSCHQOS131, 0x000000F0);
+	mmio_write_32(DBSC_DBSCHQOS132, 0x000000A0);
+	mmio_write_32(DBSC_DBSCHQOS133, 0x00000040);
+	mmio_write_32(DBSC_DBSCHQOS140, 0x000000C0);
+	mmio_write_32(DBSC_DBSCHQOS141, 0x000000B0);
+	mmio_write_32(DBSC_DBSCHQOS142, 0x00000080);
+	mmio_write_32(DBSC_DBSCHQOS143, 0x00000040);
+	mmio_write_32(DBSC_DBSCHQOS150, 0x00000040);
+	mmio_write_32(DBSC_DBSCHQOS151, 0x00000030);
+	mmio_write_32(DBSC_DBSCHQOS152, 0x00000020);
+	mmio_write_32(DBSC_DBSCHQOS153, 0x00000010);
+
+	if (pdqsr_ctl == 0)
+		mmio_write_32(0xE67F0018, 0x00000001);
+
+	mmio_write_32(DBSC_DBSYSCNT0, 0x00000000);
+#endif
+
+	return 1;
+
+} /* recovery_from_backup_mode */
+
+/*
+ * init_ddr : MD19=0,DDR3L,1584Mbps / MD19=1,DDR3L,1856Mbps
+ */
+
+/*
+ * DDR Initialize entry for IPL
+ */
+int32_t rcar_dram_init(void)
+{
+	uint32_t dataL;
+	uint32_t failcount;
+	uint32_t md = 0;
+	uint32_t ddr = 0;
+	uint32_t ddr_backup;
+
+	md = *((volatile uint32_t*)RST_MODEMR);
+	ddr = (md & 0x00080000) >> 19;
+	if (ddr == 0x0)
+		NOTICE("BL2: DDR1584(%s)\n", RCAR_E3_DDR_VERSION);
+	else if (ddr == 0x1)
+		NOTICE("BL2: DDR1856(%s)\n", RCAR_E3_DDR_VERSION);
+
+	rcar_dram_get_boot_status(&ddr_backup);
+
+	if (ddr_backup == DRAM_BOOT_STATUS_WARM)
+		dataL = recovery_from_backup_mode(ddr_backup);	/* WARM boot */
+	else
+		dataL = init_ddr();				/* COLD boot */
+
+	if (dataL == 1)
+		failcount = 0;
+	else
+		failcount = 1;
+
+	if (failcount == 0)
+		return INITDRAM_OK;
+	else
+		return INITDRAM_NG;
+
+}
diff --git a/drivers/renesas/rcar/ddr/ddr_a/ddr_init_v3m.c b/drivers/renesas/rcar/ddr/ddr_a/ddr_init_v3m.c
new file mode 100644
index 000000000..5410771c9
--- /dev/null
+++ b/drivers/renesas/rcar/ddr/ddr_a/ddr_init_v3m.c
@@ -0,0 +1,339 @@
+/*
+ * Copyright (c) 2015-2019, Renesas Electronics Corporation
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <lib/mmio.h>
+#include <lib/utils_def.h>
+#include <stdint.h>
+#include "boot_init_dram.h"
+#include "rcar_def.h"
+#include "../ddr_regs.h"
+
+static uint32_t init_ddr_v3m_1600(void)
+{
+	uint32_t i, r2, r5, r6, r7, r12;
+
+	mmio_write_32(DBSC_DBSYSCNT0, 0x00001234);
+	mmio_write_32(DBSC_DBKIND, 0x00000007);
+#if RCAR_DRAM_DDR3L_MEMCONF == 0
+	mmio_write_32(DBSC_DBMEMCONF_0_0, 0x0f030a02); // 1GB: Eagle
+#else
+	mmio_write_32(DBSC_DBMEMCONF_0_0, 0x10030a02); // 2GB: V3MSK
+#endif
+	mmio_write_32(DBSC_DBPHYCONF0, 0x00000001);
+	mmio_write_32(DBSC_DBTR0, 0x0000000B);
+	mmio_write_32(DBSC_DBTR1, 0x00000008);
+	mmio_write_32(DBSC_DBTR3, 0x0000000B);
+	mmio_write_32(DBSC_DBTR4, 0x000B000B);
+	mmio_write_32(DBSC_DBTR5, 0x00000027);
+	mmio_write_32(DBSC_DBTR6, 0x0000001C);
+	mmio_write_32(DBSC_DBTR7, 0x00060006);
+	mmio_write_32(DBSC_DBTR8, 0x00000020);
+	mmio_write_32(DBSC_DBTR9, 0x00000006);
+	mmio_write_32(DBSC_DBTR10, 0x0000000C);
+	mmio_write_32(DBSC_DBTR11, 0x0000000B);
+	mmio_write_32(DBSC_DBTR12, 0x00120012);
+	mmio_write_32(DBSC_DBTR13, 0x01180118);
+	mmio_write_32(DBSC_DBTR14, 0x00140005);
+	mmio_write_32(DBSC_DBTR15, 0x00050004);
+	mmio_write_32(DBSC_DBTR16, 0x071D0305);
+	mmio_write_32(DBSC_DBTR17, 0x040C0010);
+	mmio_write_32(DBSC_DBTR18, 0x00000200);
+	mmio_write_32(DBSC_DBTR19, 0x01000040);
+	mmio_write_32(DBSC_DBTR20, 0x02000120);
+	mmio_write_32(DBSC_DBTR21, 0x00040004);
+	mmio_write_32(DBSC_DBBL, 0x00000000);
+	mmio_write_32(DBSC_DBODT0, 0x00000001);
+	mmio_write_32(DBSC_DBADJ0, 0x00000001);
+	mmio_write_32(DBSC_DBCAM0CNF1, 0x00082010);
+	mmio_write_32(DBSC_DBCAM0CNF2, 0x00002000);
+	mmio_write_32(DBSC_DBSCHCNT0, 0x080f003f);
+	mmio_write_32(DBSC_DBSCHCNT1, 0x00001010);
+	mmio_write_32(DBSC_DBSCHSZ0, 0x00000001);
+	mmio_write_32(DBSC_DBSCHRW0, 0x00000200);
+	mmio_write_32(DBSC_DBSCHRW1, 0x00000040);
+	mmio_write_32(DBSC_DBSCHQOS40, 0x00000600);
+	mmio_write_32(DBSC_DBSCHQOS41, 0x00000480);
+	mmio_write_32(DBSC_DBSCHQOS42, 0x00000300);
+	mmio_write_32(DBSC_DBSCHQOS43, 0x00000180);
+	mmio_write_32(DBSC_DBSCHQOS90, 0x00000400);
+	mmio_write_32(DBSC_DBSCHQOS91, 0x00000300);
+	mmio_write_32(DBSC_DBSCHQOS92, 0x00000200);
+	mmio_write_32(DBSC_DBSCHQOS93, 0x00000100);
+	mmio_write_32(DBSC_DBSCHQOS130, 0x00000300);
+	mmio_write_32(DBSC_DBSCHQOS131, 0x00000240);
+	mmio_write_32(DBSC_DBSCHQOS132, 0x00000180);
+	mmio_write_32(DBSC_DBSCHQOS133, 0x000000c0);
+	mmio_write_32(DBSC_DBSCHQOS140, 0x00000200);
+	mmio_write_32(DBSC_DBSCHQOS141, 0x00000180);
+	mmio_write_32(DBSC_DBSCHQOS142, 0x00000100);
+	mmio_write_32(DBSC_DBSCHQOS143, 0x00000080);
+	mmio_write_32(DBSC_DBSCHQOS150, 0x00000100);
+	mmio_write_32(DBSC_DBSCHQOS151, 0x000000c0);
+	mmio_write_32(DBSC_DBSCHQOS152, 0x00000080);
+	mmio_write_32(DBSC_DBSCHQOS153, 0x00000040);
+	mmio_write_32(DBSC_DBSYSCONF1, 0x00000002);
+	mmio_write_32(DBSC_DBCAM0CNF1, 0x00040C04);
+	mmio_write_32(DBSC_DBCAM0CNF2, 0x000001c4);
+	mmio_write_32(DBSC_DBSCHSZ0, 0x00000003);
+	mmio_write_32(DBSC_DBSCHRW1, 0x001a0080);
+	mmio_write_32(DBSC_DBDFICNT_0, 0x00000010);
+
+	mmio_write_32(DBSC_DBPDLK_0, 0x0000A55A);
+	mmio_write_32(DBSC_DBCMD, 0x01000001);
+	mmio_write_32(DBSC_DBCMD, 0x08000000);
+	mmio_write_32(DBSC_DBPDRGA_0, 0x00000001);
+	mmio_write_32(DBSC_DBPDRGD_0, 0x80010000);
+	mmio_write_32(DBSC_DBPDRGA_0, 0x00000006);
+	while (!(mmio_read_32(DBSC_DBPDRGD_0) & BIT(0)))
+		;
+
+	mmio_write_32(DBSC_DBPDRGA_0, 0x00000008);
+	mmio_write_32(DBSC_DBPDRGD_0, 0x000B8000);
+	mmio_write_32(DBSC_DBPDRGA_0, 0x00000090);
+	mmio_write_32(DBSC_DBPDRGD_0, 0x04058904);
+	mmio_write_32(DBSC_DBPDRGA_0, 0x00000091);
+	mmio_write_32(DBSC_DBPDRGD_0, 0x0007BB6D);
+	mmio_write_32(DBSC_DBPDRGA_0, 0x00000095);
+	mmio_write_32(DBSC_DBPDRGD_0, 0x0007BB6B);
+	mmio_write_32(DBSC_DBPDRGA_0, 0x00000099);
+	mmio_write_32(DBSC_DBPDRGD_0, 0x0007BB6D);
+	mmio_write_32(DBSC_DBPDRGA_0, 0x00000090);
+	mmio_write_32(DBSC_DBPDRGD_0, 0x04058900);
+	mmio_write_32(DBSC_DBPDRGA_0, 0x00000021);
+	mmio_write_32(DBSC_DBPDRGD_0, 0x0024641E);
+	mmio_write_32(DBSC_DBPDRGA_0, 0x00000001);
+	mmio_write_32(DBSC_DBPDRGD_0, 0x00010073);
+	mmio_write_32(DBSC_DBPDRGA_0, 0x00000006);
+	while (!(mmio_read_32(DBSC_DBPDRGD_0) & BIT(0)))
+		;
+
+	mmio_write_32(DBSC_DBPDRGA_0, 0x00000090);
+	mmio_write_32(DBSC_DBPDRGD_0, 0x0C058900);
+	mmio_write_32(DBSC_DBPDRGA_0, 0x00000090);
+	mmio_write_32(DBSC_DBPDRGD_0, 0x04058900);
+	mmio_write_32(DBSC_DBPDRGA_0, 0x00000006);
+	while (!(mmio_read_32(DBSC_DBPDRGD_0) & BIT(0)))
+		;
+
+	mmio_write_32(DBSC_DBPDRGA_0, 0x00000003);
+	mmio_write_32(DBSC_DBPDRGD_0, 0x0780C700);
+	mmio_write_32(DBSC_DBPDRGA_0, 0x00000007);
+	while (!(mmio_read_32(DBSC_DBPDRGD_0) & BIT(30)))
+		;
+
+	mmio_write_32(DBSC_DBPDRGA_0, 0x00000004);
+	mmio_write_32(DBSC_DBPDRGD_0, 0x08C0C170);
+	mmio_write_32(DBSC_DBPDRGA_0, 0x00000022);
+	mmio_write_32(DBSC_DBPDRGD_0, 0x1000040B);
+	mmio_write_32(DBSC_DBPDRGA_0, 0x00000023);
+	mmio_write_32(DBSC_DBPDRGD_0, 0x2D9C0B66);
+	mmio_write_32(DBSC_DBPDRGA_0, 0x00000024);
+	mmio_write_32(DBSC_DBPDRGD_0, 0x2A88C400);
+	mmio_write_32(DBSC_DBPDRGA_0, 0x00000025);
+	mmio_write_32(DBSC_DBPDRGD_0, 0x30005200);
+	mmio_write_32(DBSC_DBPDRGA_0, 0x00000026);
+	mmio_write_32(DBSC_DBPDRGD_0, 0x0014A9C9);
+	mmio_write_32(DBSC_DBPDRGA_0, 0x00000027);
+	mmio_write_32(DBSC_DBPDRGD_0, 0x00000D70);
+	mmio_write_32(DBSC_DBPDRGA_0, 0x00000028);
+	mmio_write_32(DBSC_DBPDRGD_0, 0x00000004);
+	mmio_write_32(DBSC_DBPDRGA_0, 0x00000029);
+	mmio_write_32(DBSC_DBPDRGD_0, 0x00000018);
+	mmio_write_32(DBSC_DBPDRGA_0, 0x0000002C);
+	mmio_write_32(DBSC_DBPDRGD_0, 0x81003047);
+	mmio_write_32(DBSC_DBPDRGA_0, 0x00000020);
+	mmio_write_32(DBSC_DBPDRGD_0, 0x00181884);
+	mmio_write_32(DBSC_DBPDRGA_0, 0x0000001A);
+	mmio_write_32(DBSC_DBPDRGD_0, 0x13C03C10);
+	mmio_write_32(DBSC_DBPDRGA_0, 0x00000006);
+	while (!(mmio_read_32(DBSC_DBPDRGD_0) & BIT(0)))
+		;
+
+	mmio_write_32(DBSC_DBPDRGA_0, 0x000000A7);
+	mmio_write_32(DBSC_DBPDRGD_0, 0x0D0D0D0D);
+	mmio_write_32(DBSC_DBPDRGA_0, 0x000000A8);
+	mmio_write_32(DBSC_DBPDRGD_0, 0x0D0D0D0D);
+	mmio_write_32(DBSC_DBPDRGA_0, 0x000000A9);
+	mmio_write_32(DBSC_DBPDRGD_0, 0x000D0D0D);
+	mmio_write_32(DBSC_DBPDRGA_0, 0x000000C7);
+	mmio_write_32(DBSC_DBPDRGD_0, 0x0D0D0D0D);
+	mmio_write_32(DBSC_DBPDRGA_0, 0x000000C8);
+	mmio_write_32(DBSC_DBPDRGD_0, 0x0D0D0D0D);
+	mmio_write_32(DBSC_DBPDRGA_0, 0x000000C9);
+	mmio_write_32(DBSC_DBPDRGD_0, 0x000D0D0D);
+	mmio_write_32(DBSC_DBPDRGA_0, 0x000000E7);
+	mmio_write_32(DBSC_DBPDRGD_0, 0x0D0D0D0D);
+	mmio_write_32(DBSC_DBPDRGA_0, 0x000000E8);
+	mmio_write_32(DBSC_DBPDRGD_0, 0x0D0D0D0D);
+	mmio_write_32(DBSC_DBPDRGA_0, 0x000000E9);
+	mmio_write_32(DBSC_DBPDRGD_0, 0x000D0D0D);
+	mmio_write_32(DBSC_DBPDRGA_0, 0x00000107);
+	mmio_write_32(DBSC_DBPDRGD_0, 0x0D0D0D0D);
+	mmio_write_32(DBSC_DBPDRGA_0, 0x00000108);
+	mmio_write_32(DBSC_DBPDRGD_0, 0x0D0D0D0D);
+	mmio_write_32(DBSC_DBPDRGA_0, 0x00000109);
+	mmio_write_32(DBSC_DBPDRGD_0, 0x000D0D0D);
+	mmio_write_32(DBSC_DBPDRGA_0, 0x00000001);
+	mmio_write_32(DBSC_DBPDRGD_0, 0x00010181);
+	mmio_write_32(DBSC_DBCMD, 0x08000001);
+	mmio_write_32(DBSC_DBPDRGA_0, 0x00000006);
+	while (!(mmio_read_32(DBSC_DBPDRGD_0) & BIT(0)))
+		;
+
+	mmio_write_32(DBSC_DBPDRGA_0, 0x00000001);
+	mmio_write_32(DBSC_DBPDRGD_0, 0x00010601);
+	mmio_write_32(DBSC_DBPDRGA_0, 0x00000006);
+	while (!(mmio_read_32(DBSC_DBPDRGD_0) & BIT(0)))
+		;
+
+	for (i = 0; i < 4; i++) {
+		mmio_write_32(DBSC_DBPDRGA_0, 0xB1 + i * 0x20);
+		r5 = (mmio_read_32(DBSC_DBPDRGD_0) & 0xFF00) >> 8;
+		mmio_write_32(DBSC_DBPDRGA_0, 0xB4 + i * 0x20);
+		r6 = mmio_read_32(DBSC_DBPDRGD_0) & 0xFF;
+		mmio_write_32(DBSC_DBPDRGA_0, 0xB3 + i * 0x20);
+		r7 = mmio_read_32(DBSC_DBPDRGD_0) & 0x7;
+
+		if (r6 > 0) {
+			mmio_write_32(DBSC_DBPDRGA_0, 0xB2 + i * 0x20);
+			r2 = (mmio_read_32(DBSC_DBPDRGD_0) & 0xFFFFFFF8);
+
+			mmio_write_32(DBSC_DBPDRGA_0, 0xB2 + i * 0x20);
+			mmio_write_32(DBSC_DBPDRGD_0, ((r7 + 1) & 0x7) | r2);
+			mmio_write_32(DBSC_DBPDRGA_0, 0xB0 + i * 0x20);
+			r2 = (mmio_read_32(DBSC_DBPDRGD_0) & 0xFFFFFF00);
+			mmio_write_32(DBSC_DBPDRGA_0, 0xB0 + i * 0x20);
+			mmio_write_32(DBSC_DBPDRGD_0, r2 | r6);
+		} else {
+			mmio_write_32(DBSC_DBPDRGA_0, 0xB2 + i * 0x20);
+			r2 = (mmio_read_32(DBSC_DBPDRGD_0) & 0xFFFFFFF8);
+			mmio_write_32(DBSC_DBPDRGA_0, 0xB2 + i * 0x20);
+			mmio_write_32(DBSC_DBPDRGD_0, r2 | r7);
+
+			mmio_write_32(DBSC_DBPDRGA_0, 0xB0 + i * 0x20);
+			r2 = (mmio_read_32(DBSC_DBPDRGD_0) & 0xFFFFFF00);
+			mmio_write_32(DBSC_DBPDRGA_0, 0xB0 + i * 0x20);
+			mmio_write_32(DBSC_DBPDRGD_0, r2 |
+						     (((r5 << 1) + r6) & 0xFF));
+		}
+	}
+
+	mmio_write_32(DBSC_DBPDRGA_0, 0x00000005);
+	mmio_write_32(DBSC_DBPDRGD_0, 0xC1AA00A0);
+	mmio_write_32(DBSC_DBPDRGA_0, 0x000000A0);
+	mmio_write_32(DBSC_DBPDRGD_0, 0x7C0002C5);
+	mmio_write_32(DBSC_DBPDRGA_0, 0x000000C0);
+	mmio_write_32(DBSC_DBPDRGD_0, 0x7C0002C5);
+	mmio_write_32(DBSC_DBPDRGA_0, 0x000000E0);
+	mmio_write_32(DBSC_DBPDRGD_0, 0x7C0002C5);
+	mmio_write_32(DBSC_DBPDRGA_0, 0x00000100);
+	mmio_write_32(DBSC_DBPDRGD_0, 0x7C0002C5);
+	mmio_write_32(DBSC_DBPDRGA_0, 0x00000001);
+	mmio_write_32(DBSC_DBPDRGD_0, 0x00010801);
+	mmio_write_32(DBSC_DBPDRGA_0, 0x00000006);
+	while (!(mmio_read_32(DBSC_DBPDRGD_0) & BIT(0)))
+		;
+
+	mmio_write_32(DBSC_DBPDRGA_0, 0x00000005);
+	mmio_write_32(DBSC_DBPDRGD_0, 0xC1AA00B8);
+	mmio_write_32(DBSC_DBPDRGA_0, 0x00000001);
+	mmio_write_32(DBSC_DBPDRGD_0, 0x0001F001);
+	mmio_write_32(DBSC_DBPDRGA_0, 0x00000006);
+	while (!(mmio_read_32(DBSC_DBPDRGD_0) & BIT(0)))
+		;
+
+	mmio_write_32(DBSC_DBPDRGA_0, 0x000000A0);
+	mmio_write_32(DBSC_DBPDRGD_0, 0x7C000285);
+	mmio_write_32(DBSC_DBPDRGA_0, 0x000000C0);
+	mmio_write_32(DBSC_DBPDRGD_0, 0x7C000285);
+	mmio_write_32(DBSC_DBPDRGA_0, 0x000000E0);
+	mmio_write_32(DBSC_DBPDRGD_0, 0x7C000285);
+	mmio_write_32(DBSC_DBPDRGA_0, 0x00000100);
+	mmio_write_32(DBSC_DBPDRGD_0, 0x7C000285);
+	mmio_write_32(DBSC_DBPDRGA_0, 0x0000002C);
+	mmio_write_32(DBSC_DBPDRGD_0, 0x81003087);
+	mmio_write_32(DBSC_DBPDRGA_0, 0x00000001);
+	mmio_write_32(DBSC_DBPDRGD_0, 0x00010401);
+	mmio_write_32(DBSC_DBPDRGA_0, 0x00000006);
+	while (!(mmio_read_32(DBSC_DBPDRGD_0) & BIT(0)))
+		;
+
+	for (i = 0; i < 4; i++) {
+		mmio_write_32(DBSC_DBPDRGA_0, 0xB1 + i * 0x20);
+		r5 = (mmio_read_32(DBSC_DBPDRGD_0) & 0xFF00) >> 8;
+		mmio_write_32(DBSC_DBPDRGA_0, 0xB4 + i * 0x20);
+		r6 = (mmio_read_32(DBSC_DBPDRGD_0) & 0xFF);
+
+		mmio_write_32(DBSC_DBPDRGA_0, 0xB3 + i * 0x20);
+		r7 = (mmio_read_32(DBSC_DBPDRGD_0) & 0x7);
+		r12 = (r5 >> 2);
+		if (r6 - r12 > 0) {
+			mmio_write_32(DBSC_DBPDRGA_0, 0xB2 + i * 0x20);
+			r2 = (mmio_read_32(DBSC_DBPDRGD_0) & 0xFFFFFFF8);
+
+			mmio_write_32(DBSC_DBPDRGA_0, 0xB2 + i * 0x20);
+			mmio_write_32(DBSC_DBPDRGD_0, ((r7 + 1) & 0x7) | r2);
+			mmio_write_32(DBSC_DBPDRGA_0, 0xB0 + i * 0x20);
+			r2 = (mmio_read_32(DBSC_DBPDRGD_0) & 0xFFFFFF00);
+
+			mmio_write_32(DBSC_DBPDRGA_0, 0xB0 + i * 0x20);
+			mmio_write_32(DBSC_DBPDRGD_0, ((r6 - r12) & 0xFF) | r2);
+		} else {
+			mmio_write_32(DBSC_DBPDRGA_0, 0xB2 + i * 0x20);
+			r2 = (mmio_read_32(DBSC_DBPDRGD_0) & 0xFFFFFFF8);
+			mmio_write_32(DBSC_DBPDRGA_0, 0xB2 + i * 0x20);
+			mmio_write_32(DBSC_DBPDRGD_0, (r7 & 0x7) | r2);
+			mmio_write_32(DBSC_DBPDRGA_0, 0xB0 + i * 0x20);
+			r2 = (mmio_read_32(DBSC_DBPDRGD_0) & 0xFFFFFF00);
+			mmio_write_32(DBSC_DBPDRGA_0, 0xB0 + i * 0x20);
+			mmio_write_32(DBSC_DBPDRGD_0, r2 |
+						     ((r6 + r5 +
+						      (r5 >> 1) + r12) & 0xFF));
+		}
+	}
+
+	mmio_write_32(DBSC_DBPDRGA_0, 0x000000A0);
+	mmio_write_32(DBSC_DBPDRGD_0, 0x7C0002C5);
+	mmio_write_32(DBSC_DBPDRGA_0, 0x000000C0);
+	mmio_write_32(DBSC_DBPDRGD_0, 0x7C0002C5);
+	mmio_write_32(DBSC_DBPDRGA_0, 0x000000E0);
+	mmio_write_32(DBSC_DBPDRGD_0, 0x7C0002C5);
+	mmio_write_32(DBSC_DBPDRGA_0, 0x00000100);
+	mmio_write_32(DBSC_DBPDRGD_0, 0x7C0002C5);
+	mmio_write_32(DBSC_DBPDRGA_0, 0x00000001);
+	mmio_write_32(DBSC_DBPDRGD_0, 0x00015001);
+	mmio_write_32(DBSC_DBPDRGA_0, 0x00000006);
+	while (!(mmio_read_32(DBSC_DBPDRGD_0) & BIT(0)))
+		;
+
+	mmio_write_32(DBSC_DBPDRGA_0, 0x00000003);
+	mmio_write_32(DBSC_DBPDRGD_0, 0x0380C700);
+	mmio_write_32(DBSC_DBPDRGA_0, 0x00000007);
+	while (mmio_read_32(DBSC_DBPDRGD_0) & BIT(30))
+		;
+	mmio_write_32(DBSC_DBPDRGA_0, 0x00000021);
+	mmio_write_32(DBSC_DBPDRGD_0, 0x0024643E);
+
+	mmio_write_32(DBSC_DBBUS0CNF1, 0x00000000);
+	mmio_write_32(DBSC_DBBUS0CNF0, 0x00010001);
+	mmio_write_32(DBSC_DBCALCNF, 0x0100200E);
+	mmio_write_32(DBSC_DBRFCNF1, 0x00081860);
+	mmio_write_32(DBSC_DBRFCNF2, 0x00010000);
+	mmio_write_32(DBSC_DBDFICUPDCNF, 0x40100001);
+	mmio_write_32(DBSC_DBRFEN, 0x00000001);
+	mmio_write_32(DBSC_DBACEN, 0x00000001);
+	mmio_write_32(DBSC_DBPDLK_0, 0x00000000);
+	mmio_write_32(0xE67F0024, 0x00000001);
+	mmio_write_32(DBSC_DBSYSCNT0, 0x00000000);
+
+	return INITDRAM_OK;
+}
+
+int32_t rcar_dram_init(void)
+{
+	return init_ddr_v3m_1600();
+}
diff --git a/drivers/staging/renesas/rcar/ddr/ddr_b/boot_init_dram.c b/drivers/renesas/rcar/ddr/ddr_b/boot_init_dram.c
index 89d666ce6..1d6e83a2c 100644
--- a/drivers/staging/renesas/rcar/ddr/ddr_b/boot_init_dram.c
+++ b/drivers/renesas/rcar/ddr/ddr_b/boot_init_dram.c
@@ -1,5 +1,6 @@
 /*
- * Copyright (c) 2015-2019, Renesas Electronics Corporation. All rights reserved.
+ * Copyright (c) 2015-2019, Renesas Electronics Corporation.
+ * All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -20,20 +21,19 @@
 #include "boot_init_dram.h"
 #include "dram_sub_func.h"
 #include "micro_delay.h"
+#include "rcar_def.h"
 
 #define DDR_BACKUPMODE
 #define FATAL_MSG(x) NOTICE(x)
 
-/*******************************************************************************
- *	variables
- ******************************************************************************/
+/* variables */
 #ifdef RCAR_DDR_FIXED_LSI_TYPE
 #ifndef RCAR_AUTO
 #define RCAR_AUTO	99
-#define RCAR_H3	0
-#define RCAR_M3	1
+#define RCAR_H3		0
+#define RCAR_M3		1
 #define RCAR_M3N	2
-#define RCAR_E3	3		/*  NON */
+#define RCAR_E3		3	/* NON */
 #define RCAR_H3N	4
 
 #define RCAR_CUT_10	0
@@ -44,42 +44,41 @@
 #ifndef RCAR_LSI
 #define RCAR_LSI	RCAR_AUTO
 #endif
-#if(RCAR_LSI==RCAR_AUTO)
-static uint32_t Prr_Product;
-static uint32_t Prr_Cut;
+
+#if (RCAR_LSI == RCAR_AUTO)
+static uint32_t prr_product;
+static uint32_t prr_cut;
 #else
-#if(RCAR_LSI==RCAR_H3)
-static const uint32_t Prr_Product = PRR_PRODUCT_H3;
-#elif(RCAR_LSI==RCAR_M3)
-static const uint32_t Prr_Product = PRR_PRODUCT_M3;
-#elif(RCAR_LSI==RCAR_M3N)
-static const uint32_t Prr_Product = PRR_PRODUCT_M3N;
-#elif(RCAR_LSI==RCAR_H3N)
-static const uint32_t Prr_Product = PRR_PRODUCT_H3;
+#if (RCAR_LSI == RCAR_H3)
+static const uint32_t prr_product = PRR_PRODUCT_H3;
+#elif(RCAR_LSI == RCAR_M3)
+static const uint32_t prr_product = PRR_PRODUCT_M3;
+#elif(RCAR_LSI == RCAR_M3N)
+static const uint32_t prr_product = PRR_PRODUCT_M3N;
+#elif(RCAR_LSI == RCAR_H3N)
+static const uint32_t prr_product = PRR_PRODUCT_H3;
 #endif /* RCAR_LSI */
 
 #ifndef RCAR_LSI_CUT
-static uint32_t Prr_Cut;
+static uint32_t prr_cut;
 #else /* RCAR_LSI_CUT */
-#if(RCAR_LSI_CUT==RCAR_CUT_10)
-static const uint32_t Prr_Cut = PRR_PRODUCT_10;
-#elif(RCAR_LSI_CUT==RCAR_CUT_11)
-static const uint32_t Prr_Cut = PRR_PRODUCT_11;
-#elif(RCAR_LSI_CUT==RCAR_CUT_20)
-static const uint32_t Prr_Cut = PRR_PRODUCT_20;
-#elif(RCAR_LSI_CUT==RCAR_CUT_30)
-static const uint32_t Prr_Cut = PRR_PRODUCT_30;
+#if (RCAR_LSI_CUT == RCAR_CUT_10)
+static const uint32_t prr_cut = PRR_PRODUCT_10;
+#elif(RCAR_LSI_CUT == RCAR_CUT_11)
+static const uint32_t prr_cut = PRR_PRODUCT_11;
+#elif(RCAR_LSI_CUT == RCAR_CUT_20)
+static const uint32_t prr_cut = PRR_PRODUCT_20;
+#elif(RCAR_LSI_CUT == RCAR_CUT_30)
+static const uint32_t prr_cut = PRR_PRODUCT_30;
 #endif /* RCAR_LSI_CUT */
 #endif /* RCAR_LSI_CUT */
 #endif /* RCAR_AUTO_NON */
 #else /* RCAR_DDR_FIXED_LSI_TYPE */
-static uint32_t Prr_Product;
-static uint32_t Prr_Cut;
+static uint32_t prr_product;
+static uint32_t prr_cut;
 #endif /* RCAR_DDR_FIXED_LSI_TYPE */
 
-char *pRCAR_DDR_VERSION;
-uint32_t _cnf_BOARDTYPE;
-static const uint32_t *pDDR_REGDEF_TBL;
+static const uint32_t *p_ddr_regdef_tbl;
 static uint32_t brd_clk;
 static uint32_t brd_clkdiv;
 static uint32_t brd_clkdiva;
@@ -87,11 +86,11 @@ static uint32_t ddr_mbps;
 static uint32_t ddr_mbpsdiv;
 static uint32_t ddr_tccd;
 static uint32_t ddr_phycaslice;
-static const struct _boardcnf *Boardcnf;
+static const struct _boardcnf *board_cnf;
 static uint32_t ddr_phyvalid;
 static uint32_t ddr_density[DRAM_CH_CNT][CS_CNT];
-static uint32_t ch_have_this_cs[CS_CNT] __attribute__ ((aligned(64)));
-static uint32_t rdqdm_dly[DRAM_CH_CNT][CS_CNT][SLICE_CNT * 2][9];
+static uint32_t ch_have_this_cs[CS_CNT] __aligned(64);
+static uint32_t rdqdm_dly[DRAM_CH_CNT][CSAB_CNT][SLICE_CNT * 2][9];
 static uint32_t max_density;
 static uint32_t ddr0800_mul;
 static uint32_t ddr_mul;
@@ -118,10 +117,10 @@ static uint32_t _cnf_DDR_PHY_ADR_V_REGSET[DDR_PHY_REGSET_MAX];
 static uint32_t _cnf_DDR_PHY_ADR_I_REGSET[DDR_PHY_REGSET_MAX];
 static uint32_t _cnf_DDR_PHY_ADR_G_REGSET[DDR_PHY_REGSET_MAX];
 static uint32_t _cnf_DDR_PI_REGSET[DDR_PI_REGSET_MAX];
-static uint32_t Pll3Mode;
+static uint32_t pll3_mode;
 static uint32_t loop_max;
 #ifdef DDR_BACKUPMODE
-uint32_t ddrBackup;
+uint32_t ddr_backup;
 /* #define DDR_BACKUPMODE_HALF           //for Half channel(ch0,1 only) */
 #endif
 
@@ -129,7 +128,9 @@ uint32_t ddrBackup;
 #define OPERATING_FREQ			(400U)	/* Mhz */
 #define BASE_SUB_SLOT_NUM		(0x6U)
 #define SUB_SLOT_CYCLE			(0x7EU)	/* 126 */
-#define QOSWT_WTSET0_CYCLE		((SUB_SLOT_CYCLE * BASE_SUB_SLOT_NUM * 1000U)/OPERATING_FREQ)	/* unit:ns */
+#define QOSWT_WTSET0_CYCLE		\
+	((SUB_SLOT_CYCLE * BASE_SUB_SLOT_NUM * 1000U) / \
+	OPERATING_FREQ)	/* unit:ns */
 
 uint32_t get_refperiod(void)
 {
@@ -155,8 +156,8 @@ static const uint32_t _reg_PHY_RX_CAL_X[_reg_PHY_RX_CAL_X_NUM] = {
 };
 
 #define _reg_PHY_CLK_WRX_SLAVE_DELAY_NUM 10
-static const uint32_t
-    _reg_PHY_CLK_WRX_SLAVE_DELAY[_reg_PHY_CLK_WRX_SLAVE_DELAY_NUM] = {
+static const uint32_t _reg_PHY_CLK_WRX_SLAVE_DELAY
+	[_reg_PHY_CLK_WRX_SLAVE_DELAY_NUM] = {
 	_reg_PHY_CLK_WRDQ0_SLAVE_DELAY,
 	_reg_PHY_CLK_WRDQ1_SLAVE_DELAY,
 	_reg_PHY_CLK_WRDQ2_SLAVE_DELAY,
@@ -170,8 +171,8 @@ static const uint32_t
 };
 
 #define _reg_PHY_RDDQS_X_FALL_SLAVE_DELAY_NUM 9
-static const uint32_t
-    _reg_PHY_RDDQS_X_FALL_SLAVE_DELAY[_reg_PHY_RDDQS_X_FALL_SLAVE_DELAY_NUM] = {
+static const uint32_t _reg_PHY_RDDQS_X_FALL_SLAVE_DELAY
+	[_reg_PHY_RDDQS_X_FALL_SLAVE_DELAY_NUM] = {
 	_reg_PHY_RDDQS_DQ0_FALL_SLAVE_DELAY,
 	_reg_PHY_RDDQS_DQ1_FALL_SLAVE_DELAY,
 	_reg_PHY_RDDQS_DQ2_FALL_SLAVE_DELAY,
@@ -184,8 +185,8 @@ static const uint32_t
 };
 
 #define _reg_PHY_RDDQS_X_RISE_SLAVE_DELAY_NUM 9
-static const uint32_t
-    _reg_PHY_RDDQS_X_RISE_SLAVE_DELAY[_reg_PHY_RDDQS_X_RISE_SLAVE_DELAY_NUM] = {
+static const uint32_t _reg_PHY_RDDQS_X_RISE_SLAVE_DELAY
+	[_reg_PHY_RDDQS_X_RISE_SLAVE_DELAY_NUM] = {
 	_reg_PHY_RDDQS_DQ0_RISE_SLAVE_DELAY,
 	_reg_PHY_RDDQS_DQ1_RISE_SLAVE_DELAY,
 	_reg_PHY_RDDQS_DQ2_RISE_SLAVE_DELAY,
@@ -210,8 +211,8 @@ static const uint32_t _reg_PHY_PAD_TERM_X[_reg_PHY_PAD_TERM_X_NUM] = {
 };
 
 #define _reg_PHY_CLK_CACS_SLAVE_DELAY_X_NUM 10
-static const uint32_t
-    _reg_PHY_CLK_CACS_SLAVE_DELAY_X[_reg_PHY_CLK_CACS_SLAVE_DELAY_X_NUM] = {
+static const uint32_t _reg_PHY_CLK_CACS_SLAVE_DELAY_X
+	[_reg_PHY_CLK_CACS_SLAVE_DELAY_X_NUM] = {
 	_reg_PHY_ADR0_CLK_WR_SLAVE_DELAY,
 	_reg_PHY_ADR1_CLK_WR_SLAVE_DELAY,
 	_reg_PHY_ADR2_CLK_WR_SLAVE_DELAY,
@@ -225,9 +226,7 @@ static const uint32_t
 	_reg_PHY_GRP_SLAVE_DELAY_3
 };
 
-/*******************************************************************************
- *	Prototypes
- ******************************************************************************/
+/* Prototypes */
 static inline uint32_t vch_nxt(uint32_t pos);
 static void cpg_write_32(uint32_t a, uint32_t v);
 static void pll3_control(uint32_t high);
@@ -248,21 +247,21 @@ static void ddr_setval_ach_s(uint32_t slice, uint32_t regdef, uint32_t val);
 static void ddr_setval_ach(uint32_t regdef, uint32_t val);
 static void ddr_setval_ach_as(uint32_t regdef, uint32_t val);
 static uint32_t ddr_getval(uint32_t ch, uint32_t regdef);
-static uint32_t ddr_getval_ach(uint32_t regdef, uint32_t * p);
-static uint32_t ddr_getval_ach_as(uint32_t regdef, uint32_t * p);
-static void _tblcopy(uint32_t * to, const uint32_t * from, uint32_t size);
-static void ddrtbl_setval(uint32_t * tbl, uint32_t _regdef, uint32_t val);
-static uint32_t ddrtbl_getval(uint32_t * tbl, uint32_t _regdef);
+static uint32_t ddr_getval_ach(uint32_t regdef, uint32_t *p);
+static uint32_t ddr_getval_ach_as(uint32_t regdef, uint32_t *p);
+static void _tblcopy(uint32_t *to, const uint32_t *from, uint32_t size);
+static void ddrtbl_setval(uint32_t *tbl, uint32_t _regdef, uint32_t val);
+static uint32_t ddrtbl_getval(uint32_t *tbl, uint32_t _regdef);
 static uint32_t ddrphy_regif_chk(void);
-static inline void ddrphy_regif_idle();
-static uint16_t _f_scale(uint32_t ddr_mbps, uint32_t ddr_mbpsdiv, uint32_t ps,
+static inline void ddrphy_regif_idle(void);
+static uint16_t _f_scale(uint32_t _ddr_mbps, uint32_t _ddr_mbpsdiv, uint32_t ps,
 			 uint16_t cyc);
-static void _f_scale_js2(uint32_t ddr_mbps, uint32_t ddr_mbpsdiv,
-			 uint16_t * js2);
+static void _f_scale_js2(uint32_t _ddr_mbps, uint32_t _ddr_mbpsdiv,
+			 uint16_t *_js2);
 static int16_t _f_scale_adj(int16_t ps);
 static void ddrtbl_load(void);
 static void ddr_config_sub(void);
-static void get_ca_swizzle(uint32_t ch, uint32_t ddr_csn, uint32_t * p_swz);
+static void get_ca_swizzle(uint32_t ch, uint32_t ddr_csn, uint32_t *p_swz);
 static void ddr_config_sub_h3v1x(void);
 static void ddr_config(void);
 static void dbsc_regset(void);
@@ -291,20 +290,19 @@ static uint32_t rx_offset_cal_hw(void);
 static void adjust_rddqs_latency(void);
 static void adjust_wpath_latency(void);
 
-struct DdrtData {
-	int32_t init_temp;	/*  Initial Temperature (do) */
-	uint32_t init_cal[4];	/*  Initial io-code (4 is for H3) */
-	uint32_t tcomp_cal[4];	/*  Temperature compensated io-code (4 is for H3) */
+struct ddrt_data {
+	int32_t init_temp;	/* Initial Temperature (do) */
+	uint32_t init_cal[4];	/* Initial io-code (4 is for H3) */
+	uint32_t tcomp_cal[4];	/* Temp. compensated io-code (4 is for H3) */
 };
-struct DdrtData tcal;
+
+static struct ddrt_data tcal;
 
 static void pvtcode_update(void);
 static void pvtcode_update2(void);
 static void ddr_padcal_tcompensate_getinit(uint32_t override);
 
-/*******************************************************************************
- *	load board configuration
- ******************************************************************************/
+/* load board configuration */
 #include "boot_init_dram_config.c"
 
 #ifndef DDR_FAST_INIT
@@ -325,9 +323,7 @@ static void wdqdm_clr1(uint32_t ch, uint32_t ddr_csn);
 static uint32_t wdqdm_ana1(uint32_t ch, uint32_t ddr_csn);
 #endif/* DDR_FAST_INIT */
 
-/*******************************************************************************
- *	macro for channel selection loop
- ******************************************************************************/
+/* macro for channel selection loop */
 static inline uint32_t vch_nxt(uint32_t pos)
 {
 	uint32_t posn;
@@ -340,19 +336,15 @@ static inline uint32_t vch_nxt(uint32_t pos)
 }
 
 #define foreach_vch(ch) \
-for(ch=vch_nxt(0);ch<DRAM_CH_CNT;ch=vch_nxt(ch+1))
+for (ch = vch_nxt(0); ch < DRAM_CH_CNT; ch = vch_nxt(ch + 1))
 
 #define foreach_ech(ch) \
-for(ch=0;ch<DRAM_CH_CNT;ch++)
+for (ch = 0; ch < DRAM_CH_CNT; ch++)
 
-/*******************************************************************************
- *	Printing functions
- ******************************************************************************/
+/* Printing functions */
 #define MSG_LF(...)
 
-/*******************************************************************************
- *	clock settings, reset control
- ******************************************************************************/
+/* clock settings, reset control */
 static void cpg_write_32(uint32_t a, uint32_t v)
 {
 	mmio_write_32(CPG_CPGWPR, ~v);
@@ -361,155 +353,151 @@ static void cpg_write_32(uint32_t a, uint32_t v)
 
 static void pll3_control(uint32_t high)
 {
-	uint32_t dataL, dataDIV, dataMUL, tmpDIV;
+	uint32_t data_l, data_div, data_mul, tmp_div;
 
 	if (high) {
-		tmpDIV = 3999 * brd_clkdiv * (brd_clkdiva + 1) /
+		tmp_div = 3999 * brd_clkdiv * (brd_clkdiva + 1) /
 			(brd_clk * ddr_mul) / 2;
-		dataMUL = (((ddr_mul * tmpDIV) - 1) << 24) |
-			(brd_clkdiva << 7);
-		Pll3Mode = 1;
+		data_mul = ((ddr_mul * tmp_div) - 1) << 24;
+		pll3_mode = 1;
 		loop_max = 2;
 	} else {
-		tmpDIV = 3999 * brd_clkdiv * (brd_clkdiva + 1) /
+		tmp_div = 3999 * brd_clkdiv * (brd_clkdiva + 1) /
 			(brd_clk * ddr0800_mul) / 2;
-		dataMUL = (((ddr0800_mul * tmpDIV) - 1) << 24) |
-			(brd_clkdiva << 7);
-		Pll3Mode = 0;
+		data_mul = ((ddr0800_mul * tmp_div) - 1) << 24;
+		pll3_mode = 0;
 		loop_max = 8;
 	}
 
-	switch (tmpDIV) {
+	switch (tmp_div) {
 	case 1:
-		dataDIV = 0;
+		data_div = 0;
 		break;
 	case 2:
 	case 3:
 	case 4:
-		dataDIV = tmpDIV;
+		data_div = tmp_div;
 		break;
 	default:
-		dataDIV = 6;
-		dataMUL = (dataMUL * tmpDIV) / 3;
+		data_div = 6;
+		data_mul = (data_mul * tmp_div) / 3;
 		break;
 	}
-	dataMUL = dataMUL | (brd_clkdiva << 7);
+	data_mul = data_mul | (brd_clkdiva << 7);
 
 	/* PLL3 disable */
-	dataL = mmio_read_32(CPG_PLLECR) & ~CPG_PLLECR_PLL3E_BIT;
-	cpg_write_32(CPG_PLLECR, dataL);
+	data_l = mmio_read_32(CPG_PLLECR) & ~CPG_PLLECR_PLL3E_BIT;
+	cpg_write_32(CPG_PLLECR, data_l);
 	dsb_sev();
 
-	if ((Prr_Product == PRR_PRODUCT_M3) ||
-	    ((Prr_Product == PRR_PRODUCT_H3) && (Prr_Cut <= PRR_PRODUCT_20))) {
+	if ((prr_product == PRR_PRODUCT_M3) ||
+	    ((prr_product == PRR_PRODUCT_H3) && (prr_cut <= PRR_PRODUCT_20))) {
 		/* PLL3 DIV resetting(Lowest value:3) */
-		dataL = 0x00030003 | (0xFF80FF80 & mmio_read_32(CPG_FRQCRD));
-		cpg_write_32(CPG_FRQCRD, dataL);
+		data_l = 0x00030003 | (0xFF80FF80 & mmio_read_32(CPG_FRQCRD));
+		cpg_write_32(CPG_FRQCRD, data_l);
 		dsb_sev();
 
 		/* zb3 clk stop */
-		dataL = CPG_ZB3CKCR_ZB3ST_BIT | mmio_read_32(CPG_ZB3CKCR);
-		cpg_write_32(CPG_ZB3CKCR, dataL);
+		data_l = CPG_ZB3CKCR_ZB3ST_BIT | mmio_read_32(CPG_ZB3CKCR);
+		cpg_write_32(CPG_ZB3CKCR, data_l);
 		dsb_sev();
 
 		/* PLL3 enable */
-		dataL = CPG_PLLECR_PLL3E_BIT | mmio_read_32(CPG_PLLECR);
-		cpg_write_32(CPG_PLLECR, dataL);
+		data_l = CPG_PLLECR_PLL3E_BIT | mmio_read_32(CPG_PLLECR);
+		cpg_write_32(CPG_PLLECR, data_l);
 		dsb_sev();
 
 		do {
-			dataL = mmio_read_32(CPG_PLLECR);
-		} while ((dataL & CPG_PLLECR_PLL3ST_BIT) == 0);
+			data_l = mmio_read_32(CPG_PLLECR);
+		} while ((data_l & CPG_PLLECR_PLL3ST_BIT) == 0);
 		dsb_sev();
 
 		/* PLL3 DIV resetting (Highest value:0) */
-		dataL = (0xFF80FF80 & mmio_read_32(CPG_FRQCRD));
-		cpg_write_32(CPG_FRQCRD, dataL);
+		data_l = (0xFF80FF80 & mmio_read_32(CPG_FRQCRD));
+		cpg_write_32(CPG_FRQCRD, data_l);
 		dsb_sev();
 
 		/* DIV SET KICK */
-		dataL = CPG_FRQCRB_KICK_BIT | mmio_read_32(CPG_FRQCRB);
-		cpg_write_32(CPG_FRQCRB, dataL);
+		data_l = CPG_FRQCRB_KICK_BIT | mmio_read_32(CPG_FRQCRB);
+		cpg_write_32(CPG_FRQCRB, data_l);
 		dsb_sev();
 
 		/* PLL3 multiplie set */
-		cpg_write_32(CPG_PLL3CR, dataMUL);
+		cpg_write_32(CPG_PLL3CR, data_mul);
 		dsb_sev();
 
 		do {
-			dataL = mmio_read_32(CPG_PLLECR);
-		} while ((dataL & CPG_PLLECR_PLL3ST_BIT) == 0);
+			data_l = mmio_read_32(CPG_PLLECR);
+		} while ((data_l & CPG_PLLECR_PLL3ST_BIT) == 0);
 		dsb_sev();
 
 		/* PLL3 DIV resetting(Target value) */
-		dataL = (dataDIV << 16) | dataDIV | (0xFF80FF80 & mmio_read_32(CPG_FRQCRD));
-		cpg_write_32(CPG_FRQCRD, dataL);
+		data_l = (data_div << 16) | data_div |
+			 (mmio_read_32(CPG_FRQCRD) & 0xFF80FF80);
+		cpg_write_32(CPG_FRQCRD, data_l);
 		dsb_sev();
 
 		/* DIV SET KICK */
-		dataL = CPG_FRQCRB_KICK_BIT | mmio_read_32(CPG_FRQCRB);
-		cpg_write_32(CPG_FRQCRB, dataL);
+		data_l = CPG_FRQCRB_KICK_BIT | mmio_read_32(CPG_FRQCRB);
+		cpg_write_32(CPG_FRQCRB, data_l);
 		dsb_sev();
 
 		do {
-			dataL = mmio_read_32(CPG_PLLECR);
-		} while ((dataL & CPG_PLLECR_PLL3ST_BIT) == 0);
+			data_l = mmio_read_32(CPG_PLLECR);
+		} while ((data_l & CPG_PLLECR_PLL3ST_BIT) == 0);
 		dsb_sev();
 
 		/* zb3 clk start */
-		dataL = (~CPG_ZB3CKCR_ZB3ST_BIT) & mmio_read_32(CPG_ZB3CKCR);
-		cpg_write_32(CPG_ZB3CKCR, dataL);
+		data_l = (~CPG_ZB3CKCR_ZB3ST_BIT) & mmio_read_32(CPG_ZB3CKCR);
+		cpg_write_32(CPG_ZB3CKCR, data_l);
 		dsb_sev();
 
 	} else { /*  H3Ver.3.0/M3N/V3H */
 
 		/* PLL3 multiplie set */
-		cpg_write_32(CPG_PLL3CR, dataMUL);
+		cpg_write_32(CPG_PLL3CR, data_mul);
 		dsb_sev();
 
 		/* PLL3 DIV set(Target value) */
-		dataL = (dataDIV << 16) | dataDIV | (0xFF80FF80 & mmio_read_32(CPG_FRQCRD));
-		cpg_write_32(CPG_FRQCRD, dataL);
+		data_l = (data_div << 16) | data_div |
+			 (mmio_read_32(CPG_FRQCRD) & 0xFF80FF80);
+		cpg_write_32(CPG_FRQCRD, data_l);
 
 		/* DIV SET KICK */
-		dataL = CPG_FRQCRB_KICK_BIT | mmio_read_32(CPG_FRQCRB);
-		cpg_write_32(CPG_FRQCRB, dataL);
+		data_l = CPG_FRQCRB_KICK_BIT | mmio_read_32(CPG_FRQCRB);
+		cpg_write_32(CPG_FRQCRB, data_l);
 		dsb_sev();
 
 		/* PLL3 enable */
-		dataL = CPG_PLLECR_PLL3E_BIT | mmio_read_32(CPG_PLLECR);
-		cpg_write_32(CPG_PLLECR, dataL);
+		data_l = CPG_PLLECR_PLL3E_BIT | mmio_read_32(CPG_PLLECR);
+		cpg_write_32(CPG_PLLECR, data_l);
 		dsb_sev();
 
 		do {
-			dataL = mmio_read_32(CPG_PLLECR);
-		} while ((dataL & CPG_PLLECR_PLL3ST_BIT) == 0);
+			data_l = mmio_read_32(CPG_PLLECR);
+		} while ((data_l & CPG_PLLECR_PLL3ST_BIT) == 0);
 		dsb_sev();
 	}
 }
 
-/*******************************************************************************
- *	barrier
- ******************************************************************************/
+/* barrier */
 static inline void dsb_sev(void)
 {
 	__asm__ __volatile__("dsb sy");
 }
 
-/*******************************************************************************
- *	DDR memory register access
- ******************************************************************************/
+/* DDR memory register access */
 static void wait_dbcmd(void)
 {
-	uint32_t dataL;
+	uint32_t data_l;
 	/* dummy read */
-	dataL = mmio_read_32(DBSC_DBCMD);
+	data_l = mmio_read_32(DBSC_DBCMD);
 	dsb_sev();
 	while (1) {
 		/* wait DBCMD 1=busy, 0=ready */
-		dataL = mmio_read_32(DBSC_DBWAIT);
+		data_l = mmio_read_32(DBSC_DBWAIT);
 		dsb_sev();
-		if ((dataL & 0x00000001) == 0x00)
+		if ((data_l & 0x00000001) == 0x00)
 			break;
 	}
 }
@@ -522,17 +510,15 @@ static void send_dbcmd(uint32_t cmd)
 	dsb_sev();
 }
 
-/*******************************************************************************
- *	DDRPHY register access (raw)
- ******************************************************************************/
+/* DDRPHY register access (raw) */
 static uint32_t reg_ddrphy_read(uint32_t phyno, uint32_t regadd)
 {
 	uint32_t val;
 	uint32_t loop;
 
 	val = 0;
-	if ((PRR_PRODUCT_M3N != Prr_Product)
-	    && (PRR_PRODUCT_V3H != Prr_Product)) {
+	if ((prr_product != PRR_PRODUCT_M3N) &&
+	    (prr_product != PRR_PRODUCT_V3H)) {
 		mmio_write_32(DBSC_DBPDRGA(phyno), regadd);
 		dsb_sev();
 
@@ -578,8 +564,8 @@ static void reg_ddrphy_write(uint32_t phyno, uint32_t regadd, uint32_t regdata)
 	uint32_t val;
 	uint32_t loop;
 
-	if ((PRR_PRODUCT_M3N != Prr_Product)
-	    && (PRR_PRODUCT_V3H != Prr_Product)) {
+	if ((prr_product != PRR_PRODUCT_M3N) &&
+	    (prr_product != PRR_PRODUCT_V3H)) {
 		mmio_write_32(DBSC_DBPDRGA(phyno), regadd);
 		dsb_sev();
 		for (loop = 0; loop < loop_max; loop++) {
@@ -627,8 +613,8 @@ static void reg_ddrphy_write_a(uint32_t regadd, uint32_t regdata)
 	uint32_t val;
 	uint32_t loop;
 
-	if ((PRR_PRODUCT_M3N != Prr_Product)
-	    && (PRR_PRODUCT_V3H != Prr_Product)) {
+	if ((prr_product != PRR_PRODUCT_M3N) &&
+	    (prr_product != PRR_PRODUCT_V3H)) {
 		foreach_vch(ch) {
 			mmio_write_32(DBSC_DBPDRGA(ch), regadd);
 			dsb_sev();
@@ -652,7 +638,7 @@ static void reg_ddrphy_write_a(uint32_t regadd, uint32_t regdata)
 	}
 }
 
-static inline void ddrphy_regif_idle()
+static inline void ddrphy_regif_idle(void)
 {
 	uint32_t val;
 
@@ -661,22 +647,20 @@ static inline void ddrphy_regif_idle()
 	(void)val;
 }
 
-/*******************************************************************************
- *	DDRPHY register access (field modify)
- ******************************************************************************/
+/* DDRPHY register access (field modify) */
 static inline uint32_t ddr_regdef(uint32_t _regdef)
 {
-	return pDDR_REGDEF_TBL[_regdef];
+	return p_ddr_regdef_tbl[_regdef];
 }
 
 static inline uint32_t ddr_regdef_adr(uint32_t _regdef)
 {
-	return DDR_REGDEF_ADR(pDDR_REGDEF_TBL[_regdef]);
+	return DDR_REGDEF_ADR(p_ddr_regdef_tbl[_regdef]);
 }
 
 static inline uint32_t ddr_regdef_lsb(uint32_t _regdef)
 {
-	return DDR_REGDEF_LSB(pDDR_REGDEF_TBL[_regdef]);
+	return DDR_REGDEF_LSB(p_ddr_regdef_tbl[_regdef]);
 }
 
 static void ddr_setval_s(uint32_t ch, uint32_t slice, uint32_t _regdef,
@@ -758,7 +742,7 @@ static uint32_t ddr_getval(uint32_t ch, uint32_t regdef)
 	return ddr_getval_s(ch, 0, regdef);
 }
 
-static uint32_t ddr_getval_ach(uint32_t regdef, uint32_t * p)
+static uint32_t ddr_getval_ach(uint32_t regdef, uint32_t *p)
 {
 	uint32_t ch;
 
@@ -767,22 +751,20 @@ static uint32_t ddr_getval_ach(uint32_t regdef, uint32_t * p)
 	return p[0];
 }
 
-static uint32_t ddr_getval_ach_as(uint32_t regdef, uint32_t * p)
+static uint32_t ddr_getval_ach_as(uint32_t regdef, uint32_t *p)
 {
 	uint32_t ch, slice;
 	uint32_t *pp;
 
 	pp = p;
 	foreach_vch(ch)
-	    for (slice = 0; slice < SLICE_CNT; slice++)
-		*pp++ = ddr_getval_s(ch, slice, regdef);
+		for (slice = 0; slice < SLICE_CNT; slice++)
+			*pp++ = ddr_getval_s(ch, slice, regdef);
 	return p[0];
 }
 
-/*******************************************************************************
- *	handling functions for setteing ddrphy value table
- ******************************************************************************/
-static void _tblcopy(uint32_t * to, const uint32_t * from, uint32_t size)
+/* handling functions for setteing ddrphy value table */
+static void _tblcopy(uint32_t *to, const uint32_t *from, uint32_t size)
 {
 	uint32_t i;
 
@@ -791,7 +773,7 @@ static void _tblcopy(uint32_t * to, const uint32_t * from, uint32_t size)
 	}
 }
 
-static void ddrtbl_setval(uint32_t * tbl, uint32_t _regdef, uint32_t val)
+static void ddrtbl_setval(uint32_t *tbl, uint32_t _regdef, uint32_t val)
 {
 	uint32_t adr;
 	uint32_t lsb;
@@ -821,7 +803,7 @@ static void ddrtbl_setval(uint32_t * tbl, uint32_t _regdef, uint32_t val)
 	tbl[adr & adrmsk] = tmp;
 }
 
-static uint32_t ddrtbl_getval(uint32_t * tbl, uint32_t _regdef)
+static uint32_t ddrtbl_getval(uint32_t *tbl, uint32_t _regdef)
 {
 	uint32_t adr;
 	uint32_t lsb;
@@ -852,9 +834,7 @@ static uint32_t ddrtbl_getval(uint32_t * tbl, uint32_t _regdef)
 	return tmp;
 }
 
-/*******************************************************************************
- *	DDRPHY register access handling
- ******************************************************************************/
+/* DDRPHY register access handling */
 static uint32_t ddrphy_regif_chk(void)
 {
 	uint32_t tmp_ach[DRAM_CH_CNT];
@@ -862,49 +842,56 @@ static uint32_t ddrphy_regif_chk(void)
 	uint32_t err;
 	uint32_t PI_VERSION_CODE;
 
-	if (((Prr_Product == PRR_PRODUCT_H3) && (Prr_Cut <= PRR_PRODUCT_11))
-	    || (Prr_Product == PRR_PRODUCT_M3)) {
-		PI_VERSION_CODE = 0x2041;	/* H3 Ver.1.x/M3-W */
+	if (((prr_product == PRR_PRODUCT_H3) && (prr_cut <= PRR_PRODUCT_11)) ||
+	    (prr_product == PRR_PRODUCT_M3)) {
+		PI_VERSION_CODE = 0x2041; /* H3 Ver.1.x/M3-W */
 	} else {
-		PI_VERSION_CODE = 0x2040;	/* H3 Ver.2.0 or later/M3-N/V3H */
+		PI_VERSION_CODE = 0x2040; /* H3 Ver.2.0 or later/M3-N/V3H */
 	}
 
-	ddr_getval_ach(_reg_PI_VERSION, (uint32_t *) tmp_ach);
+	ddr_getval_ach(_reg_PI_VERSION, (uint32_t *)tmp_ach);
 	err = 0;
 	foreach_vch(ch) {
-		if (PI_VERSION_CODE != tmp_ach[ch])
+		if (tmp_ach[ch] != PI_VERSION_CODE)
 			err = 1;
 	}
 	return err;
 }
 
-/*******************************************************************************
- *	functions and parameters for timing setting
- ******************************************************************************/
+/* functions and parameters for timing setting */
 struct _jedec_spec1 {
 	uint16_t fx3;
-	uint8_t RLwoDBI;
-	uint8_t RLwDBI;
+	uint8_t rlwodbi;
+	uint8_t rlwdbi;
 	uint8_t WL;
-	uint8_t nWR;
-	uint8_t nRTP;
+	uint8_t nwr;
+	uint8_t nrtp;
 	uint8_t MR1;
 	uint8_t MR2;
 };
+
 #define JS1_USABLEC_SPEC_LO 2
 #define JS1_USABLEC_SPEC_HI 5
 #define JS1_FREQ_TBL_NUM 8
-#define JS1_MR1(f) (0x04 | ((f)<<4))
-#define JS1_MR2(f) (0x00 | ((f)<<3) | (f))
+#define JS1_MR1(f) (0x04 | ((f) << 4))
+#define JS1_MR2(f) (0x00 | ((f) << 3) | (f))
 const struct _jedec_spec1 js1[JS1_FREQ_TBL_NUM] = {
-	{  800,  6,  6,  4,  6,  8, JS1_MR1(0), JS1_MR2(0)|0x40 }, /*  533.333Mbps */
-	{ 1600, 10, 12,  8, 10,  8, JS1_MR1(1), JS1_MR2(1)|0x40 }, /* 1066.666Mbps */
-	{ 2400, 14, 16, 12, 16,  8, JS1_MR1(2), JS1_MR2(2)|0x40 }, /* 1600.000Mbps */
-	{ 3200, 20, 22, 10, 20,  8, JS1_MR1(3), JS1_MR2(3) },      /* 2133.333Mbps */
-	{ 4000, 24, 28, 12, 24, 10, JS1_MR1(4), JS1_MR2(4) },      /* 2666.666Mbps */
-	{ 4800, 28, 32, 14, 30, 12, JS1_MR1(5), JS1_MR2(5) },      /* 3200.000Mbps */
-	{ 5600, 32, 36, 16, 34, 14, JS1_MR1(6), JS1_MR2(6) },      /* 3733.333Mbps */
-	{ 6400, 36, 40, 18, 40, 16, JS1_MR1(7), JS1_MR2(7) }       /* 4266.666Mbps */
+	/* 533.333Mbps */
+	{  800,  6,  6,  4,  6,  8, JS1_MR1(0), JS1_MR2(0) | 0x40 },
+	/* 1066.666Mbps */
+	{ 1600, 10, 12,  8, 10,  8, JS1_MR1(1), JS1_MR2(1) | 0x40 },
+	/* 1600.000Mbps */
+	{ 2400, 14, 16, 12, 16,  8, JS1_MR1(2), JS1_MR2(2) | 0x40 },
+	/* 2133.333Mbps */
+	{ 3200, 20, 22, 10, 20,  8, JS1_MR1(3), JS1_MR2(3) },
+	/* 2666.666Mbps */
+	{ 4000, 24, 28, 12, 24, 10, JS1_MR1(4), JS1_MR2(4) },
+	/* 3200.000Mbps */
+	{ 4800, 28, 32, 14, 30, 12, JS1_MR1(5), JS1_MR2(5) },
+	/* 3733.333Mbps */
+	{ 5600, 32, 36, 16, 34, 14, JS1_MR1(6), JS1_MR2(6) },
+	/* 4266.666Mbps */
+	{ 6400, 36, 40, 18, 40, 16, JS1_MR1(7), JS1_MR2(7) }
 };
 
 struct _jedec_spec2 {
@@ -912,34 +899,34 @@ struct _jedec_spec2 {
 	uint16_t cyc;
 };
 
-#define JS2_tSR 0
-#define JS2_tXP 1
-#define JS2_tRTP 2
-#define JS2_tRCD 3
-#define JS2_tRPpb 4
-#define JS2_tRPab 5
-#define JS2_tRAS 6
-#define JS2_tWR 7
-#define JS2_tWTR 8
-#define JS2_tRRD 9
-#define JS2_tPPD 10
-#define JS2_tFAW 11
-#define JS2_tDQSCK 12
-#define JS2_tCKEHCMD 13
-#define JS2_tCKELCMD 14
-#define JS2_tCKELPD 15
-#define JS2_tMRR 16
-#define JS2_tMRW 17
-#define JS2_tMRD 18
-#define JS2_tZQCALns 19
-#define JS2_tZQLAT 20
-#define JS2_tIEdly 21
+#define js2_tsr 0
+#define js2_txp 1
+#define js2_trtp 2
+#define js2_trcd 3
+#define js2_trppb 4
+#define js2_trpab 5
+#define js2_tras 6
+#define js2_twr 7
+#define js2_twtr 8
+#define js2_trrd 9
+#define js2_tppd 10
+#define js2_tfaw 11
+#define js2_tdqsck 12
+#define js2_tckehcmd 13
+#define js2_tckelcmd 14
+#define js2_tckelpd 15
+#define js2_tmrr 16
+#define js2_tmrw 17
+#define js2_tmrd 18
+#define js2_tzqcalns 19
+#define js2_tzqlat 20
+#define js2_tiedly 21
 #define JS2_TBLCNT 22
 
-#define JS2_tRCpb (JS2_TBLCNT)
-#define JS2_tRCab (JS2_TBLCNT+1)
-#define JS2_tRFCab (JS2_TBLCNT+2)
-#define JS2_CNT (JS2_TBLCNT+3)
+#define js2_trcpb (JS2_TBLCNT)
+#define js2_trcab (JS2_TBLCNT + 1)
+#define js2_trfcab (JS2_TBLCNT + 2)
+#define JS2_CNT (JS2_TBLCNT + 3)
 
 #ifndef JS2_DERATE
 #define JS2_DERATE 0
@@ -991,10 +978,10 @@ const struct _jedec_spec2 jedec_spec2[2][JS2_TBLCNT] = {
 /*tZQCALns*/ {1000 * 10, 0},
 /*tZQLAT*/ {30000, 10},
 /*tIEdly*/ {12500, 0}
-	     }
+	}
 };
 
-const uint16_t jedec_spec2_tRFC_ab[7] = {
+const uint16_t jedec_spec2_trfc_ab[7] = {
 /*	4Gb, 6Gb, 8Gb,12Gb, 16Gb, 24Gb(non), 32Gb(non)	*/
 	 130, 180, 180, 280, 280, 560, 560
 };
@@ -1004,35 +991,35 @@ static uint16_t js2[JS2_CNT];
 static uint8_t RL;
 static uint8_t WL;
 
-static uint16_t _f_scale(uint32_t ddr_mbps, uint32_t ddr_mbpsdiv, uint32_t ps,
+static uint16_t _f_scale(uint32_t _ddr_mbps, uint32_t _ddr_mbpsdiv, uint32_t ps,
 			 uint16_t cyc)
 {
 	uint32_t tmp;
 	uint32_t div;
 
-	tmp = (((uint32_t) (ps) + 9) / 10) * ddr_mbps;
-	div = tmp / (200000 * ddr_mbpsdiv);
-	if (tmp != (div * 200000 * ddr_mbpsdiv))
+	tmp = (((uint32_t)(ps) + 9) / 10) * _ddr_mbps;
+	div = tmp / (200000 * _ddr_mbpsdiv);
+	if (tmp != (div * 200000 * _ddr_mbpsdiv))
 		div = div + 1;
 
 	if (div > cyc)
-		return (uint16_t) div;
+		return (uint16_t)div;
 	return cyc;
 }
 
-static void _f_scale_js2(uint32_t ddr_mbps, uint32_t ddr_mbpsdiv,
-			 uint16_t * js2)
+static void _f_scale_js2(uint32_t _ddr_mbps, uint32_t _ddr_mbpsdiv,
+			 uint16_t *_js2)
 {
 	int i;
 
 	for (i = 0; i < JS2_TBLCNT; i++) {
-		js2[i] = _f_scale(ddr_mbps, ddr_mbpsdiv,
+		_js2[i] = _f_scale(_ddr_mbps, _ddr_mbpsdiv,
 				  1UL * jedec_spec2[JS2_DERATE][i].ps,
 				  jedec_spec2[JS2_DERATE][i].cyc);
 	}
 
-	js2[JS2_tRCpb] = js2[JS2_tRAS] + js2[JS2_tRPpb];
-	js2[JS2_tRCab] = js2[JS2_tRAS] + js2[JS2_tRPab];
+	_js2[js2_trcpb] = _js2[js2_tras] + _js2[js2_trppb];
+	_js2[js2_trcab] = _js2[js2_tras] + _js2[js2_trpab];
 }
 
 /* scaler for DELAY value */
@@ -1040,19 +1027,19 @@ static int16_t _f_scale_adj(int16_t ps)
 {
 	int32_t tmp;
 	/*
-	   tmp = (int32_t)512 * ps * ddr_mbps /2 / ddr_mbpsdiv / 1000 / 1000;
-	   = ps * ddr_mbps /2 / ddr_mbpsdiv *512 / 8 / 8 / 125 / 125
-	   = ps * ddr_mbps / ddr_mbpsdiv *4 / 125 / 125
+	 * tmp = (int32_t)512 * ps * ddr_mbps /2 / ddr_mbpsdiv / 1000 / 1000;
+	 *     = ps * ddr_mbps /2 / ddr_mbpsdiv *512 / 8 / 8 / 125 / 125
+	 *     = ps * ddr_mbps / ddr_mbpsdiv *4 / 125 / 125
 	 */
 	tmp =
-	    (int32_t) 4 *(int32_t) ps *(int32_t) ddr_mbps /
-	    (int32_t) ddr_mbpsdiv;
-	tmp = (int32_t) tmp / (int32_t) 15625;
+	    (int32_t)4 * (int32_t)ps * (int32_t)ddr_mbps /
+	    (int32_t)ddr_mbpsdiv;
+	tmp = (int32_t)tmp / (int32_t)15625;
 
-	return (int16_t) tmp;
+	return (int16_t)tmp;
 }
 
-const uint32_t _reg_PI_MR1_DATA_Fx_CSx[2][CSAB_CNT] = {
+static const uint32_t reg_pi_mr1_data_fx_csx[2][CSAB_CNT] = {
 	{
 	 _reg_PI_MR1_DATA_F0_0,
 	 _reg_PI_MR1_DATA_F0_1,
@@ -1065,7 +1052,7 @@ const uint32_t _reg_PI_MR1_DATA_Fx_CSx[2][CSAB_CNT] = {
 	 _reg_PI_MR1_DATA_F1_3}
 };
 
-const uint32_t _reg_PI_MR2_DATA_Fx_CSx[2][CSAB_CNT] = {
+static const uint32_t reg_pi_mr2_data_fx_csx[2][CSAB_CNT] = {
 	{
 	 _reg_PI_MR2_DATA_F0_0,
 	 _reg_PI_MR2_DATA_F0_1,
@@ -1078,7 +1065,7 @@ const uint32_t _reg_PI_MR2_DATA_Fx_CSx[2][CSAB_CNT] = {
 	 _reg_PI_MR2_DATA_F1_3}
 };
 
-const uint32_t _reg_PI_MR3_DATA_Fx_CSx[2][CSAB_CNT] = {
+static const uint32_t reg_pi_mr3_data_fx_csx[2][CSAB_CNT] = {
 	{
 	 _reg_PI_MR3_DATA_F0_0,
 	 _reg_PI_MR3_DATA_F0_1,
@@ -1091,7 +1078,7 @@ const uint32_t _reg_PI_MR3_DATA_Fx_CSx[2][CSAB_CNT] = {
 	 _reg_PI_MR3_DATA_F1_3}
 };
 
-const uint32_t _reg_PI_MR11_DATA_Fx_CSx[2][CSAB_CNT] = {
+const uint32_t reg_pi_mr11_data_fx_csx[2][CSAB_CNT] = {
 	{
 	 _reg_PI_MR11_DATA_F0_0,
 	 _reg_PI_MR11_DATA_F0_1,
@@ -1104,7 +1091,7 @@ const uint32_t _reg_PI_MR11_DATA_Fx_CSx[2][CSAB_CNT] = {
 	 _reg_PI_MR11_DATA_F1_3}
 };
 
-const uint32_t _reg_PI_MR12_DATA_Fx_CSx[2][CSAB_CNT] = {
+const uint32_t reg_pi_mr12_data_fx_csx[2][CSAB_CNT] = {
 	{
 	 _reg_PI_MR12_DATA_F0_0,
 	 _reg_PI_MR12_DATA_F0_1,
@@ -1117,7 +1104,7 @@ const uint32_t _reg_PI_MR12_DATA_Fx_CSx[2][CSAB_CNT] = {
 	 _reg_PI_MR12_DATA_F1_3}
 };
 
-const uint32_t _reg_PI_MR14_DATA_Fx_CSx[2][CSAB_CNT] = {
+const uint32_t reg_pi_mr14_data_fx_csx[2][CSAB_CNT] = {
 	{
 	 _reg_PI_MR14_DATA_F0_0,
 	 _reg_PI_MR14_DATA_F0_1,
@@ -1130,14 +1117,14 @@ const uint32_t _reg_PI_MR14_DATA_Fx_CSx[2][CSAB_CNT] = {
 	 _reg_PI_MR14_DATA_F1_3}
 };
 
-/*******************************************************************************
+/*
  * regif pll w/a   ( REGIF H3 Ver.2.0 or later/M3-N/V3H WA )
- *******************************************************************************/
+ */
 static void regif_pll_wa(void)
 {
 	uint32_t ch;
 
-	if ((Prr_Product == PRR_PRODUCT_H3) && (Prr_Cut <= PRR_PRODUCT_11)) {
+	if ((prr_product == PRR_PRODUCT_H3) && (prr_cut <= PRR_PRODUCT_11)) {
 		// PLL setting for PHY : H3 Ver.1.x
 		reg_ddrphy_write_a(ddr_regdef_adr(_reg_PHY_PLL_WAIT),
 				   (0x0064U <<
@@ -1175,17 +1162,20 @@ static void regif_pll_wa(void)
 		reg_ddrphy_write_a(ddr_regdef_adr
 				   (_reg_PHY_LP4_BOOT_TOP_PLL_CTRL),
 				   ddrtbl_getval(_cnf_DDR_PHY_ADR_G_REGSET,
-						 _reg_PHY_LP4_BOOT_TOP_PLL_CTRL));
+						 _reg_PHY_LP4_BOOT_TOP_PLL_CTRL
+						 ));
 	}
 
 	reg_ddrphy_write_a(ddr_regdef_adr(_reg_PHY_LPDDR3_CS),
-				_cnf_DDR_PHY_ADR_G_REGSET[ddr_regdef_adr(_reg_PHY_LPDDR3_CS) - DDR_PHY_ADR_G_REGSET_OFS]);
+			   _cnf_DDR_PHY_ADR_G_REGSET
+			   [ddr_regdef_adr(_reg_PHY_LPDDR3_CS) -
+			   DDR_PHY_ADR_G_REGSET_OFS]);
 
 	/* protect register interface */
 	ddrphy_regif_idle();
 	pll3_control(0);
 
-	if ((Prr_Product == PRR_PRODUCT_H3) && (Prr_Cut <= PRR_PRODUCT_11)) {
+	if ((prr_product == PRR_PRODUCT_H3) && (prr_cut <= PRR_PRODUCT_11)) {
 		/*  non */
 	} else {
 		reg_ddrphy_write_a(ddr_regdef_adr(_reg_PHY_DLL_RST_EN),
@@ -1194,9 +1184,7 @@ static void regif_pll_wa(void)
 		ddrphy_regif_idle();
 	}
 
-	/***********************************************************************
-	init start
-	***********************************************************************/
+	/* init start */
 	/* dbdficnt0:
 	 * dfi_dram_clk_disable=1
 	 * dfi_frequency = 0
@@ -1218,52 +1206,47 @@ static void regif_pll_wa(void)
 	dsb_sev();
 
 	foreach_ech(ch)
-	    if (((Boardcnf->phyvalid) & (1U << ch)))
-		while ((mmio_read_32(DBSC_PLL_LOCK(ch)) & 0x1f) != 0x1f) ;
+	if ((board_cnf->phyvalid) & BIT(ch))
+		while ((mmio_read_32(DBSC_PLL_LOCK(ch)) & 0x1f) != 0x1f)
+			;
 	dsb_sev();
 }
 
-/*******************************************************************************
- *	load table data into DDR registers
- ******************************************************************************/
+/* load table data into DDR registers */
 static void ddrtbl_load(void)
 {
 	uint32_t i;
 	uint32_t slice;
 	uint32_t csab;
 	uint32_t adr;
-	uint32_t dataL;
+	uint32_t data_l;
 	uint32_t tmp[3];
 	uint16_t dataS;
 
-	/***********************************************************************
-	TIMING REGISTERS
-	***********************************************************************/
+	/* TIMING REGISTERS */
 	/* search jedec_spec1 index */
 	for (i = JS1_USABLEC_SPEC_LO; i < JS1_FREQ_TBL_NUM - 1; i++) {
 		if (js1[i].fx3 * 2U * ddr_mbpsdiv >= ddr_mbps * 3U)
 			break;
 	}
-	if (JS1_USABLEC_SPEC_HI < i)
+	if (i > JS1_USABLEC_SPEC_HI)
 		js1_ind = JS1_USABLEC_SPEC_HI;
 	else
 		js1_ind = i;
 
-	if (Boardcnf->dbi_en)
-		RL = js1[js1_ind].RLwDBI;
+	if (board_cnf->dbi_en)
+		RL = js1[js1_ind].rlwdbi;
 	else
-		RL = js1[js1_ind].RLwoDBI;
+		RL = js1[js1_ind].rlwodbi;
 
 	WL = js1[js1_ind].WL;
 
 	/* calculate jedec_spec2 */
 	_f_scale_js2(ddr_mbps, ddr_mbpsdiv, js2);
 
-	/***********************************************************************
-	PREPARE TBL
-	***********************************************************************/
-	if (Prr_Product == PRR_PRODUCT_H3) {
-		if (Prr_Cut <= PRR_PRODUCT_11) {
+	/* PREPARE TBL */
+	if (prr_product == PRR_PRODUCT_H3) {
+		if (prr_cut <= PRR_PRODUCT_11) {
 			/*  H3 Ver.1.x */
 			_tblcopy(_cnf_DDR_PHY_SLICE_REGSET,
 				 DDR_PHY_SLICE_REGSET_H3,
@@ -1339,7 +1322,7 @@ static void ddrtbl_load(void)
 
 			DDR_PHY_ADR_I_NUM = 0;
 		}
-	} else if (Prr_Product == PRR_PRODUCT_M3) {
+	} else if (prr_product == PRR_PRODUCT_M3) {
 		/*  M3-W */
 		_tblcopy(_cnf_DDR_PHY_SLICE_REGSET,
 			 DDR_PHY_SLICE_REGSET_M3, DDR_PHY_SLICE_REGSET_NUM_M3);
@@ -1402,32 +1385,26 @@ static void ddrtbl_load(void)
 		DDR_PHY_ADR_I_NUM = 2;
 	}
 
-	/***********************************************************************
-	PLL CODE CHANGE
-	***********************************************************************/
-	if ((Prr_Product == PRR_PRODUCT_H3) && (Prr_Cut == PRR_PRODUCT_11)) {
+	/* PLL CODE CHANGE */
+	if ((prr_product == PRR_PRODUCT_H3) && (prr_cut == PRR_PRODUCT_11)) {
 		ddrtbl_setval(_cnf_DDR_PHY_ADR_G_REGSET, _reg_PHY_PLL_CTRL,
 			      0x1142);
 		ddrtbl_setval(_cnf_DDR_PHY_ADR_G_REGSET,
 			      _reg_PHY_LP4_BOOT_PLL_CTRL, 0x1142);
 	}
 
-	/***********************************************************************
-	on fly gate adjust
-	***********************************************************************/
-	if ((Prr_Product == PRR_PRODUCT_M3) && (Prr_Cut == PRR_PRODUCT_10)) {
+	/* on fly gate adjust */
+	if ((prr_product == PRR_PRODUCT_M3) && (prr_cut == PRR_PRODUCT_10)) {
 		ddrtbl_setval(_cnf_DDR_PHY_SLICE_REGSET,
 			      _reg_ON_FLY_GATE_ADJUST_EN, 0x00);
 	}
 
-	/***********************************************************************
-	Adjust PI parameters
-	***********************************************************************/
+	/* Adjust PI parameters */
 #ifdef _def_LPDDR4_ODT
 	for (i = 0; i < 2; i++) {
 		for (csab = 0; csab < CSAB_CNT; csab++) {
 			ddrtbl_setval(_cnf_DDR_PI_REGSET,
-				      _reg_PI_MR11_DATA_Fx_CSx[i][csab],
+				      reg_pi_mr11_data_fx_csx[i][csab],
 				      _def_LPDDR4_ODT);
 		}
 	}
@@ -1437,43 +1414,43 @@ static void ddrtbl_load(void)
 	for (i = 0; i < 2; i++) {
 		for (csab = 0; csab < CSAB_CNT; csab++) {
 			ddrtbl_setval(_cnf_DDR_PI_REGSET,
-				      _reg_PI_MR12_DATA_Fx_CSx[i][csab],
+				      reg_pi_mr12_data_fx_csx[i][csab],
 				      _def_LPDDR4_VREFCA);
 		}
 	}
 #endif /* _def_LPDDR4_VREFCA */
-	if ((Prr_Product == PRR_PRODUCT_M3N)
-	    || (Prr_Product == PRR_PRODUCT_V3H)) {
-		js2[JS2_tIEdly] = _f_scale(ddr_mbps, ddr_mbpsdiv, 7000, 0) + 7U;
-		if (js2[JS2_tIEdly] > (RL))
-			js2[JS2_tIEdly] = RL;
-	} else if ((Prr_Product == PRR_PRODUCT_H3)
-		   && (Prr_Cut > PRR_PRODUCT_11)) {
-		js2[JS2_tIEdly] = _f_scale(ddr_mbps, ddr_mbpsdiv, 9000, 0) + 4U;
-	} else if ((Prr_Product == PRR_PRODUCT_H3)
-		   && (Prr_Cut <= PRR_PRODUCT_11)) {
-		js2[JS2_tIEdly] = _f_scale(ddr_mbps, ddr_mbpsdiv, 10000, 0);
-	}
-
-	if (((Prr_Product == PRR_PRODUCT_H3) && (Prr_Cut > PRR_PRODUCT_11))
-	    || (Prr_Product == PRR_PRODUCT_M3N)
-	    || (Prr_Product == PRR_PRODUCT_V3H)) {
-		if ((js2[JS2_tIEdly]) >= 0x1e)
+	if ((prr_product == PRR_PRODUCT_M3N) ||
+	    (prr_product == PRR_PRODUCT_V3H)) {
+		js2[js2_tiedly] = _f_scale(ddr_mbps, ddr_mbpsdiv, 7000, 0) + 7U;
+		if (js2[js2_tiedly] > (RL))
+			js2[js2_tiedly] = RL;
+	} else if ((prr_product == PRR_PRODUCT_H3) &&
+		   (prr_cut > PRR_PRODUCT_11)) {
+		js2[js2_tiedly] = _f_scale(ddr_mbps, ddr_mbpsdiv, 9000, 0) + 4U;
+	} else if ((prr_product == PRR_PRODUCT_H3) &&
+		   (prr_cut <= PRR_PRODUCT_11)) {
+		js2[js2_tiedly] = _f_scale(ddr_mbps, ddr_mbpsdiv, 10000, 0);
+	}
+
+	if (((prr_product == PRR_PRODUCT_H3) && (prr_cut > PRR_PRODUCT_11)) ||
+	    (prr_product == PRR_PRODUCT_M3N) ||
+	    (prr_product == PRR_PRODUCT_V3H)) {
+		if ((js2[js2_tiedly]) >= 0x1e)
 			dataS = 0x1e;
 		else
-			dataS = js2[JS2_tIEdly];
+			dataS = js2[js2_tiedly];
 	} else {
-		if ((js2[JS2_tIEdly]) >= 0x0e)
+		if ((js2[js2_tiedly]) >= 0x0e)
 			dataS = 0x0e;
 		else
-			dataS = js2[JS2_tIEdly];
+			dataS = js2[js2_tiedly];
 	}
 
 	ddrtbl_setval(_cnf_DDR_PHY_SLICE_REGSET, _reg_PHY_RDDATA_EN_DLY, dataS);
 	ddrtbl_setval(_cnf_DDR_PHY_SLICE_REGSET, _reg_PHY_RDDATA_EN_TSEL_DLY,
 		      (dataS - 2));
-	if ((Prr_Product == PRR_PRODUCT_M3N)
-	    || (Prr_Product == PRR_PRODUCT_V3H)) {
+	if ((prr_product == PRR_PRODUCT_M3N) ||
+	    (prr_product == PRR_PRODUCT_V3H)) {
 		ddrtbl_setval(_cnf_DDR_PHY_SLICE_REGSET,
 			      _reg_PHY_RDDATA_EN_OE_DLY, dataS);
 	}
@@ -1481,14 +1458,14 @@ static void ddrtbl_load(void)
 
 	if (ddrtbl_getval
 	    (_cnf_DDR_PHY_SLICE_REGSET, _reg_PHY_WRITE_PATH_LAT_ADD)) {
-		dataL = WL - 1;
+		data_l = WL - 1;
 	} else {
-		dataL = WL;
+		data_l = WL;
 	}
-	ddrtbl_setval(_cnf_DDR_PI_REGSET, _reg_PI_WRLAT_ADJ_F1, dataL - 2);
-	ddrtbl_setval(_cnf_DDR_PI_REGSET, _reg_PI_WRLAT_F1, dataL);
+	ddrtbl_setval(_cnf_DDR_PI_REGSET, _reg_PI_WRLAT_ADJ_F1, data_l - 2);
+	ddrtbl_setval(_cnf_DDR_PI_REGSET, _reg_PI_WRLAT_F1, data_l);
 
-	if (Boardcnf->dbi_en) {
+	if (board_cnf->dbi_en) {
 		ddrtbl_setval(_cnf_DDR_PHY_SLICE_REGSET, _reg_PHY_DBI_MODE,
 			      0x01);
 		ddrtbl_setval(_cnf_DDR_PHY_SLICE_REGSET,
@@ -1502,42 +1479,36 @@ static void ddrtbl_load(void)
 
 	tmp[0] = js1[js1_ind].MR1;
 	tmp[1] = js1[js1_ind].MR2;
-	dataL = ddrtbl_getval(_cnf_DDR_PI_REGSET, _reg_PI_MR3_DATA_F1_0);
-	if (Boardcnf->dbi_en)
-		tmp[2] = dataL | 0xc0;
+	data_l = ddrtbl_getval(_cnf_DDR_PI_REGSET, _reg_PI_MR3_DATA_F1_0);
+	if (board_cnf->dbi_en)
+		tmp[2] = data_l | 0xc0;
 	else
-		tmp[2] = dataL & (~0xc0);
+		tmp[2] = data_l & (~0xc0);
 
 	for (i = 0; i < 2; i++) {
 		for (csab = 0; csab < CSAB_CNT; csab++) {
 			ddrtbl_setval(_cnf_DDR_PI_REGSET,
-				      _reg_PI_MR1_DATA_Fx_CSx[i][csab], tmp[0]);
+				      reg_pi_mr1_data_fx_csx[i][csab], tmp[0]);
 			ddrtbl_setval(_cnf_DDR_PI_REGSET,
-				      _reg_PI_MR2_DATA_Fx_CSx[i][csab], tmp[1]);
+				      reg_pi_mr2_data_fx_csx[i][csab], tmp[1]);
 			ddrtbl_setval(_cnf_DDR_PI_REGSET,
-				      _reg_PI_MR3_DATA_Fx_CSx[i][csab], tmp[2]);
+				      reg_pi_mr3_data_fx_csx[i][csab], tmp[2]);
 		}
 	}
 
-	/***********************************************************************
-	 DDRPHY INT START
-	***********************************************************************/
-	if ((Prr_Product == PRR_PRODUCT_H3) && (Prr_Cut <= PRR_PRODUCT_11)) {
+	/* DDRPHY INT START */
+	if ((prr_product == PRR_PRODUCT_H3) && (prr_cut <= PRR_PRODUCT_11)) {
 		/*  non */
 	} else {
 		regif_pll_wa();
 	}
 
-	/***********************************************************************
-	FREQ_SEL_MULTICAST & PER_CS_TRAINING_MULTICAST SET (for safety)
-	***********************************************************************/
+	/* FREQ_SEL_MULTICAST & PER_CS_TRAINING_MULTICAST SET (for safety) */
 	reg_ddrphy_write_a(ddr_regdef_adr(_reg_PHY_FREQ_SEL_MULTICAST_EN),
-		(0x01U << ddr_regdef_lsb(_reg_PHY_FREQ_SEL_MULTICAST_EN)));
+			   BIT(ddr_regdef_lsb(_reg_PHY_FREQ_SEL_MULTICAST_EN)));
 	ddr_setval_ach_as(_reg_PHY_PER_CS_TRAINING_MULTICAST_EN, 0x01);
 
-	/***********************************************************************
-	SET DATA SLICE TABLE
-	***********************************************************************/
+	/* SET DATA SLICE TABLE */
 	for (slice = 0; slice < SLICE_CNT; slice++) {
 		adr =
 		    DDR_PHY_SLICE_REGSET_OFS +
@@ -1548,24 +1519,23 @@ static void ddrtbl_load(void)
 		}
 	}
 
-	/***********************************************************************
-	SET ADR SLICE TABLE
-	***********************************************************************/
+	/* SET ADR SLICE TABLE */
 	adr = DDR_PHY_ADR_V_REGSET_OFS;
 	for (i = 0; i < DDR_PHY_ADR_V_REGSET_NUM; i++) {
 		reg_ddrphy_write_a(adr + i, _cnf_DDR_PHY_ADR_V_REGSET[i]);
 	}
 
-	if (((Prr_Product == PRR_PRODUCT_M3)
-	    || (Prr_Product == PRR_PRODUCT_M3N)) &&
-	    ((0x00ffffff & (uint32_t)((Boardcnf->ch[0].ca_swap) >> 40))
+	if (((prr_product == PRR_PRODUCT_M3) ||
+	     (prr_product == PRR_PRODUCT_M3N)) &&
+	    ((0x00ffffff & (uint32_t)((board_cnf->ch[0].ca_swap) >> 40))
 	    != 0x00)) {
 		adr = DDR_PHY_ADR_I_REGSET_OFS + DDR_PHY_ADR_I_REGSET_SIZE;
 		for (i = 0; i < DDR_PHY_ADR_V_REGSET_NUM; i++) {
 			reg_ddrphy_write_a(adr + i,
 					   _cnf_DDR_PHY_ADR_V_REGSET[i]);
 		}
-		ddrtbl_setval(_cnf_DDR_PHY_ADR_G_REGSET, _reg_PHY_ADR_DISABLE, 0x02);
+		ddrtbl_setval(_cnf_DDR_PHY_ADR_G_REGSET,
+			      _reg_PHY_ADR_DISABLE, 0x02);
 		DDR_PHY_ADR_I_NUM -= 1;
 		ddr_phycaslice = 1;
 
@@ -1573,7 +1543,7 @@ static void ddrtbl_load(void)
 		for (i = 0; i < 2; i++) {
 			for (csab = 0; csab < CSAB_CNT; csab++) {
 				ddrtbl_setval(_cnf_DDR_PI_REGSET,
-					      _reg_PI_MR11_DATA_Fx_CSx[i][csab],
+					      reg_pi_mr11_data_fx_csx[i][csab],
 					      0x66);
 			}
 		}
@@ -1595,45 +1565,38 @@ static void ddrtbl_load(void)
 		}
 	}
 
-	/***********************************************************************
-	SET ADRCTRL SLICE TABLE
-	***********************************************************************/
+	/* SET ADRCTRL SLICE TABLE */
 	adr = DDR_PHY_ADR_G_REGSET_OFS;
 	for (i = 0; i < DDR_PHY_ADR_G_REGSET_NUM; i++) {
 		reg_ddrphy_write_a(adr + i, _cnf_DDR_PHY_ADR_G_REGSET[i]);
 	}
 
-	/***********************************************************************
-	SET PI REGISTERS
-	***********************************************************************/
+	/* SET PI REGISTERS */
 	adr = DDR_PI_REGSET_OFS;
 	for (i = 0; i < DDR_PI_REGSET_NUM; i++) {
 		reg_ddrphy_write_a(adr + i, _cnf_DDR_PI_REGSET[i]);
 	}
 }
 
-/*******************************************************************************
- *	CONFIGURE DDR REGISTERS
- ******************************************************************************/
+/* CONFIGURE DDR REGISTERS */
 static void ddr_config_sub(void)
 {
 	uint32_t i;
 	uint32_t ch, slice;
-	uint32_t dataL;
+	uint32_t data_l;
 	uint32_t tmp;
 	uint8_t high_byte[SLICE_CNT];
 	const uint32_t _par_CALVL_DEVICE_MAP = 1;
+
 	foreach_vch(ch) {
-	/***********************************************************************
-	BOARD SETTINGS (DQ,DM,VREF_DRIVING)
-	***********************************************************************/
+	/* BOARD SETTINGS (DQ,DM,VREF_DRIVING) */
 		for (slice = 0; slice < SLICE_CNT; slice++) {
 			high_byte[slice] =
-			    (Boardcnf->ch[ch].dqs_swap >> (4 * slice)) % 2;
+			    (board_cnf->ch[ch].dqs_swap >> (4 * slice)) % 2;
 			ddr_setval_s(ch, slice, _reg_PHY_DQ_DM_SWIZZLE0,
-				     Boardcnf->ch[ch].dq_swap[slice]);
+				     board_cnf->ch[ch].dq_swap[slice]);
 			ddr_setval_s(ch, slice, _reg_PHY_DQ_DM_SWIZZLE1,
-				     Boardcnf->ch[ch].dm_swap[slice]);
+				     board_cnf->ch[ch].dm_swap[slice]);
 			if (high_byte[slice]) {
 				/* HIGHER 16 BYTE */
 				ddr_setval_s(ch, slice,
@@ -1647,110 +1610,118 @@ static void ddr_config_sub(void)
 			}
 		}
 
-	/***********************************************************************
-		BOARD SETTINGS (CA,ADDR_SEL)
-	***********************************************************************/
-		dataL = (0x00ffffff & (uint32_t)(Boardcnf->ch[ch].ca_swap)) |
+	/* BOARD SETTINGS (CA,ADDR_SEL) */
+		data_l = (0x00ffffff & (uint32_t)(board_cnf->ch[ch].ca_swap)) |
 			0x00888888;
 
 		/* --- ADR_CALVL_SWIZZLE --- */
-		if (Prr_Product == PRR_PRODUCT_M3) {
-			ddr_setval(ch, _reg_PHY_ADR_CALVL_SWIZZLE0_0, dataL);
+		if (prr_product == PRR_PRODUCT_M3) {
+			ddr_setval(ch, _reg_PHY_ADR_CALVL_SWIZZLE0_0, data_l);
 			ddr_setval(ch, _reg_PHY_ADR_CALVL_SWIZZLE1_0,
 				   0x00000000);
-			ddr_setval(ch, _reg_PHY_ADR_CALVL_SWIZZLE0_1, dataL);
+			ddr_setval(ch, _reg_PHY_ADR_CALVL_SWIZZLE0_1, data_l);
 			ddr_setval(ch, _reg_PHY_ADR_CALVL_SWIZZLE1_1,
 				   0x00000000);
 			ddr_setval(ch, _reg_PHY_ADR_CALVL_DEVICE_MAP,
 				   _par_CALVL_DEVICE_MAP);
 		} else {
-			ddr_setval(ch, _reg_PHY_ADR_CALVL_SWIZZLE0, dataL);
+			ddr_setval(ch, _reg_PHY_ADR_CALVL_SWIZZLE0, data_l);
 			ddr_setval(ch, _reg_PHY_ADR_CALVL_SWIZZLE1, 0x00000000);
 			ddr_setval(ch, _reg_PHY_CALVL_DEVICE_MAP,
 				   _par_CALVL_DEVICE_MAP);
 		}
 
 		/* --- ADR_ADDR_SEL --- */
-		if ((Prr_Product == PRR_PRODUCT_H3)
-		    && (Prr_Cut > PRR_PRODUCT_11)) {
-			dataL = 0x00FFFFFF & Boardcnf->ch[ch].ca_swap;
+		if ((prr_product == PRR_PRODUCT_H3) &&
+		    (prr_cut > PRR_PRODUCT_11)) {
+			data_l = 0x00FFFFFF & board_cnf->ch[ch].ca_swap;
 		} else {
-			dataL = 0;
-			tmp = Boardcnf->ch[ch].ca_swap;
+			data_l = 0;
+			tmp = board_cnf->ch[ch].ca_swap;
 			for (i = 0; i < 6; i++) {
-				dataL |= ((tmp & 0x0f) << (i * 5));
+				data_l |= ((tmp & 0x0f) << (i * 5));
 				tmp = tmp >> 4;
 			}
 		}
-		ddr_setval(ch, _reg_PHY_ADR_ADDR_SEL, dataL);
+		ddr_setval(ch, _reg_PHY_ADR_ADDR_SEL, data_l);
 		if (ddr_phycaslice == 1) {
 			/* ----------- adr slice2 swap ----------- */
-			tmp  = (uint32_t)((Boardcnf->ch[ch].ca_swap) >> 40);
-			dataL = (tmp & 0x00ffffff) | 0x00888888;
+			tmp  = (uint32_t)((board_cnf->ch[ch].ca_swap) >> 40);
+			data_l = (tmp & 0x00ffffff) | 0x00888888;
 
 			/* --- ADR_CALVL_SWIZZLE --- */
-			if (Prr_Product == PRR_PRODUCT_M3) {
-				ddr_setval_s(ch, 2, _reg_PHY_ADR_CALVL_SWIZZLE0_0, dataL);
-				ddr_setval_s(ch, 2, _reg_PHY_ADR_CALVL_SWIZZLE1_0,
+			if (prr_product == PRR_PRODUCT_M3) {
+				ddr_setval_s(ch, 2,
+					     _reg_PHY_ADR_CALVL_SWIZZLE0_0,
+					     data_l);
+				ddr_setval_s(ch, 2,
+					     _reg_PHY_ADR_CALVL_SWIZZLE1_0,
 					     0x00000000);
-				ddr_setval_s(ch, 2, _reg_PHY_ADR_CALVL_SWIZZLE0_1, dataL);
-				ddr_setval_s(ch, 2, _reg_PHY_ADR_CALVL_SWIZZLE1_1,
+				ddr_setval_s(ch, 2,
+					     _reg_PHY_ADR_CALVL_SWIZZLE0_1,
+					     data_l);
+				ddr_setval_s(ch, 2,
+					     _reg_PHY_ADR_CALVL_SWIZZLE1_1,
 					     0x00000000);
-				ddr_setval_s(ch, 2, _reg_PHY_ADR_CALVL_DEVICE_MAP,
+				ddr_setval_s(ch, 2,
+					     _reg_PHY_ADR_CALVL_DEVICE_MAP,
 					     _par_CALVL_DEVICE_MAP);
 			} else {
-				ddr_setval_s(ch, 2, _reg_PHY_ADR_CALVL_SWIZZLE0, dataL);
-				ddr_setval_s(ch, 2, _reg_PHY_ADR_CALVL_SWIZZLE1,
+				ddr_setval_s(ch, 2,
+					     _reg_PHY_ADR_CALVL_SWIZZLE0,
+					     data_l);
+				ddr_setval_s(ch, 2,
+					     _reg_PHY_ADR_CALVL_SWIZZLE1,
 					     0x00000000);
-				ddr_setval_s(ch, 2, _reg_PHY_CALVL_DEVICE_MAP,
+				ddr_setval_s(ch, 2,
+					     _reg_PHY_CALVL_DEVICE_MAP,
 					     _par_CALVL_DEVICE_MAP);
 			}
 
 			/* --- ADR_ADDR_SEL --- */
-			dataL = 0;
+			data_l = 0;
 			for (i = 0; i < 6; i++) {
-				dataL |= ((tmp & 0x0f) << (i * 5));
+				data_l |= ((tmp & 0x0f) << (i * 5));
 				tmp = tmp >> 4;
 			}
 
-			ddr_setval_s(ch, 2, _reg_PHY_ADR_ADDR_SEL, dataL);
+			ddr_setval_s(ch, 2, _reg_PHY_ADR_ADDR_SEL, data_l);
 		}
 
-	/***********************************************************************
-		BOARD SETTINGS (BYTE_ORDER_SEL)
-	***********************************************************************/
-		if (Prr_Product == PRR_PRODUCT_M3) {
+	/* BOARD SETTINGS (BYTE_ORDER_SEL) */
+		if (prr_product == PRR_PRODUCT_M3) {
 			/* --- DATA_BYTE_SWAP --- */
-			dataL = 0;
-			tmp = Boardcnf->ch[ch].dqs_swap;
+			data_l = 0;
+			tmp = board_cnf->ch[ch].dqs_swap;
 			for (i = 0; i < 4; i++) {
-				dataL |= ((tmp & 0x03) << (i * 2));
+				data_l |= ((tmp & 0x03) << (i * 2));
 				tmp = tmp >> 4;
 			}
 		} else {
 			/* --- DATA_BYTE_SWAP --- */
-			dataL = Boardcnf->ch[ch].dqs_swap;
+			data_l = board_cnf->ch[ch].dqs_swap;
 			ddr_setval(ch, _reg_PI_DATA_BYTE_SWAP_EN, 0x01);
 			ddr_setval(ch, _reg_PI_DATA_BYTE_SWAP_SLICE0,
-				   (dataL) & 0x0f);
+				   (data_l) & 0x0f);
 			ddr_setval(ch, _reg_PI_DATA_BYTE_SWAP_SLICE1,
-				   (dataL >> 4 * 1) & 0x0f);
+				   (data_l >> 4 * 1) & 0x0f);
 			ddr_setval(ch, _reg_PI_DATA_BYTE_SWAP_SLICE2,
-				   (dataL >> 4 * 2) & 0x0f);
+				   (data_l >> 4 * 2) & 0x0f);
 			ddr_setval(ch, _reg_PI_DATA_BYTE_SWAP_SLICE3,
-				   (dataL >> 4 * 3) & 0x0f);
+				   (data_l >> 4 * 3) & 0x0f);
 
 			ddr_setval(ch, _reg_PHY_DATA_BYTE_ORDER_SEL_HIGH, 0x00);
 		}
-		ddr_setval(ch, _reg_PHY_DATA_BYTE_ORDER_SEL, dataL);
+		ddr_setval(ch, _reg_PHY_DATA_BYTE_ORDER_SEL, data_l);
 	}
 }
 
-static void get_ca_swizzle(uint32_t ch, uint32_t ddr_csn, uint32_t * p_swz)
+static void get_ca_swizzle(uint32_t ch, uint32_t ddr_csn, uint32_t *p_swz)
 {
 	uint32_t slice;
 	uint32_t tmp;
 	uint32_t tgt;
+
 	if (ddr_csn / 2) {
 		tgt = 3;
 	} else {
@@ -1758,11 +1729,11 @@ static void get_ca_swizzle(uint32_t ch, uint32_t ddr_csn, uint32_t * p_swz)
 	}
 
 	for (slice = 0; slice < SLICE_CNT; slice++) {
-		tmp = (Boardcnf->ch[ch].dqs_swap >> (4 * slice)) & 0x0f;
+		tmp = (board_cnf->ch[ch].dqs_swap >> (4 * slice)) & 0x0f;
 		if (tgt == tmp)
 			break;
 	}
-	tmp = 0x00FFFFFF & Boardcnf->ch[ch].ca_swap;
+	tmp = 0x00FFFFFF & board_cnf->ch[ch].ca_swap;
 	if (slice % 2)
 		tmp |= 0x00888888;
 	*p_swz = tmp;
@@ -1771,7 +1742,7 @@ static void get_ca_swizzle(uint32_t ch, uint32_t ddr_csn, uint32_t * p_swz)
 static void ddr_config_sub_h3v1x(void)
 {
 	uint32_t ch, slice;
-	uint32_t dataL;
+	uint32_t data_l;
 	uint32_t tmp;
 	uint8_t high_byte[SLICE_CNT];
 	uint32_t ca_swizzle;
@@ -1788,19 +1759,18 @@ static void ddr_config_sub_h3v1x(void)
 	const uint16_t o_mr32_mr40 = 0x5a3c;
 
 	foreach_vch(ch) {
-	/***********************************************************************
-		BOARD SETTINGS (DQ,DM,VREF_DRIVING)
-	***********************************************************************/
+	/* BOARD SETTINGS (DQ,DM,VREF_DRIVING) */
 		csmap = 0;
 		for (slice = 0; slice < SLICE_CNT; slice++) {
-			tmp = (Boardcnf->ch[ch].dqs_swap >> (4 * slice)) & 0x0f;
+			tmp = (board_cnf->ch[ch].dqs_swap >> (4 * slice)) &
+			      0x0f;
 			high_byte[slice] = tmp % 2;
 			if (tmp == 1 && (slice >= 2))
 				csmap |= 0x05;
 			if (tmp == 3 && (slice >= 2))
 				csmap |= 0x50;
 			ddr_setval_s(ch, slice, _reg_PHY_DQ_SWIZZLING,
-				     Boardcnf->ch[ch].dq_swap[slice]);
+				     board_cnf->ch[ch].dq_swap[slice]);
 			if (high_byte[slice]) {
 				/* HIGHER 16 BYTE */
 				ddr_setval_s(ch, slice,
@@ -1813,10 +1783,8 @@ static void ddr_config_sub_h3v1x(void)
 					     0x01);
 			}
 		}
-	/***********************************************************************
-		BOARD SETTINGS (CA,ADDR_SEL)
-	***********************************************************************/
-		ca = 0x00FFFFFF & Boardcnf->ch[ch].ca_swap;
+	/* BOARD SETTINGS (CA,ADDR_SEL) */
+		ca = 0x00FFFFFF & board_cnf->ch[ch].ca_swap;
 		ddr_setval(ch, _reg_PHY_ADR_ADDR_SEL, ca);
 		ddr_setval(ch, _reg_PHY_CALVL_CS_MAP, csmap);
 
@@ -1839,7 +1807,7 @@ static void ddr_config_sub_h3v1x(void)
 			else
 				o_inv = o_mr15;
 
-			tmp = Boardcnf->ch[ch].dq_swap[slice];
+			tmp = board_cnf->ch[ch].dq_swap[slice];
 			inv = 0;
 			j = 0;
 			for (bit_soc = 0; bit_soc < 8; bit_soc++) {
@@ -1848,13 +1816,13 @@ static void ddr_config_sub_h3v1x(void)
 				if (o_inv & (1U << bit_mem))
 					inv |= (1U << bit_soc);
 			}
-			dataL = o_mr32_mr40;
+			data_l = o_mr32_mr40;
 			if (!high_byte[slice])
-				dataL |= (inv << 24);
+				data_l |= (inv << 24);
 			if (high_byte[slice])
-				dataL |= (inv << 16);
+				data_l |= (inv << 16);
 			ddr_setval_s(ch, slice, _reg_PHY_LP4_RDLVL_PATT8,
-				     dataL);
+				     data_l);
 		}
 	}
 }
@@ -1863,7 +1831,7 @@ static void ddr_config(void)
 {
 	int32_t i;
 	uint32_t ch, slice;
-	uint32_t dataL;
+	uint32_t data_l;
 	uint32_t tmp;
 	int8_t _adj;
 	int16_t adj;
@@ -1874,23 +1842,19 @@ static void ddr_config(void)
 	} patt;
 	uint16_t patm;
 
-	/***********************************************************************
-	configure ddrphy registers
-	***********************************************************************/
-	if ((Prr_Product == PRR_PRODUCT_H3) && (Prr_Cut <= PRR_PRODUCT_11)) {
+	/* configure ddrphy registers */
+	if ((prr_product == PRR_PRODUCT_H3) && (prr_cut <= PRR_PRODUCT_11)) {
 		ddr_config_sub_h3v1x();
-	} else {
-		ddr_config_sub();	/*  H3 Ver.2.0 or later/M3-N/V3H is same as M3-W */
+	} else {	/*  H3 Ver.2.0 or later/M3-N/V3H is same as M3-W */
+		ddr_config_sub();
 	}
 
-	/***********************************************************************
-	WDQ_USER_PATT
-	***********************************************************************/
+	/* WDQ_USER_PATT */
 	foreach_vch(ch) {
 		for (slice = 0; slice < SLICE_CNT; slice++) {
 			patm = 0;
 			for (i = 0; i < 16; i++) {
-				tmp = Boardcnf->ch[ch].wdqlvl_patt[i];
+				tmp = board_cnf->ch[ch].wdqlvl_patt[i];
 				patt.ui8[i] = tmp & 0xff;
 				if (tmp & 0x100)
 					patm |= (1U << i);
@@ -1907,119 +1871,112 @@ static void ddr_config(void)
 		}
 	}
 
-	/***********************************************************************
-	CACS DLY
-	***********************************************************************/
-	dataL = Boardcnf->cacs_dly + _f_scale_adj(Boardcnf->cacs_dly_adj);
-	reg_ddrphy_write_a(ddr_regdef_adr(_reg_PHY_FREQ_SEL_MULTICAST_EN), 0x00U);
+	/* CACS DLY */
+	data_l = board_cnf->cacs_dly + _f_scale_adj(board_cnf->cacs_dly_adj);
+	reg_ddrphy_write_a(ddr_regdef_adr(_reg_PHY_FREQ_SEL_MULTICAST_EN),
+			   0x00U);
 	foreach_vch(ch) {
-		for (i = 0; i < (_reg_PHY_CLK_CACS_SLAVE_DELAY_X_NUM - 4); i++) {
-			adj = _f_scale_adj(Boardcnf->ch[ch].cacs_adj[i]);
+		for (i = 0; i < _reg_PHY_CLK_CACS_SLAVE_DELAY_X_NUM - 4; i++) {
+			adj = _f_scale_adj(board_cnf->ch[ch].cacs_adj[i]);
 			ddrtbl_setval(_cnf_DDR_PHY_ADR_V_REGSET,
 				      _reg_PHY_CLK_CACS_SLAVE_DELAY_X[i],
-				      dataL + adj);
+				      data_l + adj);
 			reg_ddrphy_write(ch,
-					ddr_regdef_adr(
-					_reg_PHY_CLK_CACS_SLAVE_DELAY_X[i]),
-					_cnf_DDR_PHY_ADR_V_REGSET[
-					ddr_regdef_adr(
-					_reg_PHY_CLK_CACS_SLAVE_DELAY_X[i]) -
+					 ddr_regdef_adr
+					 (_reg_PHY_CLK_CACS_SLAVE_DELAY_X[i]),
+					_cnf_DDR_PHY_ADR_V_REGSET
+					[ddr_regdef_adr
+					(_reg_PHY_CLK_CACS_SLAVE_DELAY_X[i]) -
 					DDR_PHY_ADR_V_REGSET_OFS]);
 		}
 
 		for (i = (_reg_PHY_CLK_CACS_SLAVE_DELAY_X_NUM - 4);
 		     i < _reg_PHY_CLK_CACS_SLAVE_DELAY_X_NUM; i++) {
-			adj = _f_scale_adj(Boardcnf->ch[ch].cacs_adj[i]);
+			adj = _f_scale_adj(board_cnf->ch[ch].cacs_adj[i]);
 			ddrtbl_setval(_cnf_DDR_PHY_ADR_G_REGSET,
 				      _reg_PHY_CLK_CACS_SLAVE_DELAY_X[i],
-				      dataL + adj);
+				      data_l + adj);
 			reg_ddrphy_write(ch,
-					ddr_regdef_adr(
-					_reg_PHY_CLK_CACS_SLAVE_DELAY_X[i]),
-					_cnf_DDR_PHY_ADR_G_REGSET[
-					ddr_regdef_adr(
-					_reg_PHY_CLK_CACS_SLAVE_DELAY_X[i]) -
+					 ddr_regdef_adr
+					 (_reg_PHY_CLK_CACS_SLAVE_DELAY_X[i]),
+					_cnf_DDR_PHY_ADR_G_REGSET
+					[ddr_regdef_adr
+					(_reg_PHY_CLK_CACS_SLAVE_DELAY_X[i]) -
 					DDR_PHY_ADR_G_REGSET_OFS]);
 		}
 
 		if (ddr_phycaslice == 1) {
 			for (i = 0; i < 6; i++) {
-				adj = _f_scale_adj(
-					Boardcnf->ch[ch].cacs_adj[
-					i + _reg_PHY_CLK_CACS_SLAVE_DELAY_X_NUM]);
+				adj = _f_scale_adj
+					(board_cnf->ch[ch].cacs_adj
+					[i +
+					_reg_PHY_CLK_CACS_SLAVE_DELAY_X_NUM]);
 				ddrtbl_setval(_cnf_DDR_PHY_ADR_V_REGSET,
-					      _reg_PHY_CLK_CACS_SLAVE_DELAY_X[i],
-					      dataL + adj);
+					      _reg_PHY_CLK_CACS_SLAVE_DELAY_X
+					      [i],
+					      data_l + adj);
 				reg_ddrphy_write(ch,
-					ddr_regdef_adr(
-					_reg_PHY_CLK_CACS_SLAVE_DELAY_X[i]) +
+						 ddr_regdef_adr
+					(_reg_PHY_CLK_CACS_SLAVE_DELAY_X[i]) +
 					0x0100,
-					_cnf_DDR_PHY_ADR_V_REGSET[
-					ddr_regdef_adr(
-					_reg_PHY_CLK_CACS_SLAVE_DELAY_X[i]) -
+					_cnf_DDR_PHY_ADR_V_REGSET
+					[ddr_regdef_adr
+					(_reg_PHY_CLK_CACS_SLAVE_DELAY_X[i]) -
 					DDR_PHY_ADR_V_REGSET_OFS]);
 			}
 		}
 	}
 
 	reg_ddrphy_write_a(ddr_regdef_adr(_reg_PHY_FREQ_SEL_MULTICAST_EN),
-		(0x01U << ddr_regdef_lsb(_reg_PHY_FREQ_SEL_MULTICAST_EN)));
+			   BIT(ddr_regdef_lsb(_reg_PHY_FREQ_SEL_MULTICAST_EN)));
 
-	/***********************************************************************
-	WDQDM DLY
-	***********************************************************************/
-	dataL = Boardcnf->dqdm_dly_w;
+	/* WDQDM DLY */
+	data_l = board_cnf->dqdm_dly_w;
 	foreach_vch(ch) {
 		for (slice = 0; slice < SLICE_CNT; slice++) {
 			for (i = 0; i <= 8; i++) {
 				dq = slice * 8 + i;
 				if (i == 8)
-					_adj = Boardcnf->ch[ch].dm_adj_w[slice];
+					_adj = board_cnf->ch[ch].dm_adj_w[slice];
 				else
-					_adj = Boardcnf->ch[ch].dq_adj_w[dq];
+					_adj = board_cnf->ch[ch].dq_adj_w[dq];
 				adj = _f_scale_adj(_adj);
 				ddr_setval_s(ch, slice,
 					     _reg_PHY_CLK_WRX_SLAVE_DELAY[i],
-					     dataL + adj);
+					     data_l + adj);
 			}
 		}
 	}
 
-	/***********************************************************************
-	RDQDM DLY
-	***********************************************************************/
-	dataL = Boardcnf->dqdm_dly_r;
+	/* RDQDM DLY */
+	data_l = board_cnf->dqdm_dly_r;
 	foreach_vch(ch) {
 		for (slice = 0; slice < SLICE_CNT; slice++) {
 			for (i = 0; i <= 8; i++) {
 				dq = slice * 8 + i;
 				if (i == 8)
-					_adj = Boardcnf->ch[ch].dm_adj_r[slice];
+					_adj = board_cnf->ch[ch].dm_adj_r[slice];
 				else
-					_adj = Boardcnf->ch[ch].dq_adj_r[dq];
+					_adj = board_cnf->ch[ch].dq_adj_r[dq];
 				adj = _f_scale_adj(_adj);
 				ddr_setval_s(ch, slice,
 					     _reg_PHY_RDDQS_X_FALL_SLAVE_DELAY
-					     [i], dataL + adj);
+					     [i], data_l + adj);
 				ddr_setval_s(ch, slice,
 					     _reg_PHY_RDDQS_X_RISE_SLAVE_DELAY
-					     [i], dataL + adj);
+					     [i], data_l + adj);
 			}
 		}
 	}
 }
 
-/*******************************************************************************
- *	DBSC register setting functions
- ******************************************************************************/
+/* DBSC register setting functions */
 static void dbsc_regset_pre(void)
 {
 	uint32_t ch, csab;
-	uint32_t dataL;
+	uint32_t data_l;
 
-	/***********************************************************************
-	PRIMARY SETTINGS
-	***********************************************************************/
+	/* PRIMARY SETTINGS */
 	/* LPDDR4, BL=16, DFI interface */
 	mmio_write_32(DBSC_DBKIND, 0x0000000a);
 	mmio_write_32(DBSC_DBBL, 0x00000002);
@@ -2029,30 +1986,33 @@ static void dbsc_regset_pre(void)
 	mmio_write_32(DBSC_DBSYSCONF1, 0x00000002);
 
 	/* Chanel map (H3 Ver.1.x) */
-	if ((Prr_Product == PRR_PRODUCT_H3) && (Prr_Cut <= PRR_PRODUCT_11))
+	if ((prr_product == PRR_PRODUCT_H3) && (prr_cut <= PRR_PRODUCT_11))
 		mmio_write_32(DBSC_DBSCHCNT1, 0x00001010);
 
 	/* DRAM SIZE REGISTER:
 	 * set all ranks as density=0(4Gb) for PHY initialization
 	 */
-	foreach_vch(ch)
-	    for (csab = 0; csab < 4; csab++)
-		mmio_write_32(DBSC_DBMEMCONF(ch, csab), DBMEMCONF_REGD(0));
+	foreach_vch(ch) {
+		for (csab = 0; csab < 4; csab++) {
+			mmio_write_32(DBSC_DBMEMCONF(ch, csab),
+				      DBMEMCONF_REGD(0));
+		}
+	}
 
-	if (Prr_Product == PRR_PRODUCT_M3) {
-		dataL = 0xe4e4e4e4;
+	if (prr_product == PRR_PRODUCT_M3) {
+		data_l = 0xe4e4e4e4;
 		foreach_ech(ch) {
 			if ((ddr_phyvalid & (1U << ch)))
-				dataL = (dataL & (~(0x000000FF << (ch * 8))))
-				    | (((Boardcnf->ch[ch].dqs_swap & 0x0003)
-					| ((Boardcnf->ch[ch].dqs_swap & 0x0030)
+				data_l = (data_l & (~(0x000000FF << (ch * 8))))
+				    | (((board_cnf->ch[ch].dqs_swap & 0x0003)
+					| ((board_cnf->ch[ch].dqs_swap & 0x0030)
 					   >> 2)
-					| ((Boardcnf->ch[ch].dqs_swap & 0x0300)
+					| ((board_cnf->ch[ch].dqs_swap & 0x0300)
 					   >> 4)
-					| ((Boardcnf->ch[ch].dqs_swap & 0x3000)
+					| ((board_cnf->ch[ch].dqs_swap & 0x3000)
 					   >> 6)) << (ch * 8));
 		}
-		mmio_write_32(DBSC_DBBSWAP, dataL);
+		mmio_write_32(DBSC_DBBSWAP, data_l);
 	}
 }
 
@@ -2060,20 +2020,20 @@ static void dbsc_regset(void)
 {
 	int32_t i;
 	uint32_t ch;
-	uint32_t dataL;
-	uint32_t dataL2;
+	uint32_t data_l;
+	uint32_t data_l2;
 	uint32_t tmp[4];
 
 	/* RFC */
-	if ((Prr_Product == PRR_PRODUCT_H3) && (Prr_Cut == PRR_PRODUCT_20)
-	    && (max_density == 0)) {
-		js2[JS2_tRFCab] =
+	if ((prr_product == PRR_PRODUCT_H3) && (prr_cut == PRR_PRODUCT_20) &&
+	    (max_density == 0)) {
+		js2[js2_trfcab] =
 		    _f_scale(ddr_mbps, ddr_mbpsdiv,
-			     1UL * jedec_spec2_tRFC_ab[1] * 1000, 0);
+			     1UL * jedec_spec2_trfc_ab[1] * 1000, 0);
 	} else {
-		js2[JS2_tRFCab] =
+		js2[js2_trfcab] =
 		    _f_scale(ddr_mbps, ddr_mbpsdiv,
-			     1UL * jedec_spec2_tRFC_ab[max_density] *
+			     1UL * jedec_spec2_trfc_ab[max_density] *
 			     1000, 0);
 	}
 
@@ -2087,46 +2047,46 @@ static void dbsc_regset(void)
 	mmio_write_32(DBSC_DBTR(2), 0);
 
 	/* DBTR3.TRCD: tRCD */
-	mmio_write_32(DBSC_DBTR(3), js2[JS2_tRCD]);
+	mmio_write_32(DBSC_DBTR(3), js2[js2_trcd]);
 
 	/* DBTR4.TRPA,TRP: tRPab,tRPpb */
-	mmio_write_32(DBSC_DBTR(4), (js2[JS2_tRPab] << 16) | js2[JS2_tRPpb]);
+	mmio_write_32(DBSC_DBTR(4), (js2[js2_trpab] << 16) | js2[js2_trppb]);
 
 	/* DBTR5.TRC : use tRCpb */
-	mmio_write_32(DBSC_DBTR(5), js2[JS2_tRCpb]);
+	mmio_write_32(DBSC_DBTR(5), js2[js2_trcpb]);
 
 	/* DBTR6.TRAS : tRAS */
-	mmio_write_32(DBSC_DBTR(6), js2[JS2_tRAS]);
+	mmio_write_32(DBSC_DBTR(6), js2[js2_tras]);
 
 	/* DBTR7.TRRD : tRRD */
-	mmio_write_32(DBSC_DBTR(7), (js2[JS2_tRRD] << 16) | js2[JS2_tRRD]);
+	mmio_write_32(DBSC_DBTR(7), (js2[js2_trrd] << 16) | js2[js2_trrd]);
 
 	/* DBTR8.TFAW : tFAW */
-	mmio_write_32(DBSC_DBTR(8), js2[JS2_tFAW]);
+	mmio_write_32(DBSC_DBTR(8), js2[js2_tfaw]);
 
 	/* DBTR9.TRDPR : tRTP */
-	mmio_write_32(DBSC_DBTR(9), js2[JS2_tRTP]);
+	mmio_write_32(DBSC_DBTR(9), js2[js2_trtp]);
 
-	/* DBTR10.TWR : nWR */
-	mmio_write_32(DBSC_DBTR(10), js1[js1_ind].nWR);
+	/* DBTR10.TWR : nwr */
+	mmio_write_32(DBSC_DBTR(10), js1[js1_ind].nwr);
 
 	/* DBTR11.TRDWR : RL + tDQSCK + BL/2 + Rounddown(tRPST) - WL + tWPRE */
 	mmio_write_32(DBSC_DBTR(11),
-		      RL + js2[JS2_tDQSCK] + (16 / 2) + 1 - WL + 2 + 2);
+		      RL + js2[js2_tdqsck] + (16 / 2) + 1 - WL + 2 + 2);
 
 	/* DBTR12.TWRRD : WL + 1 + BL/2 + tWTR */
-	dataL = WL + 1 + (16 / 2) + js2[JS2_tWTR];
-	mmio_write_32(DBSC_DBTR(12), (dataL << 16) | dataL);
+	data_l = WL + 1 + (16 / 2) + js2[js2_twtr];
+	mmio_write_32(DBSC_DBTR(12), (data_l << 16) | data_l);
 
 	/* DBTR13.TRFCAB : tRFCab */
-	mmio_write_32(DBSC_DBTR(13), (js2[JS2_tRFCab]));
+	mmio_write_32(DBSC_DBTR(13), (js2[js2_trfcab]));
 
 	/* DBTR14.TCKEHDLL,tCKEH : tCKEHCMD,tCKEHCMD */
 	mmio_write_32(DBSC_DBTR(14),
-		      (js2[JS2_tCKEHCMD] << 16) | (js2[JS2_tCKEHCMD]));
+		      (js2[js2_tckehcmd] << 16) | (js2[js2_tckehcmd]));
 
 	/* DBTR15.TCKESR,TCKEL : tSR,tCKELPD */
-	mmio_write_32(DBSC_DBTR(15), (js2[JS2_tSR] << 16) | (js2[JS2_tCKELPD]));
+	mmio_write_32(DBSC_DBTR(15), (js2[js2_tsr] << 16) | (js2[js2_tckelpd]));
 
 	/* DBTR16 */
 	/* WDQL : tphy_wrlat + tphy_wrdata */
@@ -2149,13 +2109,13 @@ static void dbsc_regset(void)
 	/* WRCSGAP = 5 */
 	tmp[1] = 5;
 	/* RDCSLAT = RDLAT_ADJ +2 */
-	if (Prr_Product == PRR_PRODUCT_M3) {
+	if (prr_product == PRR_PRODUCT_M3) {
 		tmp[2] = tmp[3];
 	} else {
 		tmp[2] = tmp[3] + 2;
 	}
 	/* RDCSGAP = 6 */
-	if (Prr_Product == PRR_PRODUCT_M3) {
+	if (prr_product == PRR_PRODUCT_M3) {
 		tmp[3] = 4;
 	} else {
 		tmp[3] = 6;
@@ -2165,7 +2125,7 @@ static void dbsc_regset(void)
 
 	/* DBTR17.TMODRD,TMOD,TRDMR: tMRR,tMRD,(0) */
 	mmio_write_32(DBSC_DBTR(17),
-		      (js2[JS2_tMRR] << 24) | (js2[JS2_tMRD] << 16));
+		      (js2[js2_tmrr] << 24) | (js2[js2_tmrd] << 16));
 
 	/* DBTR18.RODTL, RODTA, WODTL, WODTA : do not use in LPDDR4 */
 	mmio_write_32(DBSC_DBTR(18), 0);
@@ -2174,32 +2134,32 @@ static void dbsc_regset(void)
 	mmio_write_32(DBSC_DBTR(19), 0);
 
 	/* DBTR20.TXSDLL, TXS : tRFCab+tCKEHCMD */
-	dataL = js2[JS2_tRFCab] + js2[JS2_tCKEHCMD];
-	mmio_write_32(DBSC_DBTR(20), (dataL << 16) | dataL);
+	data_l = js2[js2_trfcab] + js2[js2_tckehcmd];
+	mmio_write_32(DBSC_DBTR(20), (data_l << 16) | data_l);
 
 	/* DBTR21.TCCD */
 	/* DBTR23.TCCD */
 	/* H3 Ver.1.0 cannot use TBTR23 feature */
 	if (ddr_tccd == 8 &&
-	    !((Prr_Product == PRR_PRODUCT_H3) && (Prr_Cut <= PRR_PRODUCT_10))
+	    !((prr_product == PRR_PRODUCT_H3) && (prr_cut <= PRR_PRODUCT_10))
 	    ) {
-		dataL = 8;
-		mmio_write_32(DBSC_DBTR(21), (dataL << 16) | dataL);
+		data_l = 8;
+		mmio_write_32(DBSC_DBTR(21), (data_l << 16) | data_l);
 		mmio_write_32(DBSC_DBTR(23), 0x00000002);
 	} else if (ddr_tccd <= 11) {
-		dataL = 11;
-		mmio_write_32(DBSC_DBTR(21), (dataL << 16) | dataL);
+		data_l = 11;
+		mmio_write_32(DBSC_DBTR(21), (data_l << 16) | data_l);
 		mmio_write_32(DBSC_DBTR(23), 0x00000000);
 	} else {
-		dataL = ddr_tccd;
-		mmio_write_32(DBSC_DBTR(21), (dataL << 16) | dataL);
+		data_l = ddr_tccd;
+		mmio_write_32(DBSC_DBTR(21), (data_l << 16) | data_l);
 		mmio_write_32(DBSC_DBTR(23), 0x00000000);
 	}
 
 	/* DBTR22.ZQLAT : */
-	dataL = js2[JS2_tZQCALns] * 100;	/*  1000 * 1000 ps */
-	dataL = (dataL << 16) | (js2[JS2_tZQLAT] + 24 + 20);
-	mmio_write_32(DBSC_DBTR(22), dataL);
+	data_l = js2[js2_tzqcalns] * 100;	/*  1000 * 1000 ps */
+	data_l = (data_l << 16) | (js2[js2_tzqlat] + 24 + 20);
+	mmio_write_32(DBSC_DBTR(22), data_l);
 
 	/* DBTR25 : do not use in LPDDR4 */
 	mmio_write_32(DBSC_DBTR(25), 0);
@@ -2214,35 +2174,33 @@ static void dbsc_regset(void)
 #define _par_DBRNK_VAL		(0x7007)
 
 	for (i = 0; i < 4; i++) {
-		dataL = (_par_DBRNK_VAL >> (i * 4)) & 0x0f;
-		if ((Prr_Product == PRR_PRODUCT_H3)
-		    && (Prr_Cut > PRR_PRODUCT_11) && (i == 0)) {
-			dataL += 1;
+		data_l = (_par_DBRNK_VAL >> (i * 4)) & 0x0f;
+		if ((prr_product == PRR_PRODUCT_H3) &&
+		    (prr_cut > PRR_PRODUCT_11) && (i == 0)) {
+			data_l += 1;
 		}
-		dataL2 = 0;
+		data_l2 = 0;
 		foreach_vch(ch) {
-			dataL2 = dataL2 | (dataL << (4 * ch));
+			data_l2 = data_l2 | (data_l << (4 * ch));
 		}
-		mmio_write_32(DBSC_DBRNK(2 + i), dataL2);
+		mmio_write_32(DBSC_DBRNK(2 + i), data_l2);
 	}
 	mmio_write_32(DBSC_DBADJ0, 0x00000000);
 
-	/***********************************************************************
-	timing registers for Scheduler
-	***********************************************************************/
+	/* timing registers for Scheduler */
 	/* SCFCTST0 */
 	/* SCFCTST0 ACT-ACT */
-	tmp[3] = 1UL * js2[JS2_tRCpb] * 800 * ddr_mbpsdiv / ddr_mbps;
+	tmp[3] = 1UL * js2[js2_trcpb] * 800 * ddr_mbpsdiv / ddr_mbps;
 	/* SCFCTST0 RDA-ACT */
 	tmp[2] =
-	    1UL * ((16 / 2) + js2[JS2_tRTP] - 8 +
-		   js2[JS2_tRPpb]) * 800 * ddr_mbpsdiv / ddr_mbps;
+	    1UL * ((16 / 2) + js2[js2_trtp] - 8 +
+		   js2[js2_trppb]) * 800 * ddr_mbpsdiv / ddr_mbps;
 	/* SCFCTST0 WRA-ACT */
 	tmp[1] =
 	    1UL * (WL + 1 + (16 / 2) +
-		   js1[js1_ind].nWR) * 800 * ddr_mbpsdiv / ddr_mbps;
+		   js1[js1_ind].nwr) * 800 * ddr_mbpsdiv / ddr_mbps;
 	/* SCFCTST0 PRE-ACT */
-	tmp[0] = 1UL * js2[JS2_tRPpb];
+	tmp[0] = 1UL * js2[js2_trppb];
 	mmio_write_32(DBSC_SCFCTST0,
 		      (tmp[3] << 24) | (tmp[2] << 16) | (tmp[1] << 8) | tmp[0]);
 
@@ -2256,7 +2214,7 @@ static void dbsc_regset(void)
 	    1UL * (mmio_read_32(DBSC_DBTR(12)) & 0xff) * 800 * ddr_mbpsdiv /
 	    ddr_mbps;
 	/* SCFCTST1 ACT-RD/WR */
-	tmp[1] = 1UL * js2[JS2_tRCD] * 800 * ddr_mbpsdiv / ddr_mbps;
+	tmp[1] = 1UL * js2[js2_trcd] * 800 * ddr_mbpsdiv / ddr_mbps;
 	/* SCFCTST1 ASYNCOFS */
 	tmp[0] = 12;
 	mmio_write_32(DBSC_SCFCTST1,
@@ -2264,26 +2222,26 @@ static void dbsc_regset(void)
 
 	/* DBSCHRW1 */
 	/* DBSCHRW1 SCTRFCAB */
-	tmp[0] = 1UL * js2[JS2_tRFCab] * 800 * ddr_mbpsdiv / ddr_mbps;
-	dataL = (((mmio_read_32(DBSC_DBTR(16)) & 0x00FF0000) >> 16)
+	tmp[0] = 1UL * js2[js2_trfcab] * 800 * ddr_mbpsdiv / ddr_mbps;
+	data_l = (((mmio_read_32(DBSC_DBTR(16)) & 0x00FF0000) >> 16)
 		 + (mmio_read_32(DBSC_DBTR(22)) & 0x0000FFFF)
 		 + (0x28 * 2)) * 400 * 2 * ddr_mbpsdiv / ddr_mbps + 7;
-	if (tmp[0] < dataL)
-		tmp[0] = dataL;
+	if (tmp[0] < data_l)
+		tmp[0] = data_l;
 
-	if ((Prr_Product == PRR_PRODUCT_M3) && (Prr_Cut < PRR_PRODUCT_30)) {
+	if ((prr_product == PRR_PRODUCT_M3) && (prr_cut < PRR_PRODUCT_30)) {
 		mmio_write_32(DBSC_DBSCHRW1, tmp[0]
 			+ ((mmio_read_32(DBSC_DBTR(22)) & 0x0000FFFF)
-			* 400 * 2 * ddr_mbpsdiv +(ddr_mbps-1))/ddr_mbps - 3);
+			* 400 * 2 * ddr_mbpsdiv + (ddr_mbps - 1)) /
+			ddr_mbps - 3);
 	} else {
 		mmio_write_32(DBSC_DBSCHRW1, tmp[0]
 			+ ((mmio_read_32(DBSC_DBTR(22)) & 0x0000FFFF)
-			* 400 * 2 * ddr_mbpsdiv +(ddr_mbps-1))/ddr_mbps);
+			* 400 * 2 * ddr_mbpsdiv + (ddr_mbps - 1)) /
+			ddr_mbps);
 	}
 
-	/***********************************************************************
-	QOS and CAM
-	***********************************************************************/
+	/* QOS and CAM */
 #ifdef ddr_qos_init_setting	/*  only for non qos_init */
 	/*wbkwait(0004), wbkmdhi(4,2),wbkmdlo(1,8) */
 	mmio_write_32(DBSC_DBCAM0CNF1, 0x00043218);
@@ -2329,18 +2287,18 @@ static void dbsc_regset(void)
 	mmio_write_32(QOSCTRL_RAEN, 0x00000001U);
 #endif /* ddr_qos_init_setting */
 	/* H3 Ver.1.1 need to set monitor function */
-	if ((Prr_Product == PRR_PRODUCT_H3) && (Prr_Cut == PRR_PRODUCT_11)) {
+	if ((prr_product == PRR_PRODUCT_H3) && (prr_cut == PRR_PRODUCT_11)) {
 		mmio_write_32(DBSC_DBMONCONF4, 0x00700000);
 	}
 
-	if (Prr_Product == PRR_PRODUCT_H3) {
-		if (Prr_Cut == PRR_PRODUCT_10) {
+	if (prr_product == PRR_PRODUCT_H3) {
+		if (prr_cut == PRR_PRODUCT_10) {
 			/* resrdis, simple mode, sc off */
 			mmio_write_32(DBSC_DBBCAMDIS, 0x00000007);
-		} else if (Prr_Cut == PRR_PRODUCT_11) {
+		} else if (prr_cut == PRR_PRODUCT_11) {
 			/* resrdis, simple mode         */
 			mmio_write_32(DBSC_DBBCAMDIS, 0x00000005);
-		} else if (Prr_Cut < PRR_PRODUCT_30) {
+		} else if (prr_cut < PRR_PRODUCT_30) {
 			/* H3 Ver.2.0                   */
 			/* resrdis                      */
 			mmio_write_32(DBSC_DBBCAMDIS, 0x00000001);
@@ -2357,7 +2315,7 @@ static void dbsc_regset(void)
 static void dbsc_regset_post(void)
 {
 	uint32_t ch, cs;
-	uint32_t dataL;
+	uint32_t data_l;
 	uint32_t slice, rdlat_max, rdlat_min;
 
 	rdlat_max = 0;
@@ -2369,18 +2327,17 @@ static void dbsc_regset_post(void)
 					ddr_setval_s(ch, slice,
 						     _reg_PHY_PER_CS_TRAINING_INDEX,
 						     cs);
-					dataL =
-					    ddr_getval_s(ch, slice,
-							 _reg_PHY_RDDQS_LATENCY_ADJUST);
-					if (dataL > rdlat_max)
-						rdlat_max = dataL;
-					if (dataL < rdlat_min)
-						rdlat_min = dataL;
+					data_l = ddr_getval_s(ch, slice,
+							      _reg_PHY_RDDQS_LATENCY_ADJUST);
+					if (data_l > rdlat_max)
+						rdlat_max = data_l;
+					if (data_l < rdlat_min)
+						rdlat_min = data_l;
 				}
 			}
 		}
 	}
-	if ((Prr_Product == PRR_PRODUCT_H3) && (Prr_Cut > PRR_PRODUCT_11)) {
+	if ((prr_product == PRR_PRODUCT_H3) && (prr_cut > PRR_PRODUCT_11)) {
 		mmio_write_32(DBSC_DBTR(24),
 			      ((rdlat_max * 2 - rdlat_min + 4) << 24) +
 			      ((rdlat_min + 2) << 16) +
@@ -2410,24 +2367,26 @@ static void dbsc_regset_post(void)
 	mmio_write_32(DBSC_DBBUS0CNF1, 0x00000010);
 
 	/*set DBI */
-	if (Boardcnf->dbi_en)
+	if (board_cnf->dbi_en)
 		mmio_write_32(DBSC_DBDBICNT, 0x00000003);
 
 	/* H3 Ver.2.0 or later/M3-N/V3H DBI wa */
-	if ((((Prr_Product == PRR_PRODUCT_H3) && (Prr_Cut > PRR_PRODUCT_11))
-	     || (Prr_Product == PRR_PRODUCT_M3N)
-	     || (Prr_Product == PRR_PRODUCT_V3H)) && (Boardcnf->dbi_en))
+	if ((((prr_product == PRR_PRODUCT_H3) &&
+	      (prr_cut > PRR_PRODUCT_11)) ||
+	     (prr_product == PRR_PRODUCT_M3N) ||
+	     (prr_product == PRR_PRODUCT_V3H)) &&
+	    board_cnf->dbi_en)
 		reg_ddrphy_write_a(0x00001010, 0x01000000);
 
 	/*set REFCYCLE */
-	dataL = (get_refperiod()) * ddr_mbps / 2000 / ddr_mbpsdiv;
-	mmio_write_32(DBSC_DBRFCNF1, 0x00080000 | (dataL & 0x0000ffff));
+	data_l = (get_refperiod()) * ddr_mbps / 2000 / ddr_mbpsdiv;
+	mmio_write_32(DBSC_DBRFCNF1, 0x00080000 | (data_l & 0x0000ffff));
 	mmio_write_32(DBSC_DBRFCNF2, 0x00010000 | DBSC_REFINTS);
 
 #ifdef DDR_BACKUPMODE
-	if (ddrBackup == DRAM_BOOT_STATUS_WARM) {
+	if (ddr_backup == DRAM_BOOT_STATUS_WARM) {
 #ifdef DDR_BACKUPMODE_HALF	/* for Half channel(ch0,1 only) */
-		PutStr(" DEBUG_MESS : DDR_BACKUPMODE_HALF ", 1);
+		DEBUG(" DEBUG_MESS : DDR_BACKUPMODE_HALF ", 1);
 		send_dbcmd(0x08040001);
 		wait_dbcmd();
 		send_dbcmd(0x0A040001);
@@ -2435,7 +2394,7 @@ static void dbsc_regset_post(void)
 		send_dbcmd(0x04040010);
 		wait_dbcmd();
 
-		if (Prr_Product == PRR_PRODUCT_H3) {
+		if (prr_product == PRR_PRODUCT_H3) {
 			send_dbcmd(0x08140001);
 			wait_dbcmd();
 			send_dbcmd(0x0A140001);
@@ -2457,11 +2416,16 @@ static void dbsc_regset_post(void)
 
 #if RCAR_REWT_TRAINING != 0
 	/* Periodic-WriteDQ Training seeting */
-	if (((Prr_Product == PRR_PRODUCT_H3) && (Prr_Cut <= PRR_PRODUCT_11))
-	    || ((Prr_Product == PRR_PRODUCT_M3) && (Prr_Cut == PRR_PRODUCT_10))) {
+	if (((prr_product == PRR_PRODUCT_H3) &&
+	     (prr_cut <= PRR_PRODUCT_11)) ||
+	    ((prr_product == PRR_PRODUCT_M3) &&
+	     (prr_cut == PRR_PRODUCT_10))) {
 		/* non : H3 Ver.1.x/M3-W Ver.1.0 not support */
 	} else {
-		/* H3 Ver.2.0 or later/M3-W Ver.1.1 or later/M3-N/V3H -> Periodic-WriteDQ Training seeting */
+		/*
+		 * H3 Ver.2.0 or later/M3-W Ver.1.1 or
+		 * later/M3-N/V3H -> Periodic-WriteDQ Training seeting
+		 */
 
 		/* Periodic WriteDQ Training seeting */
 		mmio_write_32(DBSC_DBDFIPMSTRCNF, 0x00000000);
@@ -2482,7 +2446,7 @@ static void dbsc_regset_post(void)
 		ddr_setval_ach(_reg_PI_TREF_F1, 0x0000);
 		ddr_setval_ach(_reg_PI_TREF_F2, 0x0000);
 
-		if (Prr_Product == PRR_PRODUCT_M3) {
+		if (prr_product == PRR_PRODUCT_M3) {
 			ddr_setval_ach(_reg_PI_WDQLVL_EN, 0x02);
 		} else {
 			ddr_setval_ach(_reg_PI_WDQLVL_EN_F1, 0x02);
@@ -2490,18 +2454,21 @@ static void dbsc_regset_post(void)
 		ddr_setval_ach(_reg_PI_WDQLVL_PERIODIC, 0x01);
 
 		/* DFI_PHYMSTR_ACK , WTmode setting */
-		mmio_write_32(DBSC_DBDFIPMSTRCNF, 0x00000011);	/* DFI_PHYMSTR_ACK: WTmode =b'01 */
+		/* DFI_PHYMSTR_ACK: WTmode =b'01 */
+		mmio_write_32(DBSC_DBDFIPMSTRCNF, 0x00000011);
 	}
 #endif /* RCAR_REWT_TRAINING */
 	/* periodic dram zqcal and phy ctrl update enable */
 	mmio_write_32(DBSC_DBCALCNF, 0x01000010);
-	if (((Prr_Product == PRR_PRODUCT_H3) && (Prr_Cut <= PRR_PRODUCT_11))
-	    || ((Prr_Product == PRR_PRODUCT_M3) && (Prr_Cut < PRR_PRODUCT_30))) {
+	if (((prr_product == PRR_PRODUCT_H3) &&
+	     (prr_cut <= PRR_PRODUCT_11)) ||
+	    ((prr_product == PRR_PRODUCT_M3) &&
+	     (prr_cut < PRR_PRODUCT_30))) {
 		/* non : H3 Ver.1.x/M3-W Ver.1.x not support */
 	} else {
 #if RCAR_DRAM_SPLIT == 2
-		if ((Prr_Product == PRR_PRODUCT_H3)
-		    && (Boardcnf->phyvalid == 0x05))
+		if ((prr_product == PRR_PRODUCT_H3) &&
+		    (board_cnf->phyvalid == 0x05))
 			mmio_write_32(DBSC_DBDFICUPDCNF, 0x2a240001);
 		else
 			mmio_write_32(DBSC_DBDFICUPDCNF, 0x28240001);
@@ -2514,33 +2481,26 @@ static void dbsc_regset_post(void)
 	/* dram access enable */
 	mmio_write_32(DBSC_DBACEN, 0x00000001);
 
-	MSG_LF("dbsc_regset_post(done)");
-
+	MSG_LF(__func__ "(done)");
 }
 
-/*******************************************************************************
- *	DFI_INIT_START
- ******************************************************************************/
+/* DFI_INIT_START */
 static uint32_t dfi_init_start(void)
 {
 	uint32_t ch;
 	uint32_t phytrainingok;
 	uint32_t retry;
-	uint32_t dataL;
+	uint32_t data_l;
 	const uint32_t RETRY_MAX = 0x10000;
 
-	if ((Prr_Product == PRR_PRODUCT_H3) && (Prr_Cut <= PRR_PRODUCT_11)) {
-	/***********************************************************************
-		PLL3 Disable
-	***********************************************************************/
+	if ((prr_product == PRR_PRODUCT_H3) && (prr_cut <= PRR_PRODUCT_11)) {
+		/* PLL3 Disable */
 		/* protect register interface */
 		ddrphy_regif_idle();
 
 		pll3_control(0);
 
-	/***********************************************************************
-		init start
-	***********************************************************************/
+		/* init start */
 		/* dbdficnt0:
 		 * dfi_dram_clk_disable=1
 		 * dfi_frequency = 0
@@ -2572,15 +2532,13 @@ static uint32_t dfi_init_start(void)
 	    mmio_write_32(DBSC_DBPDCNT3(ch), 0x0000CF01);
 	dsb_sev();
 
-	/***********************************************************************
-	wait init_complete
-	***********************************************************************/
+	/* wait init_complete */
 	phytrainingok = 0;
 	retry = 0;
 	while (retry++ < RETRY_MAX) {
 		foreach_vch(ch) {
-			dataL = mmio_read_32(DBSC_DBDFISTAT(ch));
-			if (dataL & 0x00000001)
+			data_l = mmio_read_32(DBSC_DBDFISTAT(ch));
+			if (data_l & 0x00000001)
 				phytrainingok |= (1U << ch);
 		}
 		dsb_sev();
@@ -2590,12 +2548,10 @@ static uint32_t dfi_init_start(void)
 			ddr_setval_ach_as(_reg_SC_PHY_RX_CAL_START, 0x01);
 	}
 
-	/***********************************************************************
-	all ch ok?
-	***********************************************************************/
-	if ((phytrainingok & ddr_phyvalid) != ddr_phyvalid) {
-		return (0xff);
-	}
+	/* all ch ok? */
+	if ((phytrainingok & ddr_phyvalid) != ddr_phyvalid)
+		return 0xff;
+
 	/* dbdficnt0:
 	 * dfi_dram_clk_disable=0
 	 * dfi_frequency = 0
@@ -2609,14 +2565,12 @@ static uint32_t dfi_init_start(void)
 	return 0;
 }
 
-/*******************************************************************************
- *	drivablity setting : CMOS MODE ON/OFF
- ******************************************************************************/
+/* drivablity setting : CMOS MODE ON/OFF */
 static void change_lpddr4_en(uint32_t mode)
 {
 	uint32_t ch;
 	uint32_t i;
-	uint32_t dataL;
+	uint32_t data_l;
 	const uint32_t _reg_PHY_PAD_DRIVE_X[3] = {
 		_reg_PHY_PAD_ADDR_DRIVE,
 		_reg_PHY_PAD_CLK_DRIVE,
@@ -2625,31 +2579,30 @@ static void change_lpddr4_en(uint32_t mode)
 
 	foreach_vch(ch) {
 		for (i = 0; i < 3; i++) {
-			dataL = ddr_getval(ch, _reg_PHY_PAD_DRIVE_X[i]);
+			data_l = ddr_getval(ch, _reg_PHY_PAD_DRIVE_X[i]);
 			if (mode) {
-				dataL |= (1U << 14);
+				data_l |= (1U << 14);
 			} else {
-				dataL &= ~(1U << 14);
+				data_l &= ~(1U << 14);
 			}
-			ddr_setval(ch, _reg_PHY_PAD_DRIVE_X[i], dataL);
+			ddr_setval(ch, _reg_PHY_PAD_DRIVE_X[i], data_l);
 		}
 	}
 }
 
-/*******************************************************************************
- *	drivablity setting
- ******************************************************************************/
+/* drivablity setting */
 static uint32_t set_term_code(void)
 {
 	int32_t i;
 	uint32_t ch, index;
-	uint32_t dataL;
+	uint32_t data_l;
 	uint32_t chip_id[2];
 	uint32_t term_code;
 	uint32_t override;
 	uint32_t pvtr;
 	uint32_t pvtp;
 	uint32_t pvtn;
+
 	term_code = ddrtbl_getval(_cnf_DDR_PHY_ADR_G_REGSET,
 				  _reg_PHY_PAD_DATA_TERM);
 	override = 0;
@@ -2658,12 +2611,12 @@ static uint32_t set_term_code(void)
 
 	index = 0;
 	while (1) {
-		if (TermcodeBySample[index][0] == 0xffffffff) {
+		if (termcode_by_sample[index][0] == 0xffffffff) {
 			break;
 		}
-		if ((TermcodeBySample[index][0] == chip_id[0])
-		    && (TermcodeBySample[index][1] == chip_id[1])) {
-			term_code = TermcodeBySample[index][2];
+		if ((termcode_by_sample[index][0] == chip_id[0]) &&
+		    (termcode_by_sample[index][1] == chip_id[1])) {
+			term_code = termcode_by_sample[index][2];
 			override = 1;
 			break;
 		}
@@ -2672,14 +2625,14 @@ static uint32_t set_term_code(void)
 
 	if (override) {
 		for (index = 0; index < _reg_PHY_PAD_TERM_X_NUM; index++) {
-			dataL =
+			data_l =
 			    ddrtbl_getval(_cnf_DDR_PHY_ADR_G_REGSET,
 					  _reg_PHY_PAD_TERM_X[index]);
-			dataL = (dataL & 0xfffe0000) | term_code;
-			ddr_setval_ach(_reg_PHY_PAD_TERM_X[index], dataL);
+			data_l = (data_l & 0xfffe0000) | term_code;
+			ddr_setval_ach(_reg_PHY_PAD_TERM_X[index], data_l);
 		}
-	} else if ((Prr_Product == PRR_PRODUCT_M3)
-		   && (Prr_Cut == PRR_PRODUCT_10)) {
+	} else if ((prr_product == PRR_PRODUCT_M3) &&
+		   (prr_cut == PRR_PRODUCT_10)) {
 		/*  non */
 	} else {
 		ddr_setval_ach(_reg_PHY_PAD_TERM_X[0],
@@ -2690,139 +2643,148 @@ static uint32_t set_term_code(void)
 		ddr_setval_ach(_reg_PHY_CAL_START_0, 0x01);
 		foreach_vch(ch) {
 			do {
-				dataL =
+				data_l =
 				    ddr_getval(ch, _reg_PHY_CAL_RESULT2_OBS_0);
-			} while (!(dataL & 0x00800000));
+			} while (!(data_l & 0x00800000));
 		}
-		if ((Prr_Product == PRR_PRODUCT_H3)
-		    && (Prr_Cut <= PRR_PRODUCT_11)) {
+		if ((prr_product == PRR_PRODUCT_H3) &&
+		    (prr_cut <= PRR_PRODUCT_11)) {
 			foreach_vch(ch) {
-				dataL = ddr_getval(ch, _reg_PHY_PAD_TERM_X[0]);
-				pvtr = (dataL >> 12) & 0x1f;
+				data_l = ddr_getval(ch, _reg_PHY_PAD_TERM_X[0]);
+				pvtr = (data_l >> 12) & 0x1f;
 				pvtr += 8;
 				if (pvtr > 0x1f)
 					pvtr = 0x1f;
-				dataL =
+				data_l =
 				    ddr_getval(ch, _reg_PHY_CAL_RESULT2_OBS_0);
-				pvtn = (dataL >> 6) & 0x03f;
-				pvtp = (dataL >> 0) & 0x03f;
+				pvtn = (data_l >> 6) & 0x03f;
+				pvtp = (data_l >> 0) & 0x03f;
 
 				for (index = 0; index < _reg_PHY_PAD_TERM_X_NUM;
 				     index++) {
-					dataL =
+					data_l =
 					    ddrtbl_getval
 					    (_cnf_DDR_PHY_ADR_G_REGSET,
 					     _reg_PHY_PAD_TERM_X[index]);
-					dataL = (dataL & 0xfffe0000)
+					data_l = (data_l & 0xfffe0000)
 					    | (pvtr << 12)
 					    | (pvtn << 6)
 					    | (pvtp);
 					ddr_setval(ch,
 						   _reg_PHY_PAD_TERM_X[index],
-						   dataL);
+						   data_l);
 				}
 			}
-		} else {	/*  M3-W Ver.1.1 or later/H3 Ver.2.0 or later/M3-N/V3H */
+		} else {
+			/* M3-W Ver.1.1 or later/H3 Ver.2.0 or later/M3-N/V3H */
 			foreach_vch(ch) {
 				for (index = 0; index < _reg_PHY_PAD_TERM_X_NUM;
 				     index++) {
-					dataL =
+					data_l =
 					    ddr_getval(ch,
 						       _reg_PHY_PAD_TERM_X
 						       [index]);
 					ddr_setval(ch,
 						   _reg_PHY_PAD_TERM_X[index],
-						   (dataL & 0xFFFE0FFF) |
+						   (data_l & 0xFFFE0FFF) |
 						   0x00015000);
 				}
 			}
 		}
 	}
-	if ((Prr_Product == PRR_PRODUCT_H3) && (Prr_Cut <= PRR_PRODUCT_11)) {
-		/*  non */
+
+	if ((prr_product == PRR_PRODUCT_H3) && (prr_cut <= PRR_PRODUCT_11)) {
+		/* non */
 	} else {
 		ddr_padcal_tcompensate_getinit(override);
 	}
+
 	return 0;
 }
 
-/*******************************************************************************
- *	DDR mode register setting
- ******************************************************************************/
+/* DDR mode register setting */
 static void ddr_register_set(void)
 {
 	int32_t fspwp;
 	uint32_t tmp;
 
 	for (fspwp = 1; fspwp >= 0; fspwp--) {
-		/*MR13,fspwp */
-		send_dbcmd(0x0e840d08 | (fspwp << 6));
+		/*MR13, fspwp */
+		send_dbcmd(0x0e840d08 | ((2 - fspwp) << 6));
 
 		tmp =
 		    ddrtbl_getval(_cnf_DDR_PI_REGSET,
-				  _reg_PI_MR1_DATA_Fx_CSx[fspwp][0]);
+				  reg_pi_mr1_data_fx_csx[fspwp][0]);
 		send_dbcmd(0x0e840100 | tmp);
 
 		tmp =
 		    ddrtbl_getval(_cnf_DDR_PI_REGSET,
-				  _reg_PI_MR2_DATA_Fx_CSx[fspwp][0]);
+				  reg_pi_mr2_data_fx_csx[fspwp][0]);
 		send_dbcmd(0x0e840200 | tmp);
 
 		tmp =
 		    ddrtbl_getval(_cnf_DDR_PI_REGSET,
-				  _reg_PI_MR3_DATA_Fx_CSx[fspwp][0]);
+				  reg_pi_mr3_data_fx_csx[fspwp][0]);
 		send_dbcmd(0x0e840300 | tmp);
 
 		tmp =
 		    ddrtbl_getval(_cnf_DDR_PI_REGSET,
-				  _reg_PI_MR11_DATA_Fx_CSx[fspwp][0]);
+				  reg_pi_mr11_data_fx_csx[fspwp][0]);
 		send_dbcmd(0x0e840b00 | tmp);
 
 		tmp =
 		    ddrtbl_getval(_cnf_DDR_PI_REGSET,
-				  _reg_PI_MR12_DATA_Fx_CSx[fspwp][0]);
+				  reg_pi_mr12_data_fx_csx[fspwp][0]);
 		send_dbcmd(0x0e840c00 | tmp);
 
 		tmp =
 		    ddrtbl_getval(_cnf_DDR_PI_REGSET,
-				  _reg_PI_MR14_DATA_Fx_CSx[fspwp][0]);
+				  reg_pi_mr14_data_fx_csx[fspwp][0]);
 		send_dbcmd(0x0e840e00 | tmp);
 		/* MR22 */
 		send_dbcmd(0x0e841616);
+
+		/* ZQCAL start */
+		send_dbcmd(0x0d84004F);
+
+		/* ZQLAT */
+		send_dbcmd(0x0d840051);
 	}
+
+	/* MR13, fspwp */
+	send_dbcmd(0x0e840d08);
 }
 
-/*******************************************************************************
- *	Training handshake functions
- ******************************************************************************/
+/* Training handshake functions */
 static inline uint32_t wait_freqchgreq(uint32_t assert)
 {
-	uint32_t dataL;
+	uint32_t data_l;
 	uint32_t count;
 	uint32_t ch;
+
 	count = 100000;
 
 	/* H3 Ver.1.x cannot see frqchg_req */
-	if ((Prr_Product == PRR_PRODUCT_H3) && (Prr_Cut <= PRR_PRODUCT_11)) {
+	if ((prr_product == PRR_PRODUCT_H3) && (prr_cut <= PRR_PRODUCT_11)) {
 		return 0;
 	}
 
 	if (assert) {
 		do {
-			dataL = 1;
+			data_l = 1;
 			foreach_vch(ch) {
-				dataL &= mmio_read_32(DBSC_DBPDSTAT(ch));
+				data_l &= mmio_read_32(DBSC_DBPDSTAT(ch));
 			}
 			count = count - 1;
-		} while (((dataL & 0x01) != 0x01) & (count != 0));
+		} while (((data_l & 0x01) != 0x01) & (count != 0));
 	} else {
 		do {
-			dataL = 0;
+			data_l = 0;
 			foreach_vch(ch) {
-				dataL |= mmio_read_32(DBSC_DBPDSTAT(ch));
+				data_l |= mmio_read_32(DBSC_DBPDSTAT(ch));
 			}
 			count = count - 1;
-		} while (((dataL & 0x01) != 0x00) & (count != 0));
+		} while (((data_l & 0x01) != 0x00) & (count != 0));
 	}
 
 	return (count == 0);
@@ -2831,20 +2793,22 @@ static inline uint32_t wait_freqchgreq(uint32_t assert)
 static inline void set_freqchgack(uint32_t assert)
 {
 	uint32_t ch;
-	uint32_t dataL;
+	uint32_t data_l;
+
 	if (assert)
-		dataL = 0x0CF20000;
+		data_l = 0x0CF20000;
 	else
-		dataL = 0x00000000;
+		data_l = 0x00000000;
 
 	foreach_vch(ch)
-	    mmio_write_32(DBSC_DBPDCNT2(ch), dataL);
+	    mmio_write_32(DBSC_DBPDCNT2(ch), data_l);
 }
 
 static inline void set_dfifrequency(uint32_t freq)
 {
 	uint32_t ch;
-	if ((Prr_Product == PRR_PRODUCT_H3) && (Prr_Cut <= PRR_PRODUCT_11)) {
+
+	if ((prr_product == PRR_PRODUCT_H3) && (prr_cut <= PRR_PRODUCT_11)) {
 		foreach_vch(ch)
 		    mmio_clrsetbits_32(DBSC_DBPDCNT1(ch), 0x1fU, freq);
 	} else {
@@ -2863,7 +2827,7 @@ static uint32_t pll3_freq(uint32_t on)
 	timeout = wait_freqchgreq(1);
 
 	if (timeout) {
-		return (1);
+		return 1;
 	}
 
 	pll3_control(on);
@@ -2875,27 +2839,23 @@ static uint32_t pll3_freq(uint32_t on)
 
 	if (timeout) {
 		FATAL_MSG("BL2: Time out[2]\n");
-		return (1);
+		return 1;
 	}
-	return (0);
+	return 0;
 }
 
-/*******************************************************************************
- *	update dly
- ******************************************************************************/
+/* update dly */
 static void update_dly(void)
 {
 	ddr_setval_ach(_reg_SC_PHY_MANUAL_UPDATE, 0x01);
 	ddr_setval_ach(_reg_PHY_ADRCTL_MANUAL_UPDATE, 0x01);
 }
 
-/*******************************************************************************
- *	training by pi
- ******************************************************************************/
+/* training by pi */
 static uint32_t pi_training_go(void)
 {
 	uint32_t flag;
-	uint32_t dataL;
+	uint32_t data_l;
 	uint32_t retry;
 	const uint32_t RETRY_MAX = 4096 * 16;
 	uint32_t ch;
@@ -2905,11 +2865,7 @@ static uint32_t pi_training_go(void)
 	uint32_t complete;
 	uint32_t frqchg_req;
 
-	/* ********************************************************************* */
-
-	/***********************************************************************
-	pi_start
-	***********************************************************************/
+	/* pi_start */
 	ddr_setval_ach(_reg_PI_START, 0x01);
 	foreach_vch(ch)
 	    ddr_getval(ch, _reg_PI_INT_STATUS);
@@ -2918,9 +2874,7 @@ static uint32_t pi_training_go(void)
 	mmio_write_32(DBSC_DBDFIPMSTRCNF, 0x00000001);
 	dsb_sev();
 
-	/***********************************************************************
-	wait pi_int_status[0]
-	***********************************************************************/
+	/* wait pi_int_status[0] */
 	mst_ch = 0;
 	flag = 0;
 	complete = 0;
@@ -2930,8 +2884,8 @@ static uint32_t pi_training_go(void)
 		frqchg_req = mmio_read_32(DBSC_DBPDSTAT(mst_ch)) & 0x01;
 
 		/* H3 Ver.1.x cannot see frqchg_req */
-		if ((Prr_Product == PRR_PRODUCT_H3)
-		    && (Prr_Cut <= PRR_PRODUCT_11)) {
+		if ((prr_product == PRR_PRODUCT_H3) &&
+		    (prr_cut <= PRR_PRODUCT_11)) {
 			if ((retry % 4096) == 1) {
 				frqchg_req = 1;
 			} else {
@@ -2956,9 +2910,9 @@ static uint32_t pi_training_go(void)
 				foreach_vch(ch) {
 					if (complete & (1U << ch))
 						continue;
-					dataL =
+					data_l =
 					    ddr_getval(ch, _reg_PI_INT_STATUS);
-					if (dataL & 0x01) {
+					if (data_l & 0x01) {
 						complete |= (1U << ch);
 					}
 				}
@@ -2969,194 +2923,153 @@ static uint32_t pi_training_go(void)
 	} while (--retry);
 	foreach_vch(ch) {
 		/* dummy read */
-		dataL = ddr_getval_s(ch, 0, _reg_PHY_CAL_RESULT2_OBS_0);
-		dataL = ddr_getval(ch, _reg_PI_INT_STATUS);
-		ddr_setval(ch, _reg_PI_INT_ACK, dataL);
+		data_l = ddr_getval_s(ch, 0, _reg_PHY_CAL_RESULT2_OBS_0);
+		data_l = ddr_getval(ch, _reg_PI_INT_STATUS);
+		ddr_setval(ch, _reg_PI_INT_ACK, data_l);
 	}
 	if (ddrphy_regif_chk()) {
-		return (0xfd);
+		return 0xfd;
 	}
 	return complete;
 }
 
-/*******************************************************************************
- *	Initialize ddr
- ******************************************************************************/
+/* Initialize DDR */
 static uint32_t init_ddr(void)
 {
 	int32_t i;
-	uint32_t dataL;
+	uint32_t data_l;
 	uint32_t phytrainingok;
 	uint32_t ch, slice;
 	uint32_t err;
 	int16_t adj;
 
-	MSG_LF("init_ddr:0\n");
+	MSG_LF(__func__ ":0\n");
 
 #ifdef DDR_BACKUPMODE
-	rcar_dram_get_boot_status(&ddrBackup);
+	rcar_dram_get_boot_status(&ddr_backup);
 #endif
 
-	/***********************************************************************
-	unlock phy
-	***********************************************************************/
+	/* unlock phy */
 	/* Unlock DDRPHY register(AGAIN) */
 	foreach_vch(ch)
 	    mmio_write_32(DBSC_DBPDLK(ch), 0x0000A55A);
 	dsb_sev();
 
-	if ((((Prr_Product == PRR_PRODUCT_H3) && (Prr_Cut > PRR_PRODUCT_11))
-	     || (Prr_Product == PRR_PRODUCT_M3N)
-	     || (Prr_Product == PRR_PRODUCT_V3H)) && (Boardcnf->dbi_en))
+	if ((((prr_product == PRR_PRODUCT_H3) &&
+	      (prr_cut > PRR_PRODUCT_11)) ||
+	     (prr_product == PRR_PRODUCT_M3N) ||
+	     (prr_product == PRR_PRODUCT_V3H)) && board_cnf->dbi_en)
 		reg_ddrphy_write_a(0x00001010, 0x01000001);
 	else
 		reg_ddrphy_write_a(0x00001010, 0x00000001);
-	/***********************************************************************
-	dbsc register pre-setting
-	***********************************************************************/
+	/* DBSC register pre-setting */
 	dbsc_regset_pre();
 
-	/***********************************************************************
-	load ddrphy registers
-	***********************************************************************/
+	/* load ddrphy registers */
 
 	ddrtbl_load();
 
-	/***********************************************************************
-	configure ddrphy registers
-	***********************************************************************/
+	/* configure ddrphy registers */
 	ddr_config();
 
-	/***********************************************************************
-	dfi_reset assert
-	***********************************************************************/
+	/* dfi_reset assert */
 	foreach_vch(ch)
 	    mmio_write_32(DBSC_DBPDCNT0(ch), 0x01);
 	dsb_sev();
 
-	/***********************************************************************
-	dbsc register set
-	***********************************************************************/
+	/* dbsc register set */
 	dbsc_regset();
-	MSG_LF("init_ddr:1\n");
+	MSG_LF(__func__ ":1\n");
 
-	/***********************************************************************
-	dfi_reset negate
-	***********************************************************************/
+	/* dfi_reset negate */
 	foreach_vch(ch)
 	    mmio_write_32(DBSC_DBPDCNT0(ch), 0x00);
 	dsb_sev();
 
-	/***********************************************************************
-	dfi_init_start (start ddrphy)
-	***********************************************************************/
+	/* dfi_init_start (start ddrphy) */
 	err = dfi_init_start();
 	if (err) {
 		return INITDRAM_ERR_I;
 	}
-	MSG_LF("init_ddr:2\n");
+	MSG_LF(__func__ ":2\n");
 
-	/***********************************************************************
-	ddr backupmode end
-	***********************************************************************/
+	/* ddr backupmode end */
 #ifdef DDR_BACKUPMODE
-	if (ddrBackup) {
+	if (ddr_backup) {
 		NOTICE("BL2: [WARM_BOOT]\n");
 	} else {
 		NOTICE("BL2: [COLD_BOOT]\n");
 	}
-	err = rcar_dram_update_boot_status(ddrBackup);
+	err = rcar_dram_update_boot_status(ddr_backup);
 	if (err) {
 		NOTICE("BL2: [BOOT_STATUS_UPDATE_ERROR]\n");
 		return INITDRAM_ERR_I;
 	}
 #endif
-	MSG_LF("init_ddr:3\n");
+	MSG_LF(__func__ ":3\n");
 
-	/***********************************************************************
-	override term code after dfi_init_complete
-	***********************************************************************/
+	/* override term code after dfi_init_complete */
 	err = set_term_code();
 	if (err) {
 		return INITDRAM_ERR_I;
 	}
-	MSG_LF("init_ddr:4\n");
+	MSG_LF(__func__ ":4\n");
 
-	/***********************************************************************
-	rx offset calibration
-	***********************************************************************/
-	if ((Prr_Cut > PRR_PRODUCT_11) || (Prr_Product == PRR_PRODUCT_M3N)
-	    || (Prr_Product == PRR_PRODUCT_V3H)) {
+	/* rx offset calibration */
+	if ((prr_cut > PRR_PRODUCT_11) || (prr_product == PRR_PRODUCT_M3N) ||
+	    (prr_product == PRR_PRODUCT_V3H)) {
 		err = rx_offset_cal_hw();
 	} else {
 		err = rx_offset_cal();
 	}
 	if (err)
-		return (INITDRAM_ERR_O);
-	MSG_LF("init_ddr:5\n");
+		return INITDRAM_ERR_O;
+	MSG_LF(__func__ ":5\n");
 
 	/* PDX */
 	send_dbcmd(0x08840001);
 
-	/***********************************************************************
-	check register i/f is alive
-	***********************************************************************/
+	/* check register i/f is alive */
 	err = ddrphy_regif_chk();
 	if (err) {
-		return (INITDRAM_ERR_O);
+		return INITDRAM_ERR_O;
 	}
-	MSG_LF("init_ddr:6\n");
+	MSG_LF(__func__ ":6\n");
 
-	/***********************************************************************
-	phy initialize end
-	***********************************************************************/
+	/* phy initialize end */
 
-	/***********************************************************************
-	setup DDR mode registers
-	***********************************************************************/
+	/* setup DDR mode registers */
 	/* CMOS MODE */
 	change_lpddr4_en(0);
 
 	/* MRS */
 	ddr_register_set();
 
-	/* ZQCAL start */
-	send_dbcmd(0x0d84004F);
-
-	/* ZQLAT */
-	send_dbcmd(0x0d840051);
-
-	/***********************************************************************
-	Thermal sensor setting
-	***********************************************************************/
+	/* Thermal sensor setting */
 	/* THCTR Bit6: PONM=0 , Bit0: THSST=1  */
-	dataL = (mmio_read_32(THS1_THCTR) & 0xFFFFFFBF) | 0x00000001;
-	mmio_write_32(THS1_THCTR, dataL);
+	data_l = (mmio_read_32(THS1_THCTR) & 0xFFFFFFBF) | 0x00000001;
+	mmio_write_32(THS1_THCTR, data_l);
 
 	/* LPDDR4 MODE */
 	change_lpddr4_en(1);
 
-	MSG_LF("init_ddr:7\n");
+	MSG_LF(__func__ ":7\n");
 
-	/***********************************************************************
-	mask CS_MAP if RANKx is not found
-	***********************************************************************/
+	/* mask CS_MAP if RANKx is not found */
 	foreach_vch(ch) {
-		dataL = ddr_getval(ch, _reg_PI_CS_MAP);
+		data_l = ddr_getval(ch, _reg_PI_CS_MAP);
 		if (!(ch_have_this_cs[1] & (1U << ch)))
-			dataL = dataL & 0x05;
-		ddr_setval(ch, _reg_PI_CS_MAP, dataL);
+			data_l = data_l & 0x05;
+		ddr_setval(ch, _reg_PI_CS_MAP, data_l);
 	}
 
-	/***********************************************************************
-	exec pi_training
-	***********************************************************************/
+	/* exec pi_training */
 	reg_ddrphy_write_a(ddr_regdef_adr(_reg_PHY_FREQ_SEL_MULTICAST_EN),
 			   BIT(ddr_regdef_lsb(_reg_PHY_FREQ_SEL_MULTICAST_EN)));
 	ddr_setval_ach_as(_reg_PHY_PER_CS_TRAINING_MULTICAST_EN, 0x00);
 
-	if ((Prr_Product == PRR_PRODUCT_H3) && (Prr_Cut <= PRR_PRODUCT_11)) {
-	ddr_setval_ach_as(_reg_PHY_PER_CS_TRAINING_EN, 0x01);
+	if ((prr_product == PRR_PRODUCT_H3) && (prr_cut <= PRR_PRODUCT_11)) {
+		ddr_setval_ach_as(_reg_PHY_PER_CS_TRAINING_EN, 0x01);
 	} else {
 		foreach_vch(ch) {
 			for (slice = 0; slice < SLICE_CNT; slice++) {
@@ -3171,101 +3084,88 @@ static uint32_t init_ddr(void)
 	phytrainingok = pi_training_go();
 
 	if (ddr_phyvalid != (phytrainingok & ddr_phyvalid)) {
-		return (INITDRAM_ERR_T | phytrainingok);
+		return INITDRAM_ERR_T | phytrainingok;
 	}
 
-	MSG_LF("init_ddr:8\n");
+	MSG_LF(__func__ ":8\n");
 
-	/***********************************************************************
-	CACS DLY ADJUST
-	***********************************************************************/
-	dataL = Boardcnf->cacs_dly + _f_scale_adj(Boardcnf->cacs_dly_adj);
+	/* CACS DLY ADJUST */
+	data_l = board_cnf->cacs_dly + _f_scale_adj(board_cnf->cacs_dly_adj);
 	foreach_vch(ch) {
 		for (i = 0; i < _reg_PHY_CLK_CACS_SLAVE_DELAY_X_NUM; i++) {
-			adj = _f_scale_adj(Boardcnf->ch[ch].cacs_adj[i]);
+			adj = _f_scale_adj(board_cnf->ch[ch].cacs_adj[i]);
 			ddr_setval(ch, _reg_PHY_CLK_CACS_SLAVE_DELAY_X[i],
-				   dataL + adj);
+				   data_l + adj);
 		}
 
 		if (ddr_phycaslice == 1) {
 			for (i = 0; i < 6; i++) {
-				adj = _f_scale_adj(Boardcnf->ch[ch].cacs_adj[i + _reg_PHY_CLK_CACS_SLAVE_DELAY_X_NUM]);
-				ddr_setval_s(ch, 2, _reg_PHY_CLK_CACS_SLAVE_DELAY_X[i],
-					     dataL + adj
+				adj = _f_scale_adj(board_cnf->ch[ch].cacs_adj
+					[i +
+					_reg_PHY_CLK_CACS_SLAVE_DELAY_X_NUM]);
+				ddr_setval_s(ch, 2,
+					     _reg_PHY_CLK_CACS_SLAVE_DELAY_X
+					     [i],
+					     data_l + adj
 				);
 			}
 		}
 	}
 
 	update_dly();
-	MSG_LF("init_ddr:9\n");
+	MSG_LF(__func__ ":9\n");
 
-	/***********************************************************************
-	H3 fix rd latency to avoid bug in elasitic buffe
-	***********************************************************************/
-	if ((Prr_Product == PRR_PRODUCT_H3) && (Prr_Cut <= PRR_PRODUCT_11)) {
+	/* H3 fix rd latency to avoid bug in elasitic buffer */
+	if ((prr_product == PRR_PRODUCT_H3) && (prr_cut <= PRR_PRODUCT_11))
 		adjust_rddqs_latency();
-	}
 
-	/***********************************************************************
-	Adjust Write path latency
-	***********************************************************************/
+	/* Adjust Write path latency */
 	if (ddrtbl_getval
 	    (_cnf_DDR_PHY_SLICE_REGSET, _reg_PHY_WRITE_PATH_LAT_ADD))
 		adjust_wpath_latency();
 
-	/***********************************************************************
-	RDQLVL Training
-	***********************************************************************/
-	if (ddrtbl_getval(_cnf_DDR_PHY_SLICE_REGSET, _reg_PHY_IE_MODE) == 0x00) {
+	/* RDQLVL Training */
+	if (!ddrtbl_getval(_cnf_DDR_PHY_SLICE_REGSET, _reg_PHY_IE_MODE))
 		ddr_setval_ach_as(_reg_PHY_IE_MODE, 0x01);
-	}
 
 	err = rdqdm_man();
 
-	if (ddrtbl_getval(_cnf_DDR_PHY_SLICE_REGSET, _reg_PHY_IE_MODE) == 0x00) {
+	if (!ddrtbl_getval(_cnf_DDR_PHY_SLICE_REGSET, _reg_PHY_IE_MODE))
 		ddr_setval_ach_as(_reg_PHY_IE_MODE, 0x00);
-	}
 
 	if (err) {
-		return (INITDRAM_ERR_T);
+		return INITDRAM_ERR_T;
 	}
 	update_dly();
-	MSG_LF("init_ddr:10\n");
+	MSG_LF(__func__ ":10\n");
 
-	/***********************************************************************
-	WDQLVL Training
-	***********************************************************************/
+	/* WDQLVL Training */
 	err = wdqdm_man();
 	if (err) {
-		return (INITDRAM_ERR_T);
+		return INITDRAM_ERR_T;
 	}
 	update_dly();
-	MSG_LF("init_ddr:11\n");
-
-	/***********************************************************************
-	training complete, setup dbsc
-	***********************************************************************/
-	if (((Prr_Product == PRR_PRODUCT_H3) && (Prr_Cut > PRR_PRODUCT_11))
-	    || (Prr_Product == PRR_PRODUCT_M3N)
-	    || (Prr_Product == PRR_PRODUCT_V3H)) {
+	MSG_LF(__func__ ":11\n");
+
+	/* training complete, setup DBSC */
+	if (((prr_product == PRR_PRODUCT_H3) && (prr_cut > PRR_PRODUCT_11)) ||
+	    (prr_product == PRR_PRODUCT_M3N) ||
+	    (prr_product == PRR_PRODUCT_V3H)) {
 		ddr_setval_ach_as(_reg_PHY_DFI40_POLARITY, 0x00);
 		ddr_setval_ach(_reg_PI_DFI40_POLARITY, 0x00);
 	}
 
 	dbsc_regset_post();
-	MSG_LF("init_ddr:12\n");
+	MSG_LF(__func__ ":12\n");
 
 	return phytrainingok;
 }
 
-/*******************************************************************************
- *	SW LEVELING COMMON
- ******************************************************************************/
+/* SW LEVELING COMMON */
 static uint32_t swlvl1(uint32_t ddr_csn, uint32_t reg_cs, uint32_t reg_kick)
 {
 	uint32_t ch;
-	uint32_t dataL;
+	uint32_t data_l;
 	uint32_t retry;
 	uint32_t waiting;
 	uint32_t err;
@@ -3294,8 +3194,8 @@ static uint32_t swlvl1(uint32_t ddr_csn, uint32_t reg_cs, uint32_t reg_kick)
 		foreach_vch(ch) {
 			if (!(waiting & (1U << ch)))
 				continue;
-			dataL = ddr_getval(ch, _reg_PI_SWLVL_OP_DONE);
-			if (dataL & 0x01)
+			data_l = ddr_getval(ch, _reg_PI_SWLVL_OP_DONE);
+			if (data_l & 0x01)
 				waiting &= ~(1U << ch);
 		}
 		retry--;
@@ -3312,23 +3212,19 @@ static uint32_t swlvl1(uint32_t ddr_csn, uint32_t reg_cs, uint32_t reg_kick)
 	return err;
 }
 
-/*******************************************************************************
- *	WDQ TRAINING
- ******************************************************************************/
+/* WDQ TRAINING */
 #ifndef DDR_FAST_INIT
 static void wdqdm_clr1(uint32_t ch, uint32_t ddr_csn)
 {
 	int32_t i, k;
 	uint32_t cs, slice;
-	uint32_t dataL;
+	uint32_t data_l;
 
-	/***********************************************************************
-	clr of training results buffer
-	***********************************************************************/
+	/* clr of training results buffer */
 	cs = ddr_csn % 2;
-	dataL = Boardcnf->dqdm_dly_w;
+	data_l = board_cnf->dqdm_dly_w;
 	for (slice = 0; slice < SLICE_CNT; slice++) {
-		k = (Boardcnf->ch[ch].dqs_swap >> (4 * slice)) & 0x0f;
+		k = (board_cnf->ch[ch].dqs_swap >> (4 * slice)) & 0x0f;
 		if (((k >= 2) && (ddr_csn < 2)) || ((k < 2) && (ddr_csn >= 2)))
 			continue;
 
@@ -3337,7 +3233,7 @@ static void wdqdm_clr1(uint32_t ch, uint32_t ddr_csn)
 				wdqdm_dly[ch][cs][slice][i] =
 				    wdqdm_dly[ch][CS_CNT - 1 - cs][slice][i];
 			else
-				wdqdm_dly[ch][cs][slice][i] = dataL;
+				wdqdm_dly[ch][cs][slice][i] = data_l;
 			wdqdm_le[ch][cs][slice][i] = 0;
 			wdqdm_te[ch][cs][slice][i] = 0;
 		}
@@ -3350,7 +3246,7 @@ static uint32_t wdqdm_ana1(uint32_t ch, uint32_t ddr_csn)
 {
 	int32_t i, k;
 	uint32_t cs, slice;
-	uint32_t dataL;
+	uint32_t data_l;
 	uint32_t err;
 	const uint32_t _par_WDQLVL_RETRY_THRES = 0x7c0;
 
@@ -3360,12 +3256,10 @@ static uint32_t wdqdm_ana1(uint32_t ch, uint32_t ddr_csn)
 	int16_t adj;
 	uint32_t dq;
 
-	/***********************************************************************
-	analysis of training results
-	***********************************************************************/
+	/* analysis of training results */
 	err = 0;
 	for (slice = 0; slice < SLICE_CNT; slice += 1) {
-		k = (Boardcnf->ch[ch].dqs_swap >> (4 * slice)) & 0x0f;
+		k = (board_cnf->ch[ch].dqs_swap >> (4 * slice)) & 0x0f;
 		if (((k >= 2) && (ddr_csn < 2)) || ((k < 2) && (ddr_csn >= 2)))
 			continue;
 
@@ -3374,45 +3268,47 @@ static uint32_t wdqdm_ana1(uint32_t ch, uint32_t ddr_csn)
 		for (i = 0; i < 9; i++) {
 			dq = slice * 8 + i;
 			if (i == 8)
-				_adj = Boardcnf->ch[ch].dm_adj_w[slice];
+				_adj = board_cnf->ch[ch].dm_adj_w[slice];
 			else
-				_adj = Boardcnf->ch[ch].dq_adj_w[dq];
+				_adj = board_cnf->ch[ch].dq_adj_w[dq];
 			adj = _f_scale_adj(_adj);
 
-			dataL =
+			data_l =
 			    ddr_getval_s(ch, slice,
 					 _reg_PHY_CLK_WRX_SLAVE_DELAY[i]) + adj;
 			ddr_setval_s(ch, slice, _reg_PHY_CLK_WRX_SLAVE_DELAY[i],
-				     dataL);
-			wdqdm_dly[ch][cs][slice][i] = dataL;
+				     data_l);
+			wdqdm_dly[ch][cs][slice][i] = data_l;
 		}
 		ddr_setval_s(ch, slice, _reg_PHY_PER_CS_TRAINING_EN, 0x00);
-		dataL = ddr_getval_s(ch, slice, _reg_PHY_WDQLVL_STATUS_OBS);
-		wdqdm_st[ch][cs][slice] = dataL;
+		data_l = ddr_getval_s(ch, slice, _reg_PHY_WDQLVL_STATUS_OBS);
+		wdqdm_st[ch][cs][slice] = data_l;
 		min_win = INT_LEAST32_MAX;
 		for (i = 0; i <= 8; i++) {
 			ddr_setval_s(ch, slice, _reg_PHY_WDQLVL_DQDM_OBS_SELECT,
 				     i);
 
-			dataL =
+			data_l =
 			    ddr_getval_s(ch, slice,
 					 _reg_PHY_WDQLVL_DQDM_TE_DLY_OBS);
-			wdqdm_te[ch][cs][slice][i] = dataL;
-			dataL =
+			wdqdm_te[ch][cs][slice][i] = data_l;
+			data_l =
 			    ddr_getval_s(ch, slice,
 					 _reg_PHY_WDQLVL_DQDM_LE_DLY_OBS);
-			wdqdm_le[ch][cs][slice][i] = dataL;
+			wdqdm_le[ch][cs][slice][i] = data_l;
 			win =
-			    (int32_t) wdqdm_te[ch][cs][slice][i] -
+			    (int32_t)wdqdm_te[ch][cs][slice][i] -
 			    wdqdm_le[ch][cs][slice][i];
 			if (min_win > win)
 				min_win = win;
-			if (dataL >= _par_WDQLVL_RETRY_THRES)
+			if (data_l >= _par_WDQLVL_RETRY_THRES)
 				err = 2;
 		}
 		wdqdm_win[ch][cs][slice] = min_win;
-		if ((Prr_Product == PRR_PRODUCT_H3) && (Prr_Cut <= PRR_PRODUCT_11)) {
-		ddr_setval_s(ch, slice, _reg_PHY_PER_CS_TRAINING_EN, 0x01);
+		if ((prr_product == PRR_PRODUCT_H3) &&
+		    (prr_cut <= PRR_PRODUCT_11)) {
+			ddr_setval_s(ch, slice, _reg_PHY_PER_CS_TRAINING_EN,
+				     0x01);
 		} else {
 			ddr_setval_s(ch, slice, _reg_PHY_PER_CS_TRAINING_EN,
 				     ((ch_have_this_cs[1]) >> ch) & 0x01);
@@ -3429,9 +3325,7 @@ static void wdqdm_cp(uint32_t ddr_csn, uint32_t restore)
 	uint32_t tgt_cs, src_cs;
 	uint32_t tmp_r;
 
-	/***********************************************************************
-	copy of training results
-	***********************************************************************/
+	/* copy of training results */
 	foreach_vch(ch) {
 		for (tgt_cs = 0; tgt_cs < CS_CNT; tgt_cs++) {
 			for (slice = 0; slice < SLICE_CNT; slice++) {
@@ -3465,7 +3359,7 @@ static uint32_t wdqdm_man1(void)
 	int32_t k;
 	uint32_t ch, cs, slice;
 	uint32_t ddr_csn;
-	uint32_t dataL;
+	uint32_t data_l;
 	uint32_t err;
 	uint32_t high_dq[DRAM_CH_CNT];
 	uint32_t mr14_csab0_bak[DRAM_CH_CNT];
@@ -3473,14 +3367,13 @@ static uint32_t wdqdm_man1(void)
 	uint32_t err_flg;
 #endif/* DDR_FAST_INIT */
 
-	/***********************************************************************
-	manual execution of training
-	***********************************************************************/
-	if ((Prr_Product == PRR_PRODUCT_H3) && (Prr_Cut <= PRR_PRODUCT_11)) {
+	/* manual execution of training */
+	if ((prr_product == PRR_PRODUCT_H3) && (prr_cut <= PRR_PRODUCT_11)) {
 		foreach_vch(ch) {
 			high_dq[ch] = 0;
 			for (slice = 0; slice < SLICE_CNT; slice++) {
-				k = (Boardcnf->ch[ch].dqs_swap >> (4 * slice)) & 0x0f;
+				k = (board_cnf->ch[ch].dqs_swap >>
+				    (4 * slice)) & 0x0f;
 				if (k >= 2)
 					high_dq[ch] |= (1U << slice);
 			}
@@ -3491,10 +3384,10 @@ static uint32_t wdqdm_man1(void)
 	/* CLEAR PREV RESULT */
 	for (cs = 0; cs < CS_CNT; cs++) {
 		ddr_setval_ach_as(_reg_PHY_PER_CS_TRAINING_INDEX, cs);
-		if (((Prr_Product == PRR_PRODUCT_H3)
-		     && (Prr_Cut > PRR_PRODUCT_11))
-		    || (Prr_Product == PRR_PRODUCT_M3N)
-		    || (Prr_Product == PRR_PRODUCT_V3H)) {
+		if (((prr_product == PRR_PRODUCT_H3) &&
+		     (prr_cut > PRR_PRODUCT_11)) ||
+		    (prr_product == PRR_PRODUCT_M3N) ||
+		    (prr_product == PRR_PRODUCT_V3H)) {
 			ddr_setval_ach_as(_reg_SC_PHY_WDQLVL_CLR_PREV_RESULTS,
 					  0x01);
 		} else {
@@ -3508,33 +3401,33 @@ static uint32_t wdqdm_man1(void)
 	err_flg = 0;
 #endif/* DDR_FAST_INIT */
 	for (ddr_csn = 0; ddr_csn < CSAB_CNT; ddr_csn++) {
-		if ((Prr_Product == PRR_PRODUCT_H3)
-		    && (Prr_Cut <= PRR_PRODUCT_11)) {
+		if ((prr_product == PRR_PRODUCT_H3) &&
+		    (prr_cut <= PRR_PRODUCT_11)) {
 			foreach_vch(ch) {
-				dataL = mmio_read_32(DBSC_DBDFICNT(ch));
-				dataL &= ~(0x00ffU << 16);
+				data_l = mmio_read_32(DBSC_DBDFICNT(ch));
+				data_l &= ~(0x00ffU << 16);
 
 				if (ddr_csn >= 2)
 					k = (high_dq[ch] ^ 0x0f);
 				else
 					k = high_dq[ch];
-				dataL |= (k << 16);
-				mmio_write_32(DBSC_DBDFICNT(ch), dataL);
+				data_l |= (k << 16);
+				mmio_write_32(DBSC_DBDFICNT(ch), data_l);
 				ddr_setval(ch, _reg_PI_WDQLVL_RESP_MASK, k);
 			}
 		}
-		if (((Prr_Product == PRR_PRODUCT_H3)
-		     && (Prr_Cut <= PRR_PRODUCT_11))
-		    || ((Prr_Product == PRR_PRODUCT_M3)
-			&& (Prr_Cut == PRR_PRODUCT_10))) {
+		if (((prr_product == PRR_PRODUCT_H3) &&
+		     (prr_cut <= PRR_PRODUCT_11)) ||
+		    ((prr_product == PRR_PRODUCT_M3) &&
+		     (prr_cut == PRR_PRODUCT_10))) {
 			wdqdm_cp(ddr_csn, 0);
 		}
 
 		foreach_vch(ch) {
-			dataL =
+			data_l =
 			    ddr_getval(ch,
-				       _reg_PI_MR14_DATA_Fx_CSx[1][ddr_csn]);
-			ddr_setval(ch, _reg_PI_MR14_DATA_Fx_CSx[1][0], dataL);
+				       reg_pi_mr14_data_fx_csx[1][ddr_csn]);
+			ddr_setval(ch, reg_pi_mr14_data_fx_csx[1][0], data_l);
 		}
 
 		/* KICK WDQLVL */
@@ -3545,10 +3438,10 @@ static uint32_t wdqdm_man1(void)
 		if (ddr_csn == 0)
 			foreach_vch(ch) {
 			mr14_csab0_bak[ch] =
-			    ddr_getval(ch, _reg_PI_MR14_DATA_Fx_CSx[1][0]);
+			    ddr_getval(ch, reg_pi_mr14_data_fx_csx[1][0]);
 		} else
 			foreach_vch(ch) {
-			ddr_setval(ch, _reg_PI_MR14_DATA_Fx_CSx[1][0],
+			ddr_setval(ch, reg_pi_mr14_data_fx_csx[1][0],
 				   mr14_csab0_bak[ch]);
 			}
 #ifndef DDR_FAST_INIT
@@ -3568,16 +3461,16 @@ err_exit:
 #ifndef DDR_FAST_INIT
 	err |= err_flg;
 #endif/* DDR_FAST_INIT */
-	if ((Prr_Product == PRR_PRODUCT_H3) && (Prr_Cut <= PRR_PRODUCT_11)) {
+	if ((prr_product == PRR_PRODUCT_H3) && (prr_cut <= PRR_PRODUCT_11)) {
 		ddr_setval_ach(_reg_PI_16BIT_DRAM_CONNECT, 0x01);
 		foreach_vch(ch) {
-			dataL = mmio_read_32(DBSC_DBDFICNT(ch));
-			dataL &= ~(0x00ffU << 16);
-			mmio_write_32(DBSC_DBDFICNT(ch), dataL);
+			data_l = mmio_read_32(DBSC_DBDFICNT(ch));
+			data_l &= ~(0x00ffU << 16);
+			mmio_write_32(DBSC_DBDFICNT(ch), data_l);
 			ddr_setval(ch, _reg_PI_WDQLVL_RESP_MASK, 0x00);
 		}
 	}
-	return (err);
+	return err;
 }
 
 static uint32_t wdqdm_man(void)
@@ -3586,30 +3479,34 @@ static uint32_t wdqdm_man(void)
 	const uint32_t retry_max = 0x10;
 	uint32_t ch, ddr_csn, mr14_bkup[4][4];
 
-	ddr_setval_ach(_reg_PI_TDFI_WDQLVL_RW, (DBSC_DBTR(11) & 0xFF) + 12);
-	if (((Prr_Product == PRR_PRODUCT_H3) && (Prr_Cut > PRR_PRODUCT_11))
-	    || (Prr_Product == PRR_PRODUCT_M3N)
-	    || (Prr_Product == PRR_PRODUCT_V3H)) {
+	ddr_setval_ach(_reg_PI_TDFI_WDQLVL_RW,
+		       (mmio_read_32(DBSC_DBTR(11)) & 0xFF) + 19);
+	if (((prr_product == PRR_PRODUCT_H3) && (prr_cut > PRR_PRODUCT_11)) ||
+	    (prr_product == PRR_PRODUCT_M3N) ||
+	    (prr_product == PRR_PRODUCT_V3H)) {
+		ddr_setval_ach(_reg_PI_TDFI_WDQLVL_WR_F0,
+			       (mmio_read_32(DBSC_DBTR(12)) & 0xFF) + 10);
 		ddr_setval_ach(_reg_PI_TDFI_WDQLVL_WR_F1,
-			       (DBSC_DBTR(12) & 0xFF) + 1);
+			       (mmio_read_32(DBSC_DBTR(12)) & 0xFF) + 10);
 	} else {
 		ddr_setval_ach(_reg_PI_TDFI_WDQLVL_WR,
-			       (DBSC_DBTR(12) & 0xFF) + 1);
+			       (mmio_read_32(DBSC_DBTR(12)) & 0xFF) + 10);
 	}
-	ddr_setval_ach(_reg_PI_TRFC_F1, (DBSC_DBTR(13) & 0x1FF));
+	ddr_setval_ach(_reg_PI_TRFC_F0, mmio_read_32(DBSC_DBTR(13)) & 0x1FF);
+	ddr_setval_ach(_reg_PI_TRFC_F1, mmio_read_32(DBSC_DBTR(13)) & 0x1FF);
 
 	retry_cnt = 0;
 	err = 0;
 	do {
-		if ((Prr_Product == PRR_PRODUCT_H3)
-		    && (Prr_Cut <= PRR_PRODUCT_11)) {
+		if ((prr_product == PRR_PRODUCT_H3) &&
+		    (prr_cut <= PRR_PRODUCT_11)) {
 			err = wdqdm_man1();
 		} else {
 			ddr_setval_ach(_reg_PI_WDQLVL_VREF_EN, 0x01);
 			ddr_setval_ach(_reg_PI_WDQLVL_VREF_NORMAL_STEPSIZE,
 				       0x01);
-			if ((Prr_Product == PRR_PRODUCT_M3N)
-			    || (Prr_Product == PRR_PRODUCT_V3H)) {
+			if ((prr_product == PRR_PRODUCT_M3N) ||
+			    (prr_product == PRR_PRODUCT_V3H)) {
 				ddr_setval_ach(_reg_PI_WDQLVL_VREF_DELTA_F1,
 					       0x0C);
 			} else {
@@ -3621,14 +3518,14 @@ static uint32_t wdqdm_man(void)
 				for (ddr_csn = 0; ddr_csn < CSAB_CNT; ddr_csn++) {
 					mr14_bkup[ch][ddr_csn] =
 					    ddr_getval(ch,
-						       _reg_PI_MR14_DATA_Fx_CSx
+						       reg_pi_mr14_data_fx_csx
 						       [1][ddr_csn]);
 					dsb_sev();
 				}
 			}
 
-			if ((Prr_Product == PRR_PRODUCT_M3N)
-			    || (Prr_Product == PRR_PRODUCT_V3H)) {
+			if ((prr_product == PRR_PRODUCT_M3N) ||
+			    (prr_product == PRR_PRODUCT_V3H)) {
 				ddr_setval_ach(_reg_PI_WDQLVL_VREF_DELTA_F1,
 					       0x04);
 			} else {
@@ -3641,10 +3538,10 @@ static uint32_t wdqdm_man(void)
 					mr14_bkup[ch][ddr_csn] =
 					    (mr14_bkup[ch][ddr_csn] +
 					     ddr_getval(ch,
-							_reg_PI_MR14_DATA_Fx_CSx
+							reg_pi_mr14_data_fx_csx
 							[1][ddr_csn])) / 2;
 					ddr_setval(ch,
-						   _reg_PI_MR14_DATA_Fx_CSx[1]
+						   reg_pi_mr14_data_fx_csx[1]
 						   [ddr_csn],
 						   mr14_bkup[ch][ddr_csn]);
 				}
@@ -3652,8 +3549,8 @@ static uint32_t wdqdm_man(void)
 
 			ddr_setval_ach(_reg_PI_WDQLVL_VREF_NORMAL_STEPSIZE,
 				       0x00);
-			if ((Prr_Product == PRR_PRODUCT_M3N)
-			    || (Prr_Product == PRR_PRODUCT_V3H)) {
+			if ((prr_product == PRR_PRODUCT_M3N) ||
+			    (prr_product == PRR_PRODUCT_V3H)) {
 				ddr_setval_ach(_reg_PI_WDQLVL_VREF_DELTA_F1,
 					       0x00);
 				ddr_setval_ach
@@ -3680,31 +3577,27 @@ static uint32_t wdqdm_man(void)
 		}
 	} while (err && (++retry_cnt < retry_max));
 
-	if (((Prr_Product == PRR_PRODUCT_H3) && (Prr_Cut <= PRR_PRODUCT_11))
-	    || ((Prr_Product == PRR_PRODUCT_M3) && (Prr_Cut <= PRR_PRODUCT_10))) {
+	if (((prr_product == PRR_PRODUCT_H3) && (prr_cut <= PRR_PRODUCT_11)) ||
+	    ((prr_product == PRR_PRODUCT_M3) && (prr_cut <= PRR_PRODUCT_10))) {
 		wdqdm_cp(0, 1);
 	}
 
 	return (retry_cnt >= retry_max);
 }
 
-/*******************************************************************************
- *	RDQ TRAINING
- ******************************************************************************/
+/* RDQ TRAINING */
 #ifndef DDR_FAST_INIT
 static void rdqdm_clr1(uint32_t ch, uint32_t ddr_csn)
 {
 	int32_t i, k;
 	uint32_t cs, slice;
-	uint32_t dataL;
+	uint32_t data_l;
 
-	/***********************************************************************
-	clr of training results buffer
-	***********************************************************************/
+	/* clr of training results buffer */
 	cs = ddr_csn % 2;
-	dataL = Boardcnf->dqdm_dly_r;
+	data_l = board_cnf->dqdm_dly_r;
 	for (slice = 0; slice < SLICE_CNT; slice++) {
-		k = (Boardcnf->ch[ch].dqs_swap >> (4 * slice)) & 0x0f;
+		k = (board_cnf->ch[ch].dqs_swap >> (4 * slice)) & 0x0f;
 		if (((k >= 2) && (ddr_csn < 2)) || ((k < 2) && (ddr_csn >= 2)))
 			continue;
 
@@ -3717,8 +3610,9 @@ static void rdqdm_clr1(uint32_t ch, uint32_t ddr_csn)
 								   SLICE_CNT]
 				    [i];
 			} else {
-				rdqdm_dly[ch][cs][slice][i] = dataL;
-				rdqdm_dly[ch][cs][slice + SLICE_CNT][i] = dataL;
+				rdqdm_dly[ch][cs][slice][i] = data_l;
+				rdqdm_dly[ch][cs][slice + SLICE_CNT][i] =
+					data_l;
 			}
 			rdqdm_le[ch][cs][slice][i] = 0;
 			rdqdm_le[ch][cs][slice + SLICE_CNT][i] = 0;
@@ -3736,7 +3630,7 @@ static uint32_t rdqdm_ana1(uint32_t ch, uint32_t ddr_csn)
 {
 	int32_t i, k;
 	uint32_t cs, slice;
-	uint32_t dataL;
+	uint32_t data_l;
 	uint32_t err;
 	int8_t _adj;
 	int16_t adj;
@@ -3745,12 +3639,10 @@ static uint32_t rdqdm_ana1(uint32_t ch, uint32_t ddr_csn)
 	int32_t win;
 	uint32_t rdq_status_obs_select;
 
-	/***********************************************************************
-	analysis of training results
-	***********************************************************************/
+	/* analysis of training results */
 	err = 0;
 	for (slice = 0; slice < SLICE_CNT; slice++) {
-		k = (Boardcnf->ch[ch].dqs_swap >> (4 * slice)) & 0x0f;
+		k = (board_cnf->ch[ch].dqs_swap >> (4 * slice)) & 0x0f;
 		if (((k >= 2) && (ddr_csn < 2)) || ((k < 2) && (ddr_csn >= 2)))
 			continue;
 
@@ -3764,36 +3656,36 @@ static uint32_t rdqdm_ana1(uint32_t ch, uint32_t ddr_csn)
 		for (i = 0; i <= 8; i++) {
 			dq = slice * 8 + i;
 			if (i == 8)
-				_adj = Boardcnf->ch[ch].dm_adj_r[slice];
+				_adj = board_cnf->ch[ch].dm_adj_r[slice];
 			else
-				_adj = Boardcnf->ch[ch].dq_adj_r[dq];
+				_adj = board_cnf->ch[ch].dq_adj_r[dq];
 
 			adj = _f_scale_adj(_adj);
 
-			dataL =
+			data_l =
 			    ddr_getval_s(ch, slice,
 					 _reg_PHY_RDDQS_X_RISE_SLAVE_DELAY[i]) +
 			    adj;
 			ddr_setval_s(ch, slice,
 				     _reg_PHY_RDDQS_X_RISE_SLAVE_DELAY[i],
-				     dataL);
-			rdqdm_dly[ch][cs][slice][i] = dataL;
+				     data_l);
+			rdqdm_dly[ch][cs][slice][i] = data_l;
 
-			dataL =
+			data_l =
 			    ddr_getval_s(ch, slice,
 					 _reg_PHY_RDDQS_X_FALL_SLAVE_DELAY[i]) +
 			    adj;
 			ddr_setval_s(ch, slice,
 				     _reg_PHY_RDDQS_X_FALL_SLAVE_DELAY[i],
-				     dataL);
-			rdqdm_dly[ch][cs][slice + SLICE_CNT][i] = dataL;
+				     data_l);
+			rdqdm_dly[ch][cs][slice + SLICE_CNT][i] = data_l;
 		}
 		min_win = INT_LEAST32_MAX;
 		for (i = 0; i <= 8; i++) {
-			dataL =
+			data_l =
 			    ddr_getval_s(ch, slice, _reg_PHY_RDLVL_STATUS_OBS);
-			rdqdm_st[ch][cs][slice] = dataL;
-			rdqdm_st[ch][cs][slice + SLICE_CNT] = dataL;
+			rdqdm_st[ch][cs][slice] = data_l;
+			rdqdm_st[ch][cs][slice + SLICE_CNT] = data_l;
 			/* k : rise/fall */
 			for (k = 0; k < 2; k++) {
 				if (i == 8) {
@@ -3805,28 +3697,28 @@ static uint32_t rdqdm_ana1(uint32_t ch, uint32_t ddr_csn)
 					     _reg_PHY_RDLVL_RDDQS_DQ_OBS_SELECT,
 					     rdq_status_obs_select);
 
-				dataL =
+				data_l =
 				    ddr_getval_s(ch, slice,
 						 _reg_PHY_RDLVL_RDDQS_DQ_LE_DLY_OBS);
 				rdqdm_le[ch][cs][slice + SLICE_CNT * k][i] =
-				    dataL;
+				    data_l;
 
-				dataL =
+				data_l =
 				    ddr_getval_s(ch, slice,
 						 _reg_PHY_RDLVL_RDDQS_DQ_TE_DLY_OBS);
 				rdqdm_te[ch][cs][slice + SLICE_CNT * k][i] =
-				    dataL;
+				    data_l;
 
-				dataL =
+				data_l =
 				    ddr_getval_s(ch, slice,
 						 _reg_PHY_RDLVL_RDDQS_DQ_NUM_WINDOWS_OBS);
 				rdqdm_nw[ch][cs][slice + SLICE_CNT * k][i] =
-				    dataL;
+				    data_l;
 
 				win =
-				    (int32_t) rdqdm_te[ch][cs][slice +
-							       SLICE_CNT *
-							       k][i] -
+				    (int32_t)rdqdm_te[ch][cs][slice +
+							      SLICE_CNT *
+							      k][i] -
 				    rdqdm_le[ch][cs][slice + SLICE_CNT * k][i];
 				if (i != 8) {
 					if (min_win > win)
@@ -3839,7 +3731,7 @@ static uint32_t rdqdm_ana1(uint32_t ch, uint32_t ddr_csn)
 			err = 2;
 		}
 	}
-	return (err);
+	return err;
 }
 #endif/* DDR_FAST_INIT */
 
@@ -3849,13 +3741,11 @@ static uint32_t rdqdm_man1(void)
 	uint32_t ddr_csn;
 #ifdef DDR_FAST_INIT
 	uint32_t slice;
-	uint32_t i, adj, dataL;
+	uint32_t i, adj, data_l;
 #endif/* DDR_FAST_INIT */
 	uint32_t err;
 
-	/***********************************************************************
-	manual execution of training
-	***********************************************************************/
+	/* manual execution of training */
 	err = 0;
 
 	for (ddr_csn = 0; ddr_csn < CSAB_CNT; ddr_csn++) {
@@ -3880,7 +3770,7 @@ static uint32_t rdqdm_man1(void)
 			if (ch_have_this_cs[ddr_csn] & (1U << ch)) {
 				for (slice = 0; slice < SLICE_CNT; slice++) {
 					if (ddr_getval_s(ch, slice,
-					    _reg_PHY_RDLVL_STATUS_OBS) !=
+							 _reg_PHY_RDLVL_STATUS_OBS) !=
 					    0x0D00FFFF) {
 						err = (1U << ch) |
 							(0x10U << slice);
@@ -3888,26 +3778,26 @@ static uint32_t rdqdm_man1(void)
 					}
 				}
 			}
-			if (((Prr_Product == PRR_PRODUCT_H3)
-			    && (Prr_Cut <= PRR_PRODUCT_11))
-			    || ((Prr_Product == PRR_PRODUCT_M3)
-			    && (Prr_Cut <= PRR_PRODUCT_10))) {
+			if (((prr_product == PRR_PRODUCT_H3) &&
+			     (prr_cut <= PRR_PRODUCT_11)) ||
+			    ((prr_product == PRR_PRODUCT_M3) &&
+			     (prr_cut <= PRR_PRODUCT_10))) {
 				for (slice = 0; slice < SLICE_CNT; slice++) {
 					for (i = 0; i <= 8; i++) {
 						if (i == 8)
-							adj = _f_scale_adj(Boardcnf->ch[ch].dm_adj_r[slice]);
+							adj = _f_scale_adj(board_cnf->ch[ch].dm_adj_r[slice]);
 						else
-							adj = _f_scale_adj(Boardcnf->ch[ch].dq_adj_r[slice * 8 + i]);
+							adj = _f_scale_adj(board_cnf->ch[ch].dq_adj_r[slice * 8 + i]);
 						ddr_setval_s(ch, slice, _reg_PHY_PER_CS_TRAINING_INDEX, ddr_csn);
-						dataL = ddr_getval_s(ch, slice, _reg_PHY_RDDQS_X_RISE_SLAVE_DELAY[i]) + adj;
-						ddr_setval_s(ch, slice, _reg_PHY_RDDQS_X_RISE_SLAVE_DELAY[i], dataL);
-						rdqdm_dly[ch][ddr_csn][slice][i] = dataL;
-						rdqdm_dly[ch][ddr_csn | 1][slice][i] = dataL;
-
-						dataL = ddr_getval_s(ch, slice, _reg_PHY_RDDQS_X_FALL_SLAVE_DELAY[i]) + adj;
-						ddr_setval_s(ch, slice, _reg_PHY_RDDQS_X_FALL_SLAVE_DELAY[i], dataL);
-						rdqdm_dly[ch][ddr_csn][slice + SLICE_CNT][i] = dataL;
-						rdqdm_dly[ch][ddr_csn | 1][slice + SLICE_CNT][i] = dataL;
+						data_l = ddr_getval_s(ch, slice, _reg_PHY_RDDQS_X_RISE_SLAVE_DELAY[i]) + adj;
+						ddr_setval_s(ch, slice, _reg_PHY_RDDQS_X_RISE_SLAVE_DELAY[i], data_l);
+						rdqdm_dly[ch][ddr_csn][slice][i] = data_l;
+						rdqdm_dly[ch][ddr_csn | 1][slice][i] = data_l;
+
+						data_l = ddr_getval_s(ch, slice, _reg_PHY_RDDQS_X_FALL_SLAVE_DELAY[i]) + adj;
+						ddr_setval_s(ch, slice, _reg_PHY_RDDQS_X_FALL_SLAVE_DELAY[i], data_l);
+						rdqdm_dly[ch][ddr_csn][slice + SLICE_CNT][i] = data_l;
+						rdqdm_dly[ch][ddr_csn | 1][slice + SLICE_CNT][i] = data_l;
 					}
 				}
 			}
@@ -3918,7 +3808,7 @@ static uint32_t rdqdm_man1(void)
 	}
 
 err_exit:
-	return (err);
+	return err;
 }
 
 static uint32_t rdqdm_man(void)
@@ -3960,9 +3850,7 @@ static uint32_t rdqdm_man(void)
 	return (retry_cnt >= retry_max);
 }
 
-/*******************************************************************************
- *	rx offset calibration
- ******************************************************************************/
+/* rx offset calibration */
 static int32_t _find_change(uint64_t val, uint32_t dir)
 {
 	int32_t i;
@@ -3975,18 +3863,18 @@ static int32_t _find_change(uint64_t val, uint32_t dir)
 		for (i = 1; i <= VAL_END; i++) {
 			curval = (val >> i) & 0x01;
 			if (curval != startval)
-				return (i);
-		}
-		return (VAL_END);
-	} else {
-		startval = (val >> dir) & 0x01;
-		for (i = dir - 1; i >= 0; i--) {
-			curval = (val >> i) & 0x01;
-			if (curval != startval)
-				return (i);
+				return i;
 		}
-		return (0);
+		return VAL_END;
 	}
+
+	startval = (val >> dir) & 0x01;
+	for (i = dir - 1; i >= 0; i--) {
+		curval = (val >> i) & 0x01;
+		if (curval != startval)
+			return i;
+	}
+	return 0;
 }
 
 static uint32_t _rx_offset_cal_updn(uint32_t code)
@@ -3994,7 +3882,7 @@ static uint32_t _rx_offset_cal_updn(uint32_t code)
 	const uint32_t CODE_MAX = 0x40;
 	uint32_t tmp;
 
-	if ((Prr_Product == PRR_PRODUCT_H3) && (Prr_Cut <= PRR_PRODUCT_11)) {
+	if ((prr_product == PRR_PRODUCT_H3) && (prr_cut <= PRR_PRODUCT_11)) {
 		if (code == 0)
 			tmp = (1U << 6) | (CODE_MAX - 1);
 		else if (code <= 0x20)
@@ -4030,9 +3918,8 @@ static uint32_t rx_offset_cal(void)
 	ddr_setval_ach_as(_reg_PHY_RX_CAL_OVERRIDE, 0x01);
 	foreach_vch(ch) {
 		for (slice = 0; slice < SLICE_CNT; slice++) {
-			for (index = 0; index < _reg_PHY_RX_CAL_X_NUM; index++) {
+			for (index = 0; index < _reg_PHY_RX_CAL_X_NUM; index++)
 				val[ch][slice][index] = 0;
-			}
 		}
 	}
 
@@ -4042,7 +3929,7 @@ static uint32_t rx_offset_cal(void)
 			ddr_setval_ach_as(_reg_PHY_RX_CAL_X[index], tmp);
 		}
 		dsb_sev();
-		ddr_getval_ach_as(_reg_PHY_RX_CAL_OBS, (uint32_t *) tmp_ach_as);
+		ddr_getval_ach_as(_reg_PHY_RX_CAL_OBS, (uint32_t *)tmp_ach_as);
 
 		foreach_vch(ch) {
 			for (slice = 0; slice < SLICE_CNT; slice++) {
@@ -4062,7 +3949,8 @@ static uint32_t rx_offset_cal(void)
 	}
 	foreach_vch(ch) {
 		for (slice = 0; slice < SLICE_CNT; slice++) {
-			for (index = 0; index < _reg_PHY_RX_CAL_X_NUM; index++) {
+			for (index = 0; index < _reg_PHY_RX_CAL_X_NUM;
+			     index++) {
 				tmpval = val[ch][slice][index];
 				lsb = _find_change(tmpval, 0);
 				msb =
@@ -4099,7 +3987,7 @@ static uint32_t rx_offset_cal_hw(void)
 			ddr_setval_ach_as(_reg_SC_PHY_RX_CAL_START, 0x01);
 		}
 		foreach_vch(ch)
-		    for (slice = 0; slice < SLICE_CNT; slice++)
+		for (slice = 0; slice < SLICE_CNT; slice++)
 			tmp_ach_as[ch][slice] =
 			    ddr_getval_s(ch, slice, _reg_PHY_RX_CAL_X[9]);
 
@@ -4108,10 +3996,10 @@ static uint32_t rx_offset_cal_hw(void)
 			for (slice = 0; slice < SLICE_CNT; slice++) {
 				tmp = tmp_ach_as[ch][slice];
 				tmp = (tmp & 0x3f) + ((tmp >> 6) & 0x3f);
-				if (((Prr_Product == PRR_PRODUCT_H3)
-				     && (Prr_Cut > PRR_PRODUCT_11))
-				    || (Prr_Product == PRR_PRODUCT_M3N)
-				    || (Prr_Product == PRR_PRODUCT_V3H)) {
+				if (((prr_product == PRR_PRODUCT_H3) &&
+				     (prr_cut > PRR_PRODUCT_11)) ||
+				    (prr_product == PRR_PRODUCT_M3N) ||
+				    (prr_product == PRR_PRODUCT_V3H)) {
 					if (tmp != 0x3E)
 						complete = 0;
 				} else {
@@ -4129,9 +4017,7 @@ static uint32_t rx_offset_cal_hw(void)
 	return (complete == 0);
 }
 
-/*******************************************************************************
- *	adjust rddqs latency
- ******************************************************************************/
+/* adjust rddqs latency */
 static void adjust_rddqs_latency(void)
 {
 	uint32_t ch, slice;
@@ -4139,6 +4025,7 @@ static void adjust_rddqs_latency(void)
 	uint32_t maxlatx2;
 	uint32_t tmp;
 	uint32_t rdlat_adjx2[SLICE_CNT];
+
 	foreach_vch(ch) {
 		maxlatx2 = 0;
 		for (slice = 0; slice < SLICE_CNT; slice++) {
@@ -4171,9 +4058,7 @@ static void adjust_rddqs_latency(void)
 	}
 }
 
-/*******************************************************************************
- *	adjust wpath latency
- ******************************************************************************/
+/* adjust wpath latency */
 static void adjust_wpath_latency(void)
 {
 	uint32_t ch, cs, slice;
@@ -4206,94 +4091,90 @@ static void adjust_wpath_latency(void)
 	}
 }
 
-/*******************************************************************************
- *	DDR Initialize entry
- ******************************************************************************/
+/* DDR Initialize entry */
 int32_t rcar_dram_init(void)
 {
 	uint32_t ch, cs;
-	uint32_t dataL;
+	uint32_t data_l;
 	uint32_t bus_mbps, bus_mbpsdiv;
 	uint32_t tmp_tccd;
 	uint32_t failcount;
+	uint32_t cnf_boardtype;
 
-	/***********************************************************************
-	Thermal sensor setting
-	***********************************************************************/
-	dataL = mmio_read_32(CPG_MSTPSR5);
-	if (dataL & BIT(22)) {	/*  case THS/TSC Standby */
-		dataL &= ~(BIT(22));
-		cpg_write_32(CPG_SMSTPCR5, dataL);
-		while ((BIT(22)) & mmio_read_32(CPG_MSTPSR5));  /*  wait bit=0 */
+	/* Thermal sensor setting */
+	data_l = mmio_read_32(CPG_MSTPSR5);
+	if (data_l & BIT(22)) {	/*  case THS/TSC Standby */
+		data_l &= ~BIT(22);
+		cpg_write_32(CPG_SMSTPCR5, data_l);
+		while (mmio_read_32(CPG_MSTPSR5) & BIT(22))
+			;  /*  wait bit=0 */
 	}
 
 	/* THCTR Bit6: PONM=0 , Bit0: THSST=0   */
-	dataL = mmio_read_32(THS1_THCTR) & 0xFFFFFFBE;
-	mmio_write_32(THS1_THCTR, dataL);
+	data_l = mmio_read_32(THS1_THCTR) & 0xFFFFFFBE;
+	mmio_write_32(THS1_THCTR, data_l);
 
-	/***********************************************************************
-	Judge product and cut
-	***********************************************************************/
+	/* Judge product and cut */
 #ifdef RCAR_DDR_FIXED_LSI_TYPE
-#if(RCAR_LSI==RCAR_AUTO)
-	Prr_Product = mmio_read_32(PRR) & PRR_PRODUCT_MASK;
-	Prr_Cut = mmio_read_32(PRR) & PRR_CUT_MASK;
+#if (RCAR_LSI == RCAR_AUTO)
+	prr_product = mmio_read_32(PRR) & PRR_PRODUCT_MASK;
+	prr_cut = mmio_read_32(PRR) & PRR_CUT_MASK;
 #else /* RCAR_LSI */
 #ifndef RCAR_LSI_CUT
-	Prr_Cut = mmio_read_32(PRR) & PRR_CUT_MASK;
+	prr_cut = mmio_read_32(PRR) & PRR_CUT_MASK;
 #endif /* RCAR_LSI_CUT */
 #endif /* RCAR_LSI */
 #else /* RCAR_DDR_FIXED_LSI_TYPE */
-	Prr_Product = mmio_read_32(PRR) & PRR_PRODUCT_MASK;
-	Prr_Cut = mmio_read_32(PRR) & PRR_CUT_MASK;
+	prr_product = mmio_read_32(PRR) & PRR_PRODUCT_MASK;
+	prr_cut = mmio_read_32(PRR) & PRR_CUT_MASK;
 #endif /* RCAR_DDR_FIXED_LSI_TYPE */
 
-	if (Prr_Product == PRR_PRODUCT_H3) {
-		if (Prr_Cut <= PRR_PRODUCT_11) {
-			pDDR_REGDEF_TBL = (const uint32_t *)&DDR_REGDEF_TBL[0][0];
+	if (prr_product == PRR_PRODUCT_H3) {
+		if (prr_cut <= PRR_PRODUCT_11) {
+			p_ddr_regdef_tbl =
+				(const uint32_t *)&DDR_REGDEF_TBL[0][0];
 		} else {
-			pDDR_REGDEF_TBL = (const uint32_t *)&DDR_REGDEF_TBL[2][0];
+			p_ddr_regdef_tbl =
+				(const uint32_t *)&DDR_REGDEF_TBL[2][0];
 		}
-	} else if (Prr_Product == PRR_PRODUCT_M3) {
-		pDDR_REGDEF_TBL = (const uint32_t *)&DDR_REGDEF_TBL[1][0];
-	} else if ((Prr_Product == PRR_PRODUCT_M3N)
-		   || (Prr_Product == PRR_PRODUCT_V3H)) {
-		pDDR_REGDEF_TBL = (const uint32_t *)&DDR_REGDEF_TBL[3][0];
+	} else if (prr_product == PRR_PRODUCT_M3) {
+		p_ddr_regdef_tbl =
+			(const uint32_t *)&DDR_REGDEF_TBL[1][0];
+	} else if ((prr_product == PRR_PRODUCT_M3N) ||
+		   (prr_product == PRR_PRODUCT_V3H)) {
+		p_ddr_regdef_tbl =
+			(const uint32_t *)&DDR_REGDEF_TBL[3][0];
 	} else {
 		FATAL_MSG("BL2: DDR:Unknown Product\n");
 		return 0xff;
 	}
 
-	if (((Prr_Product == PRR_PRODUCT_H3) && (Prr_Cut <= PRR_PRODUCT_11))
-	    || ((Prr_Product == PRR_PRODUCT_M3) && (Prr_Cut < PRR_PRODUCT_30))) {
+	if (((prr_product == PRR_PRODUCT_H3) && (prr_cut <= PRR_PRODUCT_11)) ||
+	    ((prr_product == PRR_PRODUCT_M3) && (prr_cut < PRR_PRODUCT_30))) {
 		/* non : H3 Ver.1.x/M3-W Ver.1.x not support */
 	} else {
 		mmio_write_32(DBSC_DBSYSCNT0, 0x00001234);
 	}
 
-	/***********************************************************************
-	Judge board type
-	***********************************************************************/
-	_cnf_BOARDTYPE = boardcnf_get_brd_type();
-	if (_cnf_BOARDTYPE >= BOARDNUM) {
+	/* Judge board type */
+	cnf_boardtype = boardcnf_get_brd_type();
+	if (cnf_boardtype >= BOARDNUM) {
 		FATAL_MSG("BL2: DDR:Unknown Board\n");
 		return 0xff;
 	}
-	Boardcnf = (const struct _boardcnf *)&boardcnfs[_cnf_BOARDTYPE];
+	board_cnf = (const struct _boardcnf *)&boardcnfs[cnf_boardtype];
 
 /* RCAR_DRAM_SPLIT_2CH           (2U) */
 #if RCAR_DRAM_SPLIT == 2
-	/***********************************************************************
-	H3(Test for future H3-N): Swap ch2 and ch1 for 2ch-split
-	***********************************************************************/
-	if ((Prr_Product == PRR_PRODUCT_H3) && (Boardcnf->phyvalid == 0x05)) {
+	/* H3(Test for future H3-N): Swap ch2 and ch1 for 2ch-split */
+	if ((prr_product == PRR_PRODUCT_H3) && (board_cnf->phyvalid == 0x05)) {
 		mmio_write_32(DBSC_DBMEMSWAPCONF0, 0x00000006);
 		ddr_phyvalid = 0x03;
 	} else {
-		ddr_phyvalid = Boardcnf->phyvalid;
+		ddr_phyvalid = board_cnf->phyvalid;
 	}
 #else /* RCAR_DRAM_SPLIT_2CH */
-	ddr_phyvalid = Boardcnf->phyvalid;
+	ddr_phyvalid = board_cnf->phyvalid;
 #endif /* RCAR_DRAM_SPLIT_2CH */
 
 	max_density = 0;
@@ -4303,53 +4184,46 @@ int32_t rcar_dram_init(void)
 	}
 
 	foreach_ech(ch)
-	    for (cs = 0; cs < CS_CNT; cs++)
+	for (cs = 0; cs < CS_CNT; cs++)
 		ddr_density[ch][cs] = 0xff;
 
 	foreach_vch(ch) {
 		for (cs = 0; cs < CS_CNT; cs++) {
-			dataL = Boardcnf->ch[ch].ddr_density[cs];
-			ddr_density[ch][cs] = dataL;
+			data_l = board_cnf->ch[ch].ddr_density[cs];
+			ddr_density[ch][cs] = data_l;
 
-			if (dataL == 0xff)
+			if (data_l == 0xff)
 				continue;
-			if (dataL > max_density)
-				max_density = dataL;
-			if ((cs == 1) && (Prr_Product == PRR_PRODUCT_H3)
-			    && (Prr_Cut <= PRR_PRODUCT_11))
+			if (data_l > max_density)
+				max_density = data_l;
+			if ((cs == 1) && (prr_product == PRR_PRODUCT_H3) &&
+			    (prr_cut <= PRR_PRODUCT_11))
 				continue;
 			ch_have_this_cs[cs] |= (1U << ch);
 		}
 	}
 
-	/***********************************************************************
-	Judge board clock frequency (in MHz)
-	***********************************************************************/
-	boardcnf_get_brd_clk(_cnf_BOARDTYPE, &brd_clk, &brd_clkdiv);
+	/* Judge board clock frequency (in MHz) */
+	boardcnf_get_brd_clk(cnf_boardtype, &brd_clk, &brd_clkdiv);
 	if ((brd_clk / brd_clkdiv) > 25) {
 		brd_clkdiva = 1;
 	} else {
 		brd_clkdiva = 0;
 	}
 
-	/***********************************************************************
-	Judge ddr operating frequency clock(in Mbps)
-	***********************************************************************/
-	boardcnf_get_ddr_mbps(_cnf_BOARDTYPE, &ddr_mbps, &ddr_mbpsdiv);
+	/* Judge ddr operating frequency clock(in Mbps) */
+	boardcnf_get_ddr_mbps(cnf_boardtype, &ddr_mbps, &ddr_mbpsdiv);
 
 	ddr0800_mul = CLK_DIV(800, 2, brd_clk, brd_clkdiv * (brd_clkdiva + 1));
 
-	ddr_mul =
-	    CLK_DIV(ddr_mbps, ddr_mbpsdiv * 2, brd_clk,
-		    brd_clkdiv * (brd_clkdiva + 1));
+	ddr_mul = CLK_DIV(ddr_mbps, ddr_mbpsdiv * 2, brd_clk,
+			  brd_clkdiv * (brd_clkdiva + 1));
 
-	/***********************************************************************
-	Adjust tccd
-	***********************************************************************/
-	dataL = (0x00006000 & mmio_read_32(RST_MODEMR)) >> 13;
+	/* Adjust tccd */
+	data_l = (0x00006000 & mmio_read_32(RST_MODEMR)) >> 13;
 	bus_mbps = 0;
 	bus_mbpsdiv = 0;
-	switch (dataL) {
+	switch (data_l) {
 	case 0:
 		bus_mbps = brd_clk * 0x60 * 2;
 		bus_mbpsdiv = brd_clkdiv * 1;
@@ -4384,16 +4258,12 @@ int32_t rcar_dram_init(void)
 
 	MSG_LF("Start\n");
 
-	/***********************************************************************
-	PLL Setting
-	***********************************************************************/
+	/* PLL Setting */
 	pll3_control(1);
 
-	/***********************************************************************
-	initialize DDR
-	***********************************************************************/
-	dataL = init_ddr();
-	if (dataL == ddr_phyvalid) {
+	/* initialize DDR */
+	data_l = init_ddr();
+	if (data_l == ddr_phyvalid) {
 		failcount = 0;
 	} else {
 		failcount = 1;
@@ -4401,8 +4271,8 @@ int32_t rcar_dram_init(void)
 
 	foreach_vch(ch)
 	    mmio_write_32(DBSC_DBPDLK(ch), 0x00000000);
-	if (((Prr_Product == PRR_PRODUCT_H3) && (Prr_Cut <= PRR_PRODUCT_11))
-	    || ((Prr_Product == PRR_PRODUCT_M3) && (Prr_Cut < PRR_PRODUCT_30))) {
+	if (((prr_product == PRR_PRODUCT_H3) && (prr_cut <= PRR_PRODUCT_11)) ||
+	    ((prr_product == PRR_PRODUCT_M3) && (prr_cut < PRR_PRODUCT_30))) {
 		/* non : H3 Ver.1.x/M3-W Ver.1.x not support */
 	} else {
 		mmio_write_32(DBSC_DBSYSCNT0, 0x00000000);
@@ -4418,7 +4288,7 @@ int32_t rcar_dram_init(void)
 void pvtcode_update(void)
 {
 	uint32_t ch;
-	uint32_t dataL;
+	uint32_t data_l;
 	uint32_t pvtp[4], pvtn[4], pvtp_init, pvtn_init;
 	int32_t pvtp_tmp, pvtn_tmp;
 
@@ -4444,41 +4314,42 @@ void pvtcode_update(void)
 					  pvtn_init) / (pvtn_tmp) +
 			    6 * pvtp_tmp + pvtp_init;
 		}
-		if ((Prr_Product == PRR_PRODUCT_H3)
-		    && (Prr_Cut <= PRR_PRODUCT_11)) {
-			dataL = pvtp[ch] | (pvtn[ch] << 6) | (tcal.tcomp_cal[ch] & 0xfffff000);
+		if ((prr_product == PRR_PRODUCT_H3) &&
+		    (prr_cut <= PRR_PRODUCT_11)) {
+			data_l = pvtp[ch] | (pvtn[ch] << 6) |
+				 (tcal.tcomp_cal[ch] & 0xfffff000);
 			reg_ddrphy_write(ch,
 					 ddr_regdef_adr(_reg_PHY_PAD_FDBK_TERM),
-					 dataL | 0x00020000);
+					 data_l | 0x00020000);
 			reg_ddrphy_write(ch,
 					 ddr_regdef_adr(_reg_PHY_PAD_DATA_TERM),
-					 dataL);
+					 data_l);
 			reg_ddrphy_write(ch,
 					 ddr_regdef_adr(_reg_PHY_PAD_DQS_TERM),
-					 dataL);
+					 data_l);
 			reg_ddrphy_write(ch,
 					 ddr_regdef_adr(_reg_PHY_PAD_ADDR_TERM),
-					 dataL);
+					 data_l);
 			reg_ddrphy_write(ch,
 					 ddr_regdef_adr(_reg_PHY_PAD_CS_TERM),
-					 dataL);
+					 data_l);
 		} else {
-			dataL = pvtp[ch] | (pvtn[ch] << 6) | 0x00015000;
+			data_l = pvtp[ch] | (pvtn[ch] << 6) | 0x00015000;
 			reg_ddrphy_write(ch,
 					 ddr_regdef_adr(_reg_PHY_PAD_FDBK_TERM),
-					 dataL | 0x00020000);
+					 data_l | 0x00020000);
 			reg_ddrphy_write(ch,
 					 ddr_regdef_adr(_reg_PHY_PAD_DATA_TERM),
-					 dataL);
+					 data_l);
 			reg_ddrphy_write(ch,
 					 ddr_regdef_adr(_reg_PHY_PAD_DQS_TERM),
-					 dataL);
+					 data_l);
 			reg_ddrphy_write(ch,
 					 ddr_regdef_adr(_reg_PHY_PAD_ADDR_TERM),
-					 dataL);
+					 data_l);
 			reg_ddrphy_write(ch,
 					 ddr_regdef_adr(_reg_PHY_PAD_CS_TERM),
-					 dataL);
+					 data_l);
 		}
 	}
 }
@@ -4486,6 +4357,7 @@ void pvtcode_update(void)
 void pvtcode_update2(void)
 {
 	uint32_t ch;
+
 	foreach_vch(ch) {
 		reg_ddrphy_write(ch, ddr_regdef_adr(_reg_PHY_PAD_FDBK_TERM),
 				 tcal.init_cal[ch] | 0x00020000);
@@ -4503,7 +4375,7 @@ void pvtcode_update2(void)
 void ddr_padcal_tcompensate_getinit(uint32_t override)
 {
 	uint32_t ch;
-	uint32_t dataL;
+	uint32_t data_l;
 	uint32_t pvtp, pvtn;
 
 	tcal.init_temp = 0;
@@ -4518,43 +4390,43 @@ void ddr_padcal_tcompensate_getinit(uint32_t override)
 	}
 
 	if (!override) {
-		dataL = mmio_read_32(THS1_TEMP);
-		if (dataL < 2800) {
+		data_l = mmio_read_32(THS1_TEMP);
+		if (data_l < 2800) {
 			tcal.init_temp =
-			    (143 * (int32_t) dataL - 359000) / 1000;
+			    (143 * (int32_t)data_l - 359000) / 1000;
 		} else {
 			tcal.init_temp =
-			    (121 * (int32_t) dataL - 296300) / 1000;
+			    (121 * (int32_t)data_l - 296300) / 1000;
 		}
 
 		foreach_vch(ch) {
 			pvtp = (tcal.init_cal[ch] >> 0) & 0x000003F;
 			pvtn = (tcal.init_cal[ch] >> 6) & 0x000003F;
-			if ((int32_t) pvtp >
+			if ((int32_t)pvtp >
 			    ((tcal.init_temp * 29 - 3625) / 1000))
 				pvtp =
-				    (int32_t) pvtp +
+				    (int32_t)pvtp +
 				    ((3625 - tcal.init_temp * 29) / 1000);
 			else
 				pvtp = 0;
 
-			if ((int32_t) pvtn >
+			if ((int32_t)pvtn >
 			    ((tcal.init_temp * 54 - 6750) / 1000))
 				pvtn =
-				    (int32_t) pvtn +
+				    (int32_t)pvtn +
 				    ((6750 - tcal.init_temp * 54) / 1000);
 			else
 				pvtn = 0;
 
-			if ((Prr_Product == PRR_PRODUCT_H3)
-			    && (Prr_Cut <= PRR_PRODUCT_11)) {
+			if ((prr_product == PRR_PRODUCT_H3) &&
+			    (prr_cut <= PRR_PRODUCT_11)) {
 				tcal.init_cal[ch] =
-				    (tcal.
-				     init_cal[ch] & 0xfffff000) | (pvtn << 6) |
-				    (pvtp);
+				    (tcal.init_cal[ch] & 0xfffff000) |
+				    (pvtn << 6) |
+				    pvtp;
 			} else {
 				tcal.init_cal[ch] =
-				    0x00015000 | (pvtn << 6) | (pvtp);
+				    0x00015000 | (pvtn << 6) | pvtp;
 			}
 		}
 		tcal.init_temp = 125;
@@ -4562,13 +4434,9 @@ void ddr_padcal_tcompensate_getinit(uint32_t override)
 }
 
 #ifndef ddr_qos_init_setting
-/*  for QoS init */
+/* For QoS init */
 uint8_t get_boardcnf_phyvalid(void)
 {
 	return ddr_phyvalid;
 }
 #endif /* ddr_qos_init_setting */
-
-/*******************************************************************************
- *	END
- ******************************************************************************/
diff --git a/drivers/staging/renesas/rcar/ddr/ddr_b/boot_init_dram_config.c b/drivers/renesas/rcar/ddr/ddr_b/boot_init_dram_config.c
index 5d1b078c9..f8caade27 100644
--- a/drivers/staging/renesas/rcar/ddr/ddr_b/boot_init_dram_config.c
+++ b/drivers/renesas/rcar/ddr/ddr_b/boot_init_dram_config.c
@@ -1,5 +1,6 @@
 /*
- * Copyright (c) 2015-2019, Renesas Electronics Corporation. All rights reserved.
+ * Copyright (c) 2015-2019, Renesas Electronics Corporation.
+ * All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -17,7 +18,7 @@ static uint32_t boardcnf_get_brd_type(void)
 #else
 static uint32_t boardcnf_get_brd_type(void)
 {
-	return (1);
+	return 1;
 }
 #endif
 
@@ -115,7 +116,7 @@ static const struct _boardcnf boardcnfs[BOARDNUM] = {
 		  0, 0, 0, 0, 0, 0, 0, 0,
 		  0, 0, 0, 0, 0, 0, 0, 0,
 		  0, 0, 0, 0, 0, 0, 0, 0}
-		 }
+		}
 		}
 	 },
 /* boardcnf[1] RENESAS KRIEK board with M3-W/SoC */
@@ -126,8 +127,8 @@ static const struct _boardcnf boardcnfs[BOARDNUM] = {
 	 0,
 	 0x300,
 	 0x0a0,
-	 {
-	  {
+	{
+	{
 	   {0x02, 0x02},
 	   0x00345201,
 	   0x3201,
@@ -147,7 +148,7 @@ static const struct _boardcnf boardcnfs[BOARDNUM] = {
 	    0, 0, 0, 0, 0, 0, 0, 0,
 	    0, 0, 0, 0, 0, 0, 0, 0}
 	   },
-	  {
+	{
 	   {0x02, 0x02},
 	   0x00302154,
 	   0x2310,
@@ -166,8 +167,8 @@ static const struct _boardcnf boardcnfs[BOARDNUM] = {
 	    0, 0, 0, 0, 0, 0, 0, 0,
 	    0, 0, 0, 0, 0, 0, 0, 0,
 	    0, 0, 0, 0, 0, 0, 0, 0}
-	   }
-	  }
+	}
+	}
 	 },
 /* boardcnf[2] RENESAS SALVATOR-X board with H3 Ver.1.x/SIP(8Gbit 1rank) */
 	{
@@ -177,8 +178,8 @@ static const struct _boardcnf boardcnfs[BOARDNUM] = {
 	 -320,
 	 0x300,
 	 0x0a0,
-	 {
-	  {
+	{
+	{
 	   {0x02, 0xff},
 	   0x00543210,
 	   0x3210,
@@ -198,7 +199,7 @@ static const struct _boardcnf boardcnfs[BOARDNUM] = {
 	    0, 0, 0, 0, 0, 0, 0, 0,
 	    0, 0, 0, 0, 0, 0, 0, 0}
 	   },
-	  {
+	{
 	   {0x02, 0xff},
 	   0x00543210,
 	   0x3102,
@@ -218,7 +219,7 @@ static const struct _boardcnf boardcnfs[BOARDNUM] = {
 	    0, 0, 0, 0, 0, 0, 0, 0,
 	    0, 0, 0, 0, 0, 0, 0, 0}
 	   },
-	  {
+	{
 	   {0x02, 0xff},
 	   0x00543210,
 	   0x0213,
@@ -238,7 +239,7 @@ static const struct _boardcnf boardcnfs[BOARDNUM] = {
 	    0, 0, 0, 0, 0, 0, 0, 0,
 	    0, 0, 0, 0, 0, 0, 0, 0}
 	   },
-	  {
+	{
 	   {0x02, 0xff},
 	   0x00543210,
 	   0x0213,
@@ -257,8 +258,8 @@ static const struct _boardcnf boardcnfs[BOARDNUM] = {
 	    0, 0, 0, 0, 0, 0, 0, 0,
 	    0, 0, 0, 0, 0, 0, 0, 0,
 	    0, 0, 0, 0, 0, 0, 0, 0}
-	   }
-	  }
+	}
+	}
 	 },
 /* boardcnf[3] RENESAS Starter Kit board with M3-W/SIP(8Gbit 1rank) */
 	{
@@ -268,8 +269,8 @@ static const struct _boardcnf boardcnfs[BOARDNUM] = {
 	 0,
 	 0x0300,
 	 0x00a0,
-	 {
-	  {
+	{
+	{
 	   {0x02, 0xFF},
 	   0x00543210U,
 	   0x3201,
@@ -289,7 +290,7 @@ static const struct _boardcnf boardcnfs[BOARDNUM] = {
 	    0, 0, 0, 0, 0, 0, 0, 0,
 	    0, 0, 0, 0, 0, 0, 0, 0}
 	   },
-	  {
+	{
 	   {0x02, 0xFF},
 	   0x00543210,
 	   0x2310,
@@ -308,8 +309,8 @@ static const struct _boardcnf boardcnfs[BOARDNUM] = {
 	    0, 0, 0, 0, 0, 0, 0, 0,
 	    0, 0, 0, 0, 0, 0, 0, 0,
 	    0, 0, 0, 0, 0, 0, 0, 0}
-	   }
-	  }
+	}
+	}
 	 },
 /* boardcnf[4] RENESAS SALVATOR-M(1rank) board with H3 Ver.1.x/SoC */
 	{
@@ -319,8 +320,8 @@ static const struct _boardcnf boardcnfs[BOARDNUM] = {
 	 -320,
 	 0x300,
 	 0x0a0,
-	 {
-	  {
+	{
+	{
 	   {0x02, 0xff},
 	   0x00315024,
 	   0x3120,
@@ -340,7 +341,7 @@ static const struct _boardcnf boardcnfs[BOARDNUM] = {
 	    0, 0, 0, 0, 0, 0, 0, 0,
 	    0, 0, 0, 0, 0, 0, 0, 0}
 	   },
-	  {
+	{
 	   {0x02, 0xff},
 	   0x00025143,
 	   0x3210,
@@ -360,7 +361,7 @@ static const struct _boardcnf boardcnfs[BOARDNUM] = {
 	    0, 0, 0, 0, 0, 0, 0, 0,
 	    0, 0, 0, 0, 0, 0, 0, 0}
 	   },
-	  {
+	{
 	   {0x02, 0xff},
 	   0x00523104,
 	   0x2301,
@@ -380,7 +381,7 @@ static const struct _boardcnf boardcnfs[BOARDNUM] = {
 	    0, 0, 0, 0, 0, 0, 0, 0,
 	    0, 0, 0, 0, 0, 0, 0, 0}
 	   },
-	  {
+	{
 	   {0x02, 0xff},
 	   0x00153402,
 	   0x2031,
@@ -399,8 +400,8 @@ static const struct _boardcnf boardcnfs[BOARDNUM] = {
 	    0, 0, 0, 0, 0, 0, 0, 0,
 	    0, 0, 0, 0, 0, 0, 0, 0,
 	    0, 0, 0, 0, 0, 0, 0, 0}
-	   }
-	  }
+	}
+	}
 	 },
 /* boardcnf[5] RENESAS KRIEK-1rank board with M3-W/SoC */
 	{
@@ -410,8 +411,8 @@ static const struct _boardcnf boardcnfs[BOARDNUM] = {
 	 0,
 	 0x300,
 	 0x0a0,
-	 {
-	  {
+	{
+	{
 	   {0x02, 0xff},
 	   0x00345201,
 	   0x3201,
@@ -431,7 +432,7 @@ static const struct _boardcnf boardcnfs[BOARDNUM] = {
 	    0, 0, 0, 0, 0, 0, 0, 0,
 	    0, 0, 0, 0, 0, 0, 0, 0}
 	   },
-	  {
+	{
 	   {0x02, 0xff},
 	   0x00302154,
 	   0x2310,
@@ -450,8 +451,8 @@ static const struct _boardcnf boardcnfs[BOARDNUM] = {
 	    0, 0, 0, 0, 0, 0, 0, 0,
 	    0, 0, 0, 0, 0, 0, 0, 0,
 	    0, 0, 0, 0, 0, 0, 0, 0}
-	   }
-	  }
+	}
+	}
 	 },
 /* boardcnf[6] RENESAS SALVATOR-X board with H3 Ver.1.x/SIP(8Gbit 2rank) */
 	{
@@ -461,8 +462,8 @@ static const struct _boardcnf boardcnfs[BOARDNUM] = {
 	 -320,
 	 0x300,
 	 0x0a0,
-	 {
-	  {
+	{
+	{
 	   {0x02, 0x02},
 	   0x00543210,
 	   0x3210,
@@ -482,7 +483,7 @@ static const struct _boardcnf boardcnfs[BOARDNUM] = {
 	    0, 0, 0, 0, 0, 0, 0, 0,
 	    0, 0, 0, 0, 0, 0, 0, 0}
 	   },
-	  {
+	{
 	   {0x02, 0x02},
 	   0x00543210,
 	   0x3102,
@@ -502,7 +503,7 @@ static const struct _boardcnf boardcnfs[BOARDNUM] = {
 	    0, 0, 0, 0, 0, 0, 0, 0,
 	    0, 0, 0, 0, 0, 0, 0, 0}
 	   },
-	  {
+	{
 	   {0x02, 0x02},
 	   0x00543210,
 	   0x0213,
@@ -522,7 +523,7 @@ static const struct _boardcnf boardcnfs[BOARDNUM] = {
 	    0, 0, 0, 0, 0, 0, 0, 0,
 	    0, 0, 0, 0, 0, 0, 0, 0}
 	   },
-	  {
+	{
 	   {0x02, 0x02},
 	   0x00543210,
 	   0x0213,
@@ -541,10 +542,13 @@ static const struct _boardcnf boardcnfs[BOARDNUM] = {
 	    0, 0, 0, 0, 0, 0, 0, 0,
 	    0, 0, 0, 0, 0, 0, 0, 0,
 	    0, 0, 0, 0, 0, 0, 0, 0}
-	   }
-	  }
+	}
+	}
 	 },
-/* boardcnf[7] RENESAS SALVATOR-X board with H3 Ver.2.0 or later/SIP(8Gbit 1rank) */
+/*
+ * boardcnf[7] RENESAS SALVATOR-X board with
+ * H3 Ver.2.0 or later/SIP(8Gbit 1rank)
+ */
 	{
 	 0x0f,
 	 0x01,
@@ -552,8 +556,8 @@ static const struct _boardcnf boardcnfs[BOARDNUM] = {
 	 0,
 	 0x300,
 	 0x0a0,
-	 {
-	  {
+	{
+	{
 	   {0x02, 0xff},
 	   0x00543210,
 	   0x2310,
@@ -573,7 +577,7 @@ static const struct _boardcnf boardcnfs[BOARDNUM] = {
 	    0, 0, 0, 0, 0, 0, 0, 0,
 	    0, 0, 0, 0, 0, 0, 0, 0}
 	   },
-	  {
+	{
 	   {0x02, 0xff},
 	   0x00105432,
 	   0x3210,
@@ -593,7 +597,7 @@ static const struct _boardcnf boardcnfs[BOARDNUM] = {
 	    0, 0, 0, 0, 0, 0, 0, 0,
 	    0, 0, 0, 0, 0, 0, 0, 0}
 	   },
-	  {
+	{
 	   {0x02, 0xff},
 	   0x00543210,
 	   0x2301,
@@ -613,7 +617,7 @@ static const struct _boardcnf boardcnfs[BOARDNUM] = {
 	    0, 0, 0, 0, 0, 0, 0, 0,
 	    0, 0, 0, 0, 0, 0, 0, 0}
 	   },
-	  {
+	{
 	   {0x02, 0xff},
 	   0x00543210,
 	   0x2301,
@@ -632,10 +636,13 @@ static const struct _boardcnf boardcnfs[BOARDNUM] = {
 	    0, 0, 0, 0, 0, 0, 0, 0,
 	    0, 0, 0, 0, 0, 0, 0, 0,
 	    0, 0, 0, 0, 0, 0, 0, 0}
-	   }
-	  }
+	}
+	}
 	 },
-/* boardcnf[8] RENESAS SALVATOR-X board with H3 Ver.2.0 or later/SIP(8Gbit 2rank) */
+/*
+ * boardcnf[8] RENESAS SALVATOR-X board with
+ * H3 Ver.2.0 or later/SIP(8Gbit 2rank)
+ */
 	{
 #if RCAR_DRAM_CHANNEL == 5
 	 0x05,
@@ -647,8 +654,8 @@ static const struct _boardcnf boardcnfs[BOARDNUM] = {
 	 0,
 	 0x300,
 	 0x0a0,
-	 {
-	  {
+	{
+	{
 	   {0x02, 0x02},
 	   0x00543210,
 	   0x2310,
@@ -669,7 +676,7 @@ static const struct _boardcnf boardcnfs[BOARDNUM] = {
 	    0, 0, 0, 0, 0, 0, 0, 0}
 	   },
 #if ((RCAR_DRAM_CHANNEL == 5) && (RCAR_DRAM_SPLIT == 2))
-	  {
+	{
 	   {0x02, 0x02},
 	   0x00543210,
 	   0x2301,
@@ -690,7 +697,7 @@ static const struct _boardcnf boardcnfs[BOARDNUM] = {
 	    0, 0, 0, 0, 0, 0, 0, 0}
 	   },
 #else
-	  {
+	{
 	   {0x02, 0x02},
 	   0x00105432,
 	   0x3210,
@@ -711,7 +718,7 @@ static const struct _boardcnf boardcnfs[BOARDNUM] = {
 	    0, 0, 0, 0, 0, 0, 0, 0}
 	   },
 #endif
-	  {
+	{
 	   {0x02, 0x02},
 	   0x00543210,
 	   0x2301,
@@ -731,7 +738,7 @@ static const struct _boardcnf boardcnfs[BOARDNUM] = {
 	    0, 0, 0, 0, 0, 0, 0, 0,
 	    0, 0, 0, 0, 0, 0, 0, 0}
 	   },
-	  {
+	{
 	   {0x02, 0x02},
 	   0x00543210,
 	   0x2301,
@@ -750,8 +757,8 @@ static const struct _boardcnf boardcnfs[BOARDNUM] = {
 	    0, 0, 0, 0, 0, 0, 0, 0,
 	    0, 0, 0, 0, 0, 0, 0, 0,
 	    0, 0, 0, 0, 0, 0, 0, 0}
-	   }
-	  }
+	}
+	}
 	 },
 /* boardcnf[9] RENESAS SALVATOR-MS(1rank) board with H3 Ver.2.0 or later/SoC */
 	{
@@ -761,8 +768,8 @@ static const struct _boardcnf boardcnfs[BOARDNUM] = {
 	 0,
 	 0x300,
 	 0x0a0,
-	 {
-	  {
+	{
+	{
 	   {0x02, 0xff},
 	   0x00543210,
 	   0x3210,
@@ -782,7 +789,7 @@ static const struct _boardcnf boardcnfs[BOARDNUM] = {
 	    0, 0, 0, 0, 0, 0, 0, 0,
 	    0, 0, 0, 0, 0, 0, 0, 0}
 	   },
-	  {
+	{
 	   {0x02, 0xff},
 	   0x00543210,
 	   0x2301,
@@ -802,7 +809,7 @@ static const struct _boardcnf boardcnfs[BOARDNUM] = {
 	    0, 0, 0, 0, 0, 0, 0, 0,
 	    0, 0, 0, 0, 0, 0, 0, 0}
 	   },
-	  {
+	{
 	   {0x02, 0xff},
 	   0x00452103,
 	   0x3210,
@@ -822,7 +829,7 @@ static const struct _boardcnf boardcnfs[BOARDNUM] = {
 	    0, 0, 0, 0, 0, 0, 0, 0,
 	    0, 0, 0, 0, 0, 0, 0, 0}
 	   },
-	  {
+	{
 	   {0x02, 0xff},
 	   0x00520413,
 	   0x2301,
@@ -841,8 +848,8 @@ static const struct _boardcnf boardcnfs[BOARDNUM] = {
 	    0, 0, 0, 0, 0, 0, 0, 0,
 	    0, 0, 0, 0, 0, 0, 0, 0,
 	    0, 0, 0, 0, 0, 0, 0, 0}
-	   }
-	  }
+	}
+	}
 	 },
 /* boardcnf[10] RENESAS Kriek(2rank) board with M3-N/SoC */
 	{
@@ -852,8 +859,8 @@ static const struct _boardcnf boardcnfs[BOARDNUM] = {
 	 0,
 	 0x300,
 	 0x0a0,
-	 {
-	  {
+	{
+	{
 	   {0x02, 0x02},
 	   0x00345201,
 	   0x3201,
@@ -872,8 +879,8 @@ static const struct _boardcnf boardcnfs[BOARDNUM] = {
 	    0, 0, 0, 0, 0, 0, 0, 0,
 	    0, 0, 0, 0, 0, 0, 0, 0,
 	    0, 0, 0, 0, 0, 0, 0, 0}
-	   }
-	  }
+	}
+	}
 	 },
 /* boardcnf[11] RENESAS SALVATOR-X board with M3-N/SIP(8Gbit 2rank) */
 	{
@@ -883,8 +890,8 @@ static const struct _boardcnf boardcnfs[BOARDNUM] = {
 	 0,
 	 0x300,
 	 0x0a0,
-	 {
-	  {
+	{
+	{
 #if (RCAR_DRAM_LPDDR4_MEMCONF == 2)
 	   {0x04, 0x04},
 #else
@@ -907,8 +914,8 @@ static const struct _boardcnf boardcnfs[BOARDNUM] = {
 	    0, 0, 0, 0, 0, 0, 0, 0,
 	    0, 0, 0, 0, 0, 0, 0, 0,
 	    0, 0, 0, 0, 0, 0, 0, 0}
-	   }
-	  }
+	}
+	}
 	 },
 /* boardcnf[12] RENESAS CONDOR board with V3H/SoC */
 	{
@@ -918,8 +925,8 @@ static const struct _boardcnf boardcnfs[BOARDNUM] = {
 	 0,
 	 0x300,
 	 0x0a0,
-	 {
-	  {
+	{
+	{
 	   {0x02, 0x02},
 	   0x00501342,
 	   0x3201,
@@ -938,8 +945,8 @@ static const struct _boardcnf boardcnfs[BOARDNUM] = {
 	    0, 0, 0, 0, 0, 0, 0, 0,
 	    0, 0, 0, 0, 0, 0, 0, 0,
 	    0, 0, 0, 0, 0, 0, 0, 0}
-	   }
-	  }
+	}
+	}
 	 },
 /* boardcnf[13] RENESAS KRIEK board with PM3/SoC */
 	{
@@ -949,8 +956,8 @@ static const struct _boardcnf boardcnfs[BOARDNUM] = {
 	 -320,
 	 0x300,
 	 0x0a0,
-	 {
-	  {
+	{
+	{
 	   {0x02, 0x02},
 	   0x00345201,
 	   0x3201,
@@ -970,7 +977,7 @@ static const struct _boardcnf boardcnfs[BOARDNUM] = {
 	    0, 0, 0, 0, 0, 0, 0, 0,
 	    0, 0, 0, 0, 0, 0, 0, 0}
 	   },
-	  {
+	{
 	   {0x02, 0x02},
 	   0x00302154,
 	   0x2310,
@@ -990,7 +997,7 @@ static const struct _boardcnf boardcnfs[BOARDNUM] = {
 	    0, 0, 0, 0, 0, 0, 0, 0,
 	    0, 0, 0, 0, 0, 0, 0, 0}
 	   },
-	  {
+	{
 	   {0x02, 0x02},
 	   0x00302154,
 	   0x2310,
@@ -1010,7 +1017,7 @@ static const struct _boardcnf boardcnfs[BOARDNUM] = {
 	    0, 0, 0, 0, 0, 0, 0, 0,
 	    0, 0, 0, 0, 0, 0, 0, 0}
 	   },
-	  {
+	{
 	   {0xff, 0xff},
 	   0,
 	   0,
@@ -1029,8 +1036,8 @@ static const struct _boardcnf boardcnfs[BOARDNUM] = {
 	    0, 0, 0, 0, 0, 0, 0, 0,
 	    0, 0, 0, 0, 0, 0, 0, 0,
 	    0, 0, 0, 0, 0, 0, 0, 0}
-	   }
-	  }
+	}
+	}
 	 },
 /* boardcnf[14] SALVATOR-X board with H3 Ver.2.0 or later/SIP(16Gbit 1rank) */
 	{
@@ -1044,8 +1051,8 @@ static const struct _boardcnf boardcnfs[BOARDNUM] = {
 	 0,
 	 0x300,
 	 0x0a0,
-	 {
-	  {
+	{
+	{
 	   {0x04, 0xff},
 	   0x00543210,
 	   0x2310,
@@ -1066,7 +1073,7 @@ static const struct _boardcnf boardcnfs[BOARDNUM] = {
 	    0, 0, 0, 0, 0, 0, 0, 0}
 	   },
 #if ((RCAR_DRAM_CHANNEL == 5) && (RCAR_DRAM_SPLIT == 2))
-	  {
+	{
 	   {0x04, 0xff},
 	   0x00543210,
 	   0x2301,
@@ -1087,7 +1094,7 @@ static const struct _boardcnf boardcnfs[BOARDNUM] = {
 	    0, 0, 0, 0, 0, 0, 0, 0}
 	   },
 #else
-	  {
+	{
 	   {0x04, 0xff},
 	   0x00105432,
 	   0x3210,
@@ -1108,7 +1115,7 @@ static const struct _boardcnf boardcnfs[BOARDNUM] = {
 	    0, 0, 0, 0, 0, 0, 0, 0}
 	   },
 #endif
-	  {
+	{
 	   {0x04, 0xff},
 	   0x00543210,
 	   0x2301,
@@ -1128,7 +1135,7 @@ static const struct _boardcnf boardcnfs[BOARDNUM] = {
 	    0, 0, 0, 0, 0, 0, 0, 0,
 	    0, 0, 0, 0, 0, 0, 0, 0}
 	   },
-	  {
+	{
 	   {0x04, 0xff},
 	   0x00543210,
 	   0x2301,
@@ -1147,8 +1154,8 @@ static const struct _boardcnf boardcnfs[BOARDNUM] = {
 	    0, 0, 0, 0, 0, 0, 0, 0,
 	    0, 0, 0, 0, 0, 0, 0, 0,
 	    0, 0, 0, 0, 0, 0, 0, 0}
-	   }
-	  }
+	}
+	}
 	 },
 /* boardcnf[15] RENESAS KRIEK board with H3N */
 	{
@@ -1158,8 +1165,8 @@ static const struct _boardcnf boardcnfs[BOARDNUM] = {
 	 0,
 	 0x300,
 	 0x0a0,
-	 {
-	  {
+	{
+	{
 	   {0x02, 0x02},
 	   0x00345201,
 	   0x3201,
@@ -1179,7 +1186,7 @@ static const struct _boardcnf boardcnfs[BOARDNUM] = {
 	    0, 0, 0, 0, 0, 0, 0, 0,
 	    0, 0, 0, 0, 0, 0, 0, 0}
 	   },
-	  {
+	{
 	   {0x02, 0x02},
 	   0x00302154,
 	   0x2310,
@@ -1199,7 +1206,7 @@ static const struct _boardcnf boardcnfs[BOARDNUM] = {
 	    0, 0, 0, 0, 0, 0, 0, 0,
 	    0, 0, 0, 0, 0, 0, 0, 0}
 	   },
-	  {
+	{
 	   {0x02, 0x02},
 	   0x00302154,
 	   0x2310,
@@ -1219,7 +1226,7 @@ static const struct _boardcnf boardcnfs[BOARDNUM] = {
 	    0, 0, 0, 0, 0, 0, 0, 0,
 	    0, 0, 0, 0, 0, 0, 0, 0}
 	   },
-	  {
+	{
 	   {0xff, 0xff},
 	   0,
 	   0,
@@ -1238,8 +1245,8 @@ static const struct _boardcnf boardcnfs[BOARDNUM] = {
 	    0, 0, 0, 0, 0, 0, 0, 0,
 	    0, 0, 0, 0, 0, 0, 0, 0,
 	    0, 0, 0, 0, 0, 0, 0, 0}
-	   }
-	  }
+	}
+	}
 	 },
 /* boardcnf[16] RENESAS KRIEK-P2P board with M3-W/SoC */
 	{
@@ -1249,8 +1256,8 @@ static const struct _boardcnf boardcnfs[BOARDNUM] = {
 	 0,
 	 0x0300,
 	 0x00a0,
-	 {
-	  {
+	{
+	{
 	   {0x04, 0x04},
 	    0x520314FFFF523041,
 	    0x3201,
@@ -1270,7 +1277,7 @@ static const struct _boardcnf boardcnfs[BOARDNUM] = {
 	    0, 0, 0, 0, 0, 0, 0, 0,
 	    0, 0, 0, 0, 0, 0, 0, 0}
 	   },
-	  {
+	{
 	   {0x04, 0x04},
 	    0x314250FFFF312405,
 	    0x2310,
@@ -1289,8 +1296,8 @@ static const struct _boardcnf boardcnfs[BOARDNUM] = {
 	    0, 0, 0, 0, 0, 0, 0, 0,
 	    0, 0, 0, 0, 0, 0, 0, 0,
 	    0, 0, 0, 0, 0, 0, 0, 0}
-	   }
-	  }
+	}
+	}
 	 },
 /* boardcnf[17] RENESAS KRIEK-P2P board with M3-N/SoC */
 	{
@@ -1300,8 +1307,8 @@ static const struct _boardcnf boardcnfs[BOARDNUM] = {
 	 0,
 	 0x0300,
 	 0x00a0,
-	 {
-	  {
+	{
+	{
 	   {0x04, 0x04},
 	    0x520314FFFF523041,
 	    0x3201,
@@ -1320,8 +1327,8 @@ static const struct _boardcnf boardcnfs[BOARDNUM] = {
 	    0, 0, 0, 0, 0, 0, 0, 0,
 	    0, 0, 0, 0, 0, 0, 0, 0,
 	    0, 0, 0, 0, 0, 0, 0, 0}
-	  }
-	 }
+	}
+	}
 	},
 /* boardcnf[18] RENESAS SALVATOR-X board with M3-W/SIP(16Gbit 2rank) */
 	{
@@ -1331,8 +1338,8 @@ static const struct _boardcnf boardcnfs[BOARDNUM] = {
 	 0,
 	 0x0300,
 	 0x00a0,
-	 {
-	  {
+	{
+	{
 	   {0x04, 0x04},
 	    0x00543210,
 	    0x3201,
@@ -1352,7 +1359,7 @@ static const struct _boardcnf boardcnfs[BOARDNUM] = {
 	    0, 0, 0, 0, 0, 0, 0, 0,
 	    0, 0, 0, 0, 0, 0, 0, 0}
 	   },
-	  {
+	{
 	   {0x04, 0x04},
 	    0x00543210,
 	    0x2310,
@@ -1371,19 +1378,19 @@ static const struct _boardcnf boardcnfs[BOARDNUM] = {
 	    0, 0, 0, 0, 0, 0, 0, 0,
 	    0, 0, 0, 0, 0, 0, 0, 0,
 	    0, 0, 0, 0, 0, 0, 0, 0}
-	  }
-	 }
+	}
+	}
 	},
 /* boardcnf[19] RENESAS SALVATOR-X board with M3-W/SIP(16Gbit 1rank) */
-        {
-         0x03,
-         0x01,
-         0x02c0,
-         0,
-         0x0300,
-         0x00a0,
-	 {
-          {
+	{
+	 0x03,
+	 0x01,
+	 0x02c0,
+	 0,
+	 0x0300,
+	 0x00a0,
+	{
+	{
 	   {0x04, 0xff},
 	    0x00543210,
 	    0x3201,
@@ -1403,7 +1410,7 @@ static const struct _boardcnf boardcnfs[BOARDNUM] = {
 	    0, 0, 0, 0, 0, 0, 0, 0,
 	    0, 0, 0, 0, 0, 0, 0, 0}
 	   },
-	  {
+	{
 	   {0x04, 0xff},
 	    0x00543210,
 	    0x2310,
@@ -1422,118 +1429,118 @@ static const struct _boardcnf boardcnfs[BOARDNUM] = {
 	    0, 0, 0, 0, 0, 0, 0, 0,
 	    0, 0, 0, 0, 0, 0, 0, 0,
 	    0, 0, 0, 0, 0, 0, 0, 0}
-	  }
-	 }
+	}
+	}
 	},
 /* boardcnf[20] RENESAS KRIEK 16Gbit/2rank/2ch board with M3-W/SoC */
-        {
-         0x03,
-         0x01,
-         0x02c0,
-         0,
-         0x0300,
-         0x00a0,
-         {
-          {
-           {0x04, 0x04},
-            0x00345201,
-            0x3201,
-           {0x01672543, 0x45361207, 0x45632107, 0x60715234},
-           {0x08, 0x08, 0x08, 0x08},
-            WDQLVL_PAT,
-           {0, 0, 0, 0, 0, 0, 0, 0,
+	{
+	 0x03,
+	 0x01,
+	 0x02c0,
+	 0,
+	 0x0300,
+	 0x00a0,
+	{
+	{
+	   {0x04, 0x04},
+	    0x00345201,
+	    0x3201,
+	   {0x01672543, 0x45361207, 0x45632107, 0x60715234},
+	   {0x08, 0x08, 0x08, 0x08},
+	    WDQLVL_PAT,
+	   {0, 0, 0, 0, 0, 0, 0, 0,
 	    0, 0},
-           {0, 0, 0, 0},
-           {0, 0, 0, 0, 0, 0, 0, 0,
-            0, 0, 0, 0, 0, 0, 0, 0,
-            0, 0, 0, 0, 0, 0, 0, 0,
-            0, 0, 0, 0, 0, 0, 0, 0},
-           {0, 0, 0, 0},
-           {0, 0, 0, 0, 0, 0, 0, 0,
-            0, 0, 0, 0, 0, 0, 0, 0,
-            0, 0, 0, 0, 0, 0, 0, 0,
-            0, 0, 0, 0, 0, 0, 0, 0}
-           },
-          {
+	   {0, 0, 0, 0},
+	   {0, 0, 0, 0, 0, 0, 0, 0,
+	    0, 0, 0, 0, 0, 0, 0, 0,
+	    0, 0, 0, 0, 0, 0, 0, 0,
+	    0, 0, 0, 0, 0, 0, 0, 0},
+	   {0, 0, 0, 0},
+	   {0, 0, 0, 0, 0, 0, 0, 0,
+	    0, 0, 0, 0, 0, 0, 0, 0,
+	    0, 0, 0, 0, 0, 0, 0, 0,
+	    0, 0, 0, 0, 0, 0, 0, 0}
+	   },
+	{
 	   {0x04, 0x04},
-            0x00302154,
-            0x2310,
-           {0x01672543, 0x45361207, 0x45632107, 0x60715234},
-           {0x08, 0x08, 0x08, 0x08},
-           WDQLVL_PAT,
-           {0, 0, 0, 0, 0, 0, 0, 0,
-            0, 0},
-           {0, 0, 0, 0},
-           {0, 0, 0, 0, 0, 0, 0, 0,
-            0, 0, 0, 0, 0, 0, 0, 0,
-            0, 0, 0, 0, 0, 0, 0, 0,
-            0, 0, 0, 0, 0, 0, 0, 0},
-           {0, 0, 0, 0},
-           {0, 0, 0, 0, 0, 0, 0, 0,
-            0, 0, 0, 0, 0, 0, 0, 0,
-            0, 0, 0, 0, 0, 0, 0, 0,
-            0, 0, 0, 0, 0, 0, 0, 0}
-          }
-         }
-        },
+	    0x00302154,
+	    0x2310,
+	   {0x01672543, 0x45361207, 0x45632107, 0x60715234},
+	   {0x08, 0x08, 0x08, 0x08},
+	   WDQLVL_PAT,
+	   {0, 0, 0, 0, 0, 0, 0, 0,
+	    0, 0},
+	   {0, 0, 0, 0},
+	   {0, 0, 0, 0, 0, 0, 0, 0,
+	    0, 0, 0, 0, 0, 0, 0, 0,
+	    0, 0, 0, 0, 0, 0, 0, 0,
+	    0, 0, 0, 0, 0, 0, 0, 0},
+	   {0, 0, 0, 0},
+	   {0, 0, 0, 0, 0, 0, 0, 0,
+	    0, 0, 0, 0, 0, 0, 0, 0,
+	    0, 0, 0, 0, 0, 0, 0, 0,
+	    0, 0, 0, 0, 0, 0, 0, 0}
+	}
+	}
+	},
 /* boardcnf[21] RENESAS KRIEK 16Gbit/1rank/2ch board with M3-W/SoC */
-        {
-         0x03,
-         0x01,
-         0x02c0,
-         0,
-         0x0300,
-         0x00a0,
-         {
-          {
-           {0x04, 0xff},
-            0x00345201,
-            0x3201,
-           {0x01672543, 0x45361207, 0x45632107, 0x60715234},
-           {0x08, 0x08, 0x08, 0x08},
-           WDQLVL_PAT,
-           {0, 0, 0, 0, 0, 0, 0, 0,
-            0, 0},
-           {0, 0, 0, 0},
-           {0, 0, 0, 0, 0, 0, 0, 0,
-            0, 0, 0, 0, 0, 0, 0, 0,
-            0, 0, 0, 0, 0, 0, 0, 0,
-            0, 0, 0, 0, 0, 0, 0, 0},
-           {0, 0, 0, 0},
-           {0, 0, 0, 0, 0, 0, 0, 0,
-            0, 0, 0, 0, 0, 0, 0, 0,
-            0, 0, 0, 0, 0, 0, 0, 0,
-            0, 0, 0, 0, 0, 0, 0, 0}
-           },
-          {
-           {0x04, 0xff},
-            0x00302154,
-            0x2310,
-           {0x01672543, 0x45361207, 0x45632107, 0x60715234},
-           {0x08, 0x08, 0x08, 0x08},
-           WDQLVL_PAT,
-           {0, 0, 0, 0, 0, 0, 0, 0,
-            0, 0},
-           {0, 0, 0, 0},
-           {0, 0, 0, 0, 0, 0, 0, 0,
-            0, 0, 0, 0, 0, 0, 0, 0,
-            0, 0, 0, 0, 0, 0, 0, 0,
-            0, 0, 0, 0, 0, 0, 0, 0},
-           {0, 0, 0, 0},
-           {0, 0, 0, 0, 0, 0, 0, 0,
-            0, 0, 0, 0, 0, 0, 0, 0,
-            0, 0, 0, 0, 0, 0, 0, 0,
-            0, 0, 0, 0, 0, 0, 0, 0}
-           }
-          }
-         }
+	{
+	 0x03,
+	 0x01,
+	 0x02c0,
+	 0,
+	 0x0300,
+	 0x00a0,
+	{
+	{
+	   {0x04, 0xff},
+	    0x00345201,
+	    0x3201,
+	   {0x01672543, 0x45361207, 0x45632107, 0x60715234},
+	   {0x08, 0x08, 0x08, 0x08},
+	   WDQLVL_PAT,
+	   {0, 0, 0, 0, 0, 0, 0, 0,
+	    0, 0},
+	   {0, 0, 0, 0},
+	   {0, 0, 0, 0, 0, 0, 0, 0,
+	    0, 0, 0, 0, 0, 0, 0, 0,
+	    0, 0, 0, 0, 0, 0, 0, 0,
+	    0, 0, 0, 0, 0, 0, 0, 0},
+	   {0, 0, 0, 0},
+	   {0, 0, 0, 0, 0, 0, 0, 0,
+	    0, 0, 0, 0, 0, 0, 0, 0,
+	    0, 0, 0, 0, 0, 0, 0, 0,
+	    0, 0, 0, 0, 0, 0, 0, 0}
+	   },
+	{
+	   {0x04, 0xff},
+	    0x00302154,
+	    0x2310,
+	   {0x01672543, 0x45361207, 0x45632107, 0x60715234},
+	   {0x08, 0x08, 0x08, 0x08},
+	   WDQLVL_PAT,
+	   {0, 0, 0, 0, 0, 0, 0, 0,
+	    0, 0},
+	   {0, 0, 0, 0},
+	   {0, 0, 0, 0, 0, 0, 0, 0,
+	    0, 0, 0, 0, 0, 0, 0, 0,
+	    0, 0, 0, 0, 0, 0, 0, 0,
+	    0, 0, 0, 0, 0, 0, 0, 0},
+	   {0, 0, 0, 0},
+	   {0, 0, 0, 0, 0, 0, 0, 0,
+	    0, 0, 0, 0, 0, 0, 0, 0,
+	    0, 0, 0, 0, 0, 0, 0, 0,
+	    0, 0, 0, 0, 0, 0, 0, 0}
+	}
+	}
+	}
 };
 
-void boardcnf_get_brd_clk(uint32_t brd, uint32_t * clk, uint32_t * div)
+void boardcnf_get_brd_clk(uint32_t brd, uint32_t *clk, uint32_t *div)
 {
 	uint32_t md;
 
-	if ((Prr_Product == PRR_PRODUCT_H3) && (Prr_Cut == PRR_PRODUCT_10)) {
+	if ((prr_product == PRR_PRODUCT_H3) && (prr_cut == PRR_PRODUCT_10)) {
 		*clk = 50;
 		*div = 3;
 	} else {
@@ -1560,7 +1567,7 @@ void boardcnf_get_brd_clk(uint32_t brd, uint32_t * clk, uint32_t * div)
 	(void)brd;
 }
 
-void boardcnf_get_ddr_mbps(uint32_t brd, uint32_t * mbps, uint32_t * div)
+void boardcnf_get_ddr_mbps(uint32_t brd, uint32_t *mbps, uint32_t *div)
 {
 	uint32_t md;
 
@@ -1599,7 +1606,7 @@ void boardcnf_get_ddr_mbps(uint32_t brd, uint32_t * mbps, uint32_t * div)
 #define M3_SAMPLE_SS_E28        0xB866CC10, 0x3C231421
 #define M3_SAMPLE_SS_E32        0xB866CC10, 0x3C241421
 
-static const uint32_t TermcodeBySample[20][3] = {
+static const uint32_t termcode_by_sample[20][3] = {
 	{M3_SAMPLE_TT_A84, 0x000158D5},
 	{M3_SAMPLE_TT_A85, 0x00015955},
 	{M3_SAMPLE_TT_A86, 0x00015955},
@@ -1616,14 +1623,13 @@ static const uint32_t TermcodeBySample[20][3] = {
 /*
  * SAMPLE board detect function
  */
-#define PFC_PMMR   	0xE6060000U
+#define PFC_PMMR	0xE6060000U
 #define PFC_PUEN5	0xE6060414U
 #define PFC_PUEN6	0xE6060418U
 #define PFC_PUD5	0xE6060454U
 #define PFC_PUD6	0xE6060458U
 #define GPIO_INDT5	0xE605500CU
-#define GPIO_INDT6	0xE605540CU
-#define GPIO_GPSR6 	0xE6060118U
+#define GPIO_GPSR6	0xE6060118U
 
 #if (RCAR_GEN3_ULCB == 0)
 static void pfc_write_and_poll(uint32_t a, uint32_t v)
@@ -1631,7 +1637,8 @@ static void pfc_write_and_poll(uint32_t a, uint32_t v)
 	mmio_write_32(PFC_PMMR, ~v);
 	v = ~mmio_read_32(PFC_PMMR);
 	mmio_write_32(a, v);
-	while (v != mmio_read_32(a)) ;
+	while (v != mmio_read_32(a))
+		;
 	dsb_sev();
 }
 #endif
@@ -1689,10 +1696,10 @@ static uint32_t opencheck_SSI_WS6(void)
 	if (down == up) {
 		/* Same = Connect */
 		return 0;
-	} else {
-		/* Diff = Open */
-		return 1;
 	}
+
+	/* Diff = Open */
+	return 1;
 }
 
 #endif
@@ -1700,10 +1707,10 @@ static uint32_t opencheck_SSI_WS6(void)
 static uint32_t _board_judge(void)
 {
 	uint32_t brd;
-#if (RCAR_GEN3_ULCB==1)
+#if (RCAR_GEN3_ULCB == 1)
 	/* Starter Kit */
-	if (Prr_Product == PRR_PRODUCT_H3) {
-		if (Prr_Cut <= PRR_PRODUCT_11) {
+	if (prr_product == PRR_PRODUCT_H3) {
+		if (prr_cut <= PRR_PRODUCT_11) {
 			/* RENESAS Starter Kit(H3 Ver.1.x/SIP) board */
 			brd = 2;
 		} else {
@@ -1714,7 +1721,7 @@ static uint32_t _board_judge(void)
 			brd = 8;
 #endif
 		}
-	} else if (Prr_Product == PRR_PRODUCT_M3) {
+	} else if (prr_product == PRR_PRODUCT_M3) {
 		/* RENESAS Starter Kit(M3-W/SIP 8Gbit 1rank) board */
 		brd = 3;
 	} else {
@@ -1726,33 +1733,33 @@ static uint32_t _board_judge(void)
 
 	usb2_ovc_open = opencheck_SSI_WS6();
 
-	/* RENESAS Eva-borad */
+	/* RENESAS Eva-board */
 	brd = 99;
-	if (Prr_Product == PRR_PRODUCT_V3H) {
+	if (prr_product == PRR_PRODUCT_V3H) {
 		/* RENESAS Condor board */
 		brd = 12;
 	} else if (usb2_ovc_open) {
-		if (Prr_Product == PRR_PRODUCT_M3N) {
+		if (prr_product == PRR_PRODUCT_M3N) {
 			/* RENESAS Kriek board with M3-N */
 			brd = 10;
-		} else if (Prr_Product == PRR_PRODUCT_M3) {
+		} else if (prr_product == PRR_PRODUCT_M3) {
 			/* RENESAS Kriek board with M3-W */
 			brd = 1;
-		} else if ((Prr_Product == PRR_PRODUCT_H3)
-			   && (Prr_Cut<=PRR_PRODUCT_11)) {
+		} else if ((prr_product == PRR_PRODUCT_H3) &&
+			   (prr_cut <= PRR_PRODUCT_11)) {
 			/* RENESAS Kriek board with PM3 */
 			brd = 13;
-		} else if ((Prr_Product == PRR_PRODUCT_H3)
-			   && (Prr_Cut > PRR_PRODUCT_20)) {
+		} else if ((prr_product == PRR_PRODUCT_H3) &&
+			   (prr_cut > PRR_PRODUCT_20)) {
 			/* RENESAS Kriek board with H3N */
 			brd = 15;
 		}
 	} else {
-		if (Prr_Product == PRR_PRODUCT_H3) {
-			if (Prr_Cut <= PRR_PRODUCT_11) {
+		if (prr_product == PRR_PRODUCT_H3) {
+			if (prr_cut <= PRR_PRODUCT_11) {
 				/* RENESAS SALVATOR-X (H3 Ver.1.x/SIP) */
 				brd = 2;
-			} else if (Prr_Cut < PRR_PRODUCT_30) {
+			} else if (prr_cut < PRR_PRODUCT_30) {
 				/* RENESAS SALVATOR-X (H3 Ver.2.0/SIP) */
 				brd = 7;	//  8Gbit/1rank
 			} else {
@@ -1763,16 +1770,19 @@ static uint32_t _board_judge(void)
 				brd = 8;
 #endif
 			}
-		} else if (Prr_Product == PRR_PRODUCT_M3N) {
+		} else if (prr_product == PRR_PRODUCT_M3N) {
 			/* RENESAS SALVATOR-X (M3-N/SIP) */
 			brd = 11;
-		} else if ((Prr_Product == PRR_PRODUCT_M3) && (Prr_Cut <= PRR_PRODUCT_20)) {
+		} else if ((prr_product == PRR_PRODUCT_M3) &&
+			   (prr_cut <= PRR_PRODUCT_20)) {
 			/* RENESAS SALVATOR-X (M3-W/SIP) */
 			brd = 0;
-		} else if ((Prr_Product == PRR_PRODUCT_M3) && (Prr_Cut < PRR_PRODUCT_30)) {
+		} else if ((prr_product == PRR_PRODUCT_M3) &&
+			   (prr_cut < PRR_PRODUCT_30)) {
 			/* RENESAS SALVATOR-X (M3-W Ver.1.x/SIP) */
 			brd = 19;
-		} else if ((Prr_Product == PRR_PRODUCT_M3) && (Prr_Cut >= PRR_PRODUCT_30)) {
+		} else if ((prr_product == PRR_PRODUCT_M3) &&
+			   (prr_cut >= PRR_PRODUCT_30)) {
 			/* RENESAS SALVATOR-X (M3-W ver.3.0/SIP) */
 			brd = 18;
 		}
diff --git a/drivers/renesas/rcar/ddr/ddr_b/boot_init_dram_regdef.h b/drivers/renesas/rcar/ddr/ddr_b/boot_init_dram_regdef.h
new file mode 100644
index 000000000..5047e5cc2
--- /dev/null
+++ b/drivers/renesas/rcar/ddr/ddr_b/boot_init_dram_regdef.h
@@ -0,0 +1,95 @@
+/*
+ * Copyright (c) 2015-2019, Renesas Electronics Corporation.
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#define RCAR_DDR_VERSION	"rev.0.37"
+#define DRAM_CH_CNT		0x04
+#define SLICE_CNT		0x04
+#define CS_CNT			0x02
+
+/* order : CS0A, CS0B, CS1A, CS1B */
+#define CSAB_CNT		(CS_CNT * 2)
+
+/* order : CH0A, CH0B, CH1A, CH1B, CH2A, CH2B, CH3A, CH3B */
+#define CHAB_CNT		(DRAM_CH_CNT * 2)
+
+/* pll setting */
+#define CLK_DIV(a, diva, b, divb) (((a) * (divb)) / ((b) * (diva)))
+#define CLK_MUL(a, diva, b, divb) (((a) * (b)) / ((diva) * (divb)))
+
+/* for ddr deisity setting */
+#define DBMEMCONF_REG(d3, row, bank, col, dw)	\
+	((d3) << 30 | ((row) << 24) | ((bank) << 16) | ((col) << 8) | (dw))
+
+#define DBMEMCONF_REGD(density)		\
+	(DBMEMCONF_REG((density) % 2, ((density) + 1) / \
+	2 + (29 - 3 - 10 - 2), 3, 10, 2))
+
+#define DBMEMCONF_VAL(ch, cs) (DBMEMCONF_REGD(DBMEMCONF_DENS(ch, cs)))
+
+/* refresh mode */
+#define DBSC_REFINTS		(0x0)
+
+/* system registers */
+#define CPG_FRQCRB		(CPG_BASE + 0x0004U)
+
+#define CPG_PLLECR		(CPG_BASE + 0x00D0U)
+#define CPG_MSTPSR5		(CPG_BASE + 0x003CU)
+#define CPG_SRCR4		(CPG_BASE + 0x00BCU)
+#define CPG_PLL3CR		(CPG_BASE + 0x00DCU)
+#define CPG_ZB3CKCR		(CPG_BASE + 0x0380U)
+#define CPG_FRQCRD		(CPG_BASE + 0x00E4U)
+#define CPG_SMSTPCR5		(CPG_BASE + 0x0144U)
+#define CPG_CPGWPR		(CPG_BASE + 0x0900U)
+#define CPG_SRSTCLR4		(CPG_BASE + 0x0950U)
+
+#define CPG_FRQCRB_KICK_BIT	BIT(31)
+#define CPG_PLLECR_PLL3E_BIT	BIT(3)
+#define CPG_PLLECR_PLL3ST_BIT	BIT(11)
+#define CPG_ZB3CKCR_ZB3ST_BIT	BIT(11)
+
+#define RST_BASE		(0xE6160000U)
+#define RST_MODEMR		(RST_BASE + 0x0060U)
+
+#define LIFEC_CHIPID(x)		(0xE6110040U + 0x04U * (x))
+
+/* DBSC registers */
+#include "../ddr_regs.h"
+
+#define DBSC_DBMONCONF4		0xE6793010U
+
+#define DBSC_PLL_LOCK(ch)	(0xE6794054U + 0x100U * (ch))
+#define DBSC_PLL_LOCK_0		0xE6794054U
+#define DBSC_PLL_LOCK_1		0xE6794154U
+#define DBSC_PLL_LOCK_2		0xE6794254U
+#define DBSC_PLL_LOCK_3		0xE6794354U
+
+/* STAT registers */
+#define MSTAT_SL_INIT		0xE67E8000U
+#define MSTAT_REF_ARS		0xE67E8004U
+#define MSTATQ_STATQC		0xE67E8008U
+#define MSTATQ_WTENABLE		0xE67E8030U
+#define MSTATQ_WTREFRESH	0xE67E8034U
+#define MSTATQ_WTSETTING0	0xE67E8038U
+#define MSTATQ_WTSETTING1	0xE67E803CU
+
+#define QOS_BASE1		(0xE67F0000U)
+#define QOSCTRL_RAS		(QOS_BASE1 + 0x0000U)
+#define QOSCTRL_FIXTH		(QOS_BASE1 + 0x0004U)
+#define QOSCTRL_RAEN		(QOS_BASE1 + 0x0018U)
+#define QOSCTRL_REGGD		(QOS_BASE1 + 0x0020U)
+#define QOSCTRL_DANN		(QOS_BASE1 + 0x0030U)
+#define QOSCTRL_DANT		(QOS_BASE1 + 0x0038U)
+#define QOSCTRL_EC		(QOS_BASE1 + 0x003CU)
+#define QOSCTRL_EMS		(QOS_BASE1 + 0x0040U)
+#define QOSCTRL_INSFC		(QOS_BASE1 + 0x0050U)
+#define QOSCTRL_BERR		(QOS_BASE1 + 0x0054U)
+#define QOSCTRL_RACNT0		(QOS_BASE1 + 0x0080U)
+#define QOSCTRL_STATGEN0	(QOS_BASE1 + 0x0088U)
+
+/* other module */
+#define THS1_THCTR		0xE6198020U
+#define THS1_TEMP		0xE6198028U
diff --git a/drivers/staging/renesas/rcar/ddr/ddr_b/ddr_b.mk b/drivers/renesas/rcar/ddr/ddr_b/ddr_b.mk
index 875f95339..2bcc2922d 100644
--- a/drivers/staging/renesas/rcar/ddr/ddr_b/ddr_b.mk
+++ b/drivers/renesas/rcar/ddr/ddr_b/ddr_b.mk
@@ -4,4 +4,4 @@
 # SPDX-License-Identifier: BSD-3-Clause
 #
 
-BL2_SOURCES += drivers/staging/renesas/rcar/ddr/ddr_b/boot_init_dram.c
+BL2_SOURCES += drivers/renesas/rcar/ddr/ddr_b/boot_init_dram.c
diff --git a/drivers/staging/renesas/rcar/ddr/ddr_b/ddr_regdef.h b/drivers/renesas/rcar/ddr/ddr_b/ddr_regdef.h
index bad1de90f..adf8dab18 100644
--- a/drivers/staging/renesas/rcar/ddr/ddr_b/ddr_regdef.h
+++ b/drivers/renesas/rcar/ddr/ddr_b/ddr_regdef.h
@@ -1,5 +1,6 @@
 /*
- * Copyright (c) 2018-2019, Renesas Electronics Corporation. All rights reserved.
+ * Copyright (c) 2018-2019, Renesas Electronics Corporation.
+ * All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -1178,9 +1179,9 @@
 #define _reg_PI_TSDO_F1                                    0x00000493U
 #define _reg_PI_TSDO_F2                                    0x00000494U
 
-#define DDR_REGDEF_ADR(regdef) ((regdef)&0xffff)
-#define DDR_REGDEF_LEN(regdef) (((regdef)>>16)&0xff)
-#define DDR_REGDEF_LSB(regdef) (((regdef)>>24)&0xff)
+#define DDR_REGDEF_ADR(regdef) ((regdef) & 0xffff)
+#define DDR_REGDEF_LEN(regdef) (((regdef) >> 16) & 0xff)
+#define DDR_REGDEF_LSB(regdef) (((regdef) >> 24) & 0xff)
 
 static const uint32_t DDR_REGDEF_TBL[4][1173] = {
 	{
@@ -5882,5 +5883,5 @@ static const uint32_t DDR_REGDEF_TBL[4][1173] = {
 /*0492*/ 0x0808031dU,
 /*0493*/ 0x1008031dU,
 /*0494*/ 0x1808031dU,
-	 }
+	}
 };
diff --git a/drivers/renesas/rcar/ddr/ddr_b/init_dram_tbl_h3.h b/drivers/renesas/rcar/ddr/ddr_b/init_dram_tbl_h3.h
new file mode 100644
index 000000000..357f8bad0
--- /dev/null
+++ b/drivers/renesas/rcar/ddr/ddr_b/init_dram_tbl_h3.h
@@ -0,0 +1,441 @@
+/*
+ * Copyright (c) 2015-2019, Renesas Electronics Corporation.
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#define DDR_PHY_SLICE_REGSET_OFS_H3  0x0400
+#define DDR_PHY_ADR_V_REGSET_OFS_H3  0x0600
+#define DDR_PHY_ADR_I_REGSET_OFS_H3  0x0680
+#define DDR_PHY_ADR_G_REGSET_OFS_H3  0x0700
+#define DDR_PI_REGSET_OFS_H3         0x0200
+
+#define DDR_PHY_SLICE_REGSET_SIZE_H3 0x80
+#define DDR_PHY_ADR_V_REGSET_SIZE_H3 0x80
+#define DDR_PHY_ADR_I_REGSET_SIZE_H3 0x80
+#define DDR_PHY_ADR_G_REGSET_SIZE_H3 0x80
+#define DDR_PI_REGSET_SIZE_H3        0x100
+
+#define DDR_PHY_SLICE_REGSET_NUM_H3  88
+#define DDR_PHY_ADR_V_REGSET_NUM_H3  37
+#define DDR_PHY_ADR_I_REGSET_NUM_H3  37
+#define DDR_PHY_ADR_G_REGSET_NUM_H3  59
+#define DDR_PI_REGSET_NUM_H3         181
+
+static const uint32_t DDR_PHY_SLICE_REGSET_H3[DDR_PHY_SLICE_REGSET_NUM_H3] = {
+	/*0400*/ 0x000004f0,
+	/*0401*/ 0x00000000,
+	/*0402*/ 0x00000000,
+	/*0403*/ 0x00000100,
+	/*0404*/ 0x01003c0c,
+	/*0405*/ 0x02003c0c,
+	/*0406*/ 0x00010300,
+	/*0407*/ 0x04000100,
+	/*0408*/ 0x00000300,
+	/*0409*/ 0x000700c0,
+	/*040a*/ 0x00b00201,
+	/*040b*/ 0x00000020,
+	/*040c*/ 0x00000000,
+	/*040d*/ 0x00000000,
+	/*040e*/ 0x00000000,
+	/*040f*/ 0x00000000,
+	/*0410*/ 0x00000000,
+	/*0411*/ 0x00000000,
+	/*0412*/ 0x00000000,
+	/*0413*/ 0x09000000,
+	/*0414*/ 0x04080000,
+	/*0415*/ 0x04080400,
+	/*0416*/ 0x00000000,
+	/*0417*/ 0x32103210,
+	/*0418*/ 0x00800708,
+	/*0419*/ 0x000f000c,
+	/*041a*/ 0x00000100,
+	/*041b*/ 0x55aa55aa,
+	/*041c*/ 0x33cc33cc,
+	/*041d*/ 0x0ff00ff0,
+	/*041e*/ 0x0f0ff0f0,
+	/*041f*/ 0x00008e38,
+	/*0420*/ 0x76543210,
+	/*0421*/ 0x00000001,
+	/*0422*/ 0x00000000,
+	/*0423*/ 0x00000000,
+	/*0424*/ 0x00000000,
+	/*0425*/ 0x00000000,
+	/*0426*/ 0x00000000,
+	/*0427*/ 0x00000000,
+	/*0428*/ 0x00000000,
+	/*0429*/ 0x00000000,
+	/*042a*/ 0x00000000,
+	/*042b*/ 0x00000000,
+	/*042c*/ 0x00000000,
+	/*042d*/ 0x00000000,
+	/*042e*/ 0x00000000,
+	/*042f*/ 0x00000000,
+	/*0430*/ 0x00000000,
+	/*0431*/ 0x00000000,
+	/*0432*/ 0x00000000,
+	/*0433*/ 0x00200000,
+	/*0434*/ 0x08200820,
+	/*0435*/ 0x08200820,
+	/*0436*/ 0x08200820,
+	/*0437*/ 0x08200820,
+	/*0438*/ 0x08200820,
+	/*0439*/ 0x00000820,
+	/*043a*/ 0x03000300,
+	/*043b*/ 0x03000300,
+	/*043c*/ 0x03000300,
+	/*043d*/ 0x03000300,
+	/*043e*/ 0x00000300,
+	/*043f*/ 0x00000000,
+	/*0440*/ 0x00000000,
+	/*0441*/ 0x00000000,
+	/*0442*/ 0x00000000,
+	/*0443*/ 0x00a000a0,
+	/*0444*/ 0x00a000a0,
+	/*0445*/ 0x00a000a0,
+	/*0446*/ 0x00a000a0,
+	/*0447*/ 0x00a000a0,
+	/*0448*/ 0x00a000a0,
+	/*0449*/ 0x00a000a0,
+	/*044a*/ 0x00a000a0,
+	/*044b*/ 0x00a000a0,
+	/*044c*/ 0x01040109,
+	/*044d*/ 0x00000200,
+	/*044e*/ 0x01000000,
+	/*044f*/ 0x00000200,
+	/*0450*/ 0x4041a151,
+	/*0451*/ 0xc00141a0,
+	/*0452*/ 0x0e0100c0,
+	/*0453*/ 0x0010000c,
+	/*0454*/ 0x0c064208,
+	/*0455*/ 0x000f0c18,
+	/*0456*/ 0x00e00140,
+	/*0457*/ 0x00000c20
+};
+
+static const uint32_t DDR_PHY_ADR_V_REGSET_H3[DDR_PHY_ADR_V_REGSET_NUM_H3] = {
+	/*0600*/ 0x00000000,
+	/*0601*/ 0x00000000,
+	/*0602*/ 0x00000000,
+	/*0603*/ 0x00000000,
+	/*0604*/ 0x00000000,
+	/*0605*/ 0x00000000,
+	/*0606*/ 0x00000002,
+	/*0607*/ 0x00000000,
+	/*0608*/ 0x00000000,
+	/*0609*/ 0x00000000,
+	/*060a*/ 0x00400320,
+	/*060b*/ 0x00000040,
+	/*060c*/ 0x00dcba98,
+	/*060d*/ 0x00000000,
+	/*060e*/ 0x00dcba98,
+	/*060f*/ 0x01000000,
+	/*0610*/ 0x00020003,
+	/*0611*/ 0x00000000,
+	/*0612*/ 0x00000000,
+	/*0613*/ 0x00000000,
+	/*0614*/ 0x00002a01,
+	/*0615*/ 0x00000015,
+	/*0616*/ 0x00000015,
+	/*0617*/ 0x0000002a,
+	/*0618*/ 0x00000033,
+	/*0619*/ 0x0000000c,
+	/*061a*/ 0x0000000c,
+	/*061b*/ 0x00000033,
+	/*061c*/ 0x00418820,
+	/*061d*/ 0x003f0000,
+	/*061e*/ 0x0000003f,
+	/*061f*/ 0x0002006e,
+	/*0620*/ 0x02000200,
+	/*0621*/ 0x02000200,
+	/*0622*/ 0x00000200,
+	/*0623*/ 0x42080010,
+	/*0624*/ 0x00000003
+};
+
+static const uint32_t DDR_PHY_ADR_I_REGSET_H3[DDR_PHY_ADR_I_REGSET_NUM_H3] = {
+	/*0680*/ 0x04040404,
+	/*0681*/ 0x00000404,
+	/*0682*/ 0x00000000,
+	/*0683*/ 0x00000000,
+	/*0684*/ 0x00000000,
+	/*0685*/ 0x00000000,
+	/*0686*/ 0x00000002,
+	/*0687*/ 0x00000000,
+	/*0688*/ 0x00000000,
+	/*0689*/ 0x00000000,
+	/*068a*/ 0x00400320,
+	/*068b*/ 0x00000040,
+	/*068c*/ 0x00000000,
+	/*068d*/ 0x00000000,
+	/*068e*/ 0x00000000,
+	/*068f*/ 0x01000000,
+	/*0690*/ 0x00020003,
+	/*0691*/ 0x00000000,
+	/*0692*/ 0x00000000,
+	/*0693*/ 0x00000000,
+	/*0694*/ 0x00002a01,
+	/*0695*/ 0x00000015,
+	/*0696*/ 0x00000015,
+	/*0697*/ 0x0000002a,
+	/*0698*/ 0x00000033,
+	/*0699*/ 0x0000000c,
+	/*069a*/ 0x0000000c,
+	/*069b*/ 0x00000033,
+	/*069c*/ 0x00000000,
+	/*069d*/ 0x00000000,
+	/*069e*/ 0x00000000,
+	/*069f*/ 0x0002006e,
+	/*06a0*/ 0x02000200,
+	/*06a1*/ 0x02000200,
+	/*06a2*/ 0x00000200,
+	/*06a3*/ 0x42080010,
+	/*06a4*/ 0x00000003
+};
+
+static const uint32_t DDR_PHY_ADR_G_REGSET_H3[DDR_PHY_ADR_G_REGSET_NUM_H3] = {
+	/*0700*/ 0x00000001,
+	/*0701*/ 0x00000000,
+	/*0702*/ 0x00000005,
+	/*0703*/ 0x04000f00,
+	/*0704*/ 0x00020080,
+	/*0705*/ 0x00020055,
+	/*0706*/ 0x00000000,
+	/*0707*/ 0x00000000,
+	/*0708*/ 0x00000000,
+	/*0709*/ 0x00000050,
+	/*070a*/ 0x00000000,
+	/*070b*/ 0x01010100,
+	/*070c*/ 0x00000200,
+	/*070d*/ 0x00001102,
+	/*070e*/ 0x00000000,
+	/*070f*/ 0x000f1f00,
+	/*0710*/ 0x0f1f0f1f,
+	/*0711*/ 0x0f1f0f1f,
+	/*0712*/ 0x00020003,
+	/*0713*/ 0x02000200,
+	/*0714*/ 0x00000200,
+	/*0715*/ 0x00001102,
+	/*0716*/ 0x00000064,
+	/*0717*/ 0x00000000,
+	/*0718*/ 0x00000000,
+	/*0719*/ 0x00000502,
+	/*071a*/ 0x027f6e00,
+	/*071b*/ 0x007f007f,
+	/*071c*/ 0x00007f3c,
+	/*071d*/ 0x00047f6e,
+	/*071e*/ 0x0003154f,
+	/*071f*/ 0x0001154f,
+	/*0720*/ 0x0001154f,
+	/*0721*/ 0x0001154f,
+	/*0722*/ 0x0001154f,
+	/*0723*/ 0x00003fee,
+	/*0724*/ 0x0001154f,
+	/*0725*/ 0x00003fee,
+	/*0726*/ 0x0001154f,
+	/*0727*/ 0x00007f3c,
+	/*0728*/ 0x0001154f,
+	/*0729*/ 0x00000000,
+	/*072a*/ 0x00000000,
+	/*072b*/ 0x00000000,
+	/*072c*/ 0x65000000,
+	/*072d*/ 0x00000000,
+	/*072e*/ 0x00000000,
+	/*072f*/ 0x00000201,
+	/*0730*/ 0x00000000,
+	/*0731*/ 0x00000000,
+	/*0732*/ 0x00000000,
+	/*0733*/ 0x00000000,
+	/*0734*/ 0x00000000,
+	/*0735*/ 0x00000000,
+	/*0736*/ 0x00000000,
+	/*0737*/ 0x00000000,
+	/*0738*/ 0x00000000,
+	/*0739*/ 0x00000000,
+	/*073a*/ 0x00000000
+};
+
+static const uint32_t DDR_PI_REGSET_H3[DDR_PI_REGSET_NUM_H3] = {
+	/*0200*/ 0x00000b00,
+	/*0201*/ 0x00000100,
+	/*0202*/ 0x00000000,
+	/*0203*/ 0x0000ffff,
+	/*0204*/ 0x00000000,
+	/*0205*/ 0x0000ffff,
+	/*0206*/ 0x00000000,
+	/*0207*/ 0x304cffff,
+	/*0208*/ 0x00000200,
+	/*0209*/ 0x00000200,
+	/*020a*/ 0x00000200,
+	/*020b*/ 0x00000200,
+	/*020c*/ 0x0000304c,
+	/*020d*/ 0x00000200,
+	/*020e*/ 0x00000200,
+	/*020f*/ 0x00000200,
+	/*0210*/ 0x00000200,
+	/*0211*/ 0x0000304c,
+	/*0212*/ 0x00000200,
+	/*0213*/ 0x00000200,
+	/*0214*/ 0x00000200,
+	/*0215*/ 0x00000200,
+	/*0216*/ 0x00010000,
+	/*0217*/ 0x00000003,
+	/*0218*/ 0x01000001,
+	/*0219*/ 0x00000000,
+	/*021a*/ 0x00000000,
+	/*021b*/ 0x00000000,
+	/*021c*/ 0x00000000,
+	/*021d*/ 0x00000000,
+	/*021e*/ 0x00000000,
+	/*021f*/ 0x00000000,
+	/*0220*/ 0x00000000,
+	/*0221*/ 0x00000000,
+	/*0222*/ 0x00000000,
+	/*0223*/ 0x00000000,
+	/*0224*/ 0x00000000,
+	/*0225*/ 0x00000000,
+	/*0226*/ 0x00000000,
+	/*0227*/ 0x00000000,
+	/*0228*/ 0x00000000,
+	/*0229*/ 0x0f000101,
+	/*022a*/ 0x08492d25,
+	/*022b*/ 0x500e0c04,
+	/*022c*/ 0x0002500e,
+	/*022d*/ 0x00460003,
+	/*022e*/ 0x182600cf,
+	/*022f*/ 0x182600cf,
+	/*0230*/ 0x00000005,
+	/*0231*/ 0x00000000,
+	/*0232*/ 0x00000000,
+	/*0233*/ 0x00000000,
+	/*0234*/ 0x00000000,
+	/*0235*/ 0x00000000,
+	/*0236*/ 0x00000000,
+	/*0237*/ 0x00000000,
+	/*0238*/ 0x01000000,
+	/*0239*/ 0x00040404,
+	/*023a*/ 0x01280a00,
+	/*023b*/ 0x00000000,
+	/*023c*/ 0x000f0000,
+	/*023d*/ 0x00001803,
+	/*023e*/ 0x00000000,
+	/*023f*/ 0x00000000,
+	/*0240*/ 0x00060002,
+	/*0241*/ 0x00010001,
+	/*0242*/ 0x01000101,
+	/*0243*/ 0x04020201,
+	/*0244*/ 0x00080804,
+	/*0245*/ 0x00000000,
+	/*0246*/ 0x08030000,
+	/*0247*/ 0x15150408,
+	/*0248*/ 0x00000000,
+	/*0249*/ 0x00000000,
+	/*024a*/ 0x00000000,
+	/*024b*/ 0x001e0f0f,
+	/*024c*/ 0x00000000,
+	/*024d*/ 0x01000300,
+	/*024e*/ 0x00000000,
+	/*024f*/ 0x00000000,
+	/*0250*/ 0x01000000,
+	/*0251*/ 0x00010101,
+	/*0252*/ 0x000e0e0e,
+	/*0253*/ 0x000c0c0c,
+	/*0254*/ 0x02060601,
+	/*0255*/ 0x00000000,
+	/*0256*/ 0x00000003,
+	/*0257*/ 0x00181703,
+	/*0258*/ 0x00280006,
+	/*0259*/ 0x00280016,
+	/*025a*/ 0x00000016,
+	/*025b*/ 0x00000000,
+	/*025c*/ 0x00000000,
+	/*025d*/ 0x00000000,
+	/*025e*/ 0x140a0000,
+	/*025f*/ 0x0005010a,
+	/*0260*/ 0x03018d03,
+	/*0261*/ 0x000a018d,
+	/*0262*/ 0x00060100,
+	/*0263*/ 0x01000006,
+	/*0264*/ 0x018e018e,
+	/*0265*/ 0x018e0100,
+	/*0266*/ 0x1111018e,
+	/*0267*/ 0x10010204,
+	/*0268*/ 0x09090650,
+	/*0269*/ 0x20110202,
+	/*026a*/ 0x00201000,
+	/*026b*/ 0x00201000,
+	/*026c*/ 0x04041000,
+	/*026d*/ 0x18020100,
+	/*026e*/ 0x00010118,
+	/*026f*/ 0x004b004a,
+	/*0270*/ 0x050f0000,
+	/*0271*/ 0x0c01021e,
+	/*0272*/ 0x34000000,
+	/*0273*/ 0x00000000,
+	/*0274*/ 0x00000000,
+	/*0275*/ 0x00000000,
+	/*0276*/ 0x312ed400,
+	/*0277*/ 0xd4111132,
+	/*0278*/ 0x1132312e,
+	/*0279*/ 0x312ed411,
+	/*027a*/ 0x00111132,
+	/*027b*/ 0x32312ed4,
+	/*027c*/ 0x2ed41111,
+	/*027d*/ 0x11113231,
+	/*027e*/ 0x32312ed4,
+	/*027f*/ 0xd4001111,
+	/*0280*/ 0x1132312e,
+	/*0281*/ 0x312ed411,
+	/*0282*/ 0xd4111132,
+	/*0283*/ 0x1132312e,
+	/*0284*/ 0x2ed40011,
+	/*0285*/ 0x11113231,
+	/*0286*/ 0x32312ed4,
+	/*0287*/ 0x2ed41111,
+	/*0288*/ 0x11113231,
+	/*0289*/ 0x00020000,
+	/*028a*/ 0x018d018d,
+	/*028b*/ 0x0c08018d,
+	/*028c*/ 0x1f121d22,
+	/*028d*/ 0x4301b344,
+	/*028e*/ 0x10172006,
+	/*028f*/ 0x121d220c,
+	/*0290*/ 0x01b3441f,
+	/*0291*/ 0x17200643,
+	/*0292*/ 0x1d220c10,
+	/*0293*/ 0x00001f12,
+	/*0294*/ 0x4301b344,
+	/*0295*/ 0x10172006,
+	/*0296*/ 0x00020002,
+	/*0297*/ 0x00020002,
+	/*0298*/ 0x00020002,
+	/*0299*/ 0x00020002,
+	/*029a*/ 0x00020002,
+	/*029b*/ 0x00000000,
+	/*029c*/ 0x00000000,
+	/*029d*/ 0x00000000,
+	/*029e*/ 0x00000000,
+	/*029f*/ 0x00000000,
+	/*02a0*/ 0x00000000,
+	/*02a1*/ 0x00000000,
+	/*02a2*/ 0x00000000,
+	/*02a3*/ 0x00000000,
+	/*02a4*/ 0x00000000,
+	/*02a5*/ 0x00000000,
+	/*02a6*/ 0x00000000,
+	/*02a7*/ 0x01000400,
+	/*02a8*/ 0x00304c00,
+	/*02a9*/ 0x0001e2f8,
+	/*02aa*/ 0x0000304c,
+	/*02ab*/ 0x0001e2f8,
+	/*02ac*/ 0x0000304c,
+	/*02ad*/ 0x0001e2f8,
+	/*02ae*/ 0x08000000,
+	/*02af*/ 0x00000100,
+	/*02b0*/ 0x00000000,
+	/*02b1*/ 0x00000000,
+	/*02b2*/ 0x00000000,
+	/*02b3*/ 0x00000000,
+	/*02b4*/ 0x00000002
+};
diff --git a/drivers/renesas/rcar/ddr/ddr_b/init_dram_tbl_h3ver2.h b/drivers/renesas/rcar/ddr/ddr_b/init_dram_tbl_h3ver2.h
new file mode 100644
index 000000000..e5258af6c
--- /dev/null
+++ b/drivers/renesas/rcar/ddr/ddr_b/init_dram_tbl_h3ver2.h
@@ -0,0 +1,538 @@
+/*
+ * Copyright (c) 2015-2019, Renesas Electronics Corporation.
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#define DDR_PHY_SLICE_REGSET_OFS_H3VER2  0x0400
+#define DDR_PHY_ADR_V_REGSET_OFS_H3VER2  0x0600
+#define DDR_PHY_ADR_I_REGSET_OFS_H3VER2  0x0640
+#define DDR_PHY_ADR_G_REGSET_OFS_H3VER2  0x0680
+#define DDR_PI_REGSET_OFS_H3VER2         0x0200
+
+#define DDR_PHY_SLICE_REGSET_SIZE_H3VER2 0x80
+#define DDR_PHY_ADR_V_REGSET_SIZE_H3VER2 0x40
+#define DDR_PHY_ADR_I_REGSET_SIZE_H3VER2 0x40
+#define DDR_PHY_ADR_G_REGSET_SIZE_H3VER2 0x80
+#define DDR_PI_REGSET_SIZE_H3VER2        0x100
+
+#define DDR_PHY_SLICE_REGSET_NUM_H3VER2  97
+#define DDR_PHY_ADR_V_REGSET_NUM_H3VER2  37
+#define DDR_PHY_ADR_I_REGSET_NUM_H3VER2  37
+#define DDR_PHY_ADR_G_REGSET_NUM_H3VER2  79
+#define DDR_PI_REGSET_NUM_H3VER2         245
+
+static const uint32_t DDR_PHY_SLICE_REGSET_H3VER2
+	[DDR_PHY_SLICE_REGSET_NUM_H3VER2] = {
+	/*0400*/ 0x76543210,
+	/*0401*/ 0x0004f008,
+	/*0402*/ 0x00020133,
+	/*0403*/ 0x00000000,
+	/*0404*/ 0x00000000,
+	/*0405*/ 0x00010000,
+	/*0406*/ 0x016e6e0e,
+	/*0407*/ 0x026e6e0e,
+	/*0408*/ 0x00010300,
+	/*0409*/ 0x04000100,
+	/*040a*/ 0x01000000,
+	/*040b*/ 0x00000000,
+	/*040c*/ 0x00000000,
+	/*040d*/ 0x00000100,
+	/*040e*/ 0x001700c0,
+	/*040f*/ 0x020100b0,
+	/*0410*/ 0x00030020,
+	/*0411*/ 0x00000000,
+	/*0412*/ 0x00000000,
+	/*0413*/ 0x00000000,
+	/*0414*/ 0x00000000,
+	/*0415*/ 0x00000000,
+	/*0416*/ 0x00000000,
+	/*0417*/ 0x00000000,
+	/*0418*/ 0x09000000,
+	/*0419*/ 0x04080000,
+	/*041a*/ 0x04080400,
+	/*041b*/ 0x08000000,
+	/*041c*/ 0x0c008007,
+	/*041d*/ 0x00000f00,
+	/*041e*/ 0x00000100,
+	/*041f*/ 0x55aa55aa,
+	/*0420*/ 0x33cc33cc,
+	/*0421*/ 0x0ff00ff0,
+	/*0422*/ 0x0f0ff0f0,
+	/*0423*/ 0x00018e38,
+	/*0424*/ 0x00000000,
+	/*0425*/ 0x00000000,
+	/*0426*/ 0x00000000,
+	/*0427*/ 0x00000000,
+	/*0428*/ 0x00000000,
+	/*0429*/ 0x00000000,
+	/*042a*/ 0x00000000,
+	/*042b*/ 0x00000000,
+	/*042c*/ 0x00000000,
+	/*042d*/ 0x00000000,
+	/*042e*/ 0x00000000,
+	/*042f*/ 0x00000000,
+	/*0430*/ 0x00000000,
+	/*0431*/ 0x00000000,
+	/*0432*/ 0x00000000,
+	/*0433*/ 0x00000000,
+	/*0434*/ 0x00000000,
+	/*0435*/ 0x00000000,
+	/*0436*/ 0x00000000,
+	/*0437*/ 0x00000000,
+	/*0438*/ 0x00000104,
+	/*0439*/ 0x00082020,
+	/*043a*/ 0x08200820,
+	/*043b*/ 0x08200820,
+	/*043c*/ 0x08200820,
+	/*043d*/ 0x08200820,
+	/*043e*/ 0x08200820,
+	/*043f*/ 0x00000000,
+	/*0440*/ 0x00000000,
+	/*0441*/ 0x03000300,
+	/*0442*/ 0x03000300,
+	/*0443*/ 0x03000300,
+	/*0444*/ 0x03000300,
+	/*0445*/ 0x00000300,
+	/*0446*/ 0x00000000,
+	/*0447*/ 0x00000000,
+	/*0448*/ 0x00000000,
+	/*0449*/ 0x00000000,
+	/*044a*/ 0x00000000,
+	/*044b*/ 0x00a000a0,
+	/*044c*/ 0x00a000a0,
+	/*044d*/ 0x00a000a0,
+	/*044e*/ 0x00a000a0,
+	/*044f*/ 0x00a000a0,
+	/*0450*/ 0x00a000a0,
+	/*0451*/ 0x00a000a0,
+	/*0452*/ 0x00a000a0,
+	/*0453*/ 0x00a000a0,
+	/*0454*/ 0x01040109,
+	/*0455*/ 0x00000200,
+	/*0456*/ 0x01000000,
+	/*0457*/ 0x00000200,
+	/*0458*/ 0x00000004,
+	/*0459*/ 0x4041a151,
+	/*045a*/ 0xc00141a0,
+	/*045b*/ 0x0e0000c0,
+	/*045c*/ 0x0010000c,
+	/*045d*/ 0x063e4208,
+	/*045e*/ 0x0f0c180c,
+	/*045f*/ 0x00e00140,
+	/*0460*/ 0x00000c20
+};
+
+static const uint32_t
+	DDR_PHY_ADR_V_REGSET_H3VER2[DDR_PHY_ADR_V_REGSET_NUM_H3VER2] = {
+	/*0600*/ 0x00000000,
+	/*0601*/ 0x00000000,
+	/*0602*/ 0x00000000,
+	/*0603*/ 0x00000000,
+	/*0604*/ 0x00000000,
+	/*0605*/ 0x00000000,
+	/*0606*/ 0x00000000,
+	/*0607*/ 0x00010000,
+	/*0608*/ 0x00000200,
+	/*0609*/ 0x00000000,
+	/*060a*/ 0x00000000,
+	/*060b*/ 0x00000000,
+	/*060c*/ 0x00400320,
+	/*060d*/ 0x00000040,
+	/*060e*/ 0x00dcba98,
+	/*060f*/ 0x03000000,
+	/*0610*/ 0x00000200,
+	/*0611*/ 0x00000000,
+	/*0612*/ 0x00000000,
+	/*0613*/ 0x00000000,
+	/*0614*/ 0x0000002a,
+	/*0615*/ 0x00000015,
+	/*0616*/ 0x00000015,
+	/*0617*/ 0x0000002a,
+	/*0618*/ 0x00000033,
+	/*0619*/ 0x0000000c,
+	/*061a*/ 0x0000000c,
+	/*061b*/ 0x00000033,
+	/*061c*/ 0x00418820,
+	/*061d*/ 0x003f0000,
+	/*061e*/ 0x0000003f,
+	/*061f*/ 0x0002c06e,
+	/*0620*/ 0x02c002c0,
+	/*0621*/ 0x02c002c0,
+	/*0622*/ 0x000002c0,
+	/*0623*/ 0x42080010,
+	/*0624*/ 0x0000033e
+};
+
+static const uint32_t
+	DDR_PHY_ADR_I_REGSET_H3VER2[DDR_PHY_ADR_I_REGSET_NUM_H3VER2] = {
+	/*0640*/ 0x00000000,
+	/*0641*/ 0x00000000,
+	/*0642*/ 0x00000000,
+	/*0643*/ 0x00000000,
+	/*0644*/ 0x00000000,
+	/*0645*/ 0x00000000,
+	/*0646*/ 0x00000000,
+	/*0647*/ 0x00000000,
+	/*0648*/ 0x00000000,
+	/*0649*/ 0x00000000,
+	/*064a*/ 0x00000000,
+	/*064b*/ 0x00000000,
+	/*064c*/ 0x00000000,
+	/*064d*/ 0x00000000,
+	/*064e*/ 0x00000000,
+	/*064f*/ 0x00000000,
+	/*0650*/ 0x00000000,
+	/*0651*/ 0x00000000,
+	/*0652*/ 0x00000000,
+	/*0653*/ 0x00000000,
+	/*0654*/ 0x00000000,
+	/*0655*/ 0x00000000,
+	/*0656*/ 0x00000000,
+	/*0657*/ 0x00000000,
+	/*0658*/ 0x00000000,
+	/*0659*/ 0x00000000,
+	/*065a*/ 0x00000000,
+	/*065b*/ 0x00000000,
+	/*065c*/ 0x00000000,
+	/*065d*/ 0x00000000,
+	/*065e*/ 0x00000000,
+	/*065f*/ 0x00000000,
+	/*0660*/ 0x00000000,
+	/*0661*/ 0x00000000,
+	/*0662*/ 0x00000000,
+	/*0663*/ 0x00000000,
+	/*0664*/ 0x00000000
+};
+
+static const uint32_t
+	DDR_PHY_ADR_G_REGSET_H3VER2[DDR_PHY_ADR_G_REGSET_NUM_H3VER2] = {
+	/*0680*/ 0x00000000,
+	/*0681*/ 0x00000100,
+	/*0682*/ 0x00000000,
+	/*0683*/ 0x00050000,
+	/*0684*/ 0x0f000000,
+	/*0685*/ 0x00800400,
+	/*0686*/ 0x00020032,
+	/*0687*/ 0x00020055,
+	/*0688*/ 0x00000000,
+	/*0689*/ 0x00000000,
+	/*068a*/ 0x00000000,
+	/*068b*/ 0x00000050,
+	/*068c*/ 0x00000000,
+	/*068d*/ 0x01010100,
+	/*068e*/ 0x01000200,
+	/*068f*/ 0x00000000,
+	/*0690*/ 0x00010100,
+	/*0691*/ 0x00000000,
+	/*0692*/ 0x00000000,
+	/*0693*/ 0x00000000,
+	/*0694*/ 0x00000000,
+	/*0695*/ 0x00005064,
+	/*0696*/ 0x01421142,
+	/*0697*/ 0x00000142,
+	/*0698*/ 0x00000000,
+	/*0699*/ 0x000f1100,
+	/*069a*/ 0x0f110f11,
+	/*069b*/ 0x09000f11,
+	/*069c*/ 0x00000003,
+	/*069d*/ 0x0002c000,
+	/*069e*/ 0x02c002c0,
+	/*069f*/ 0x000002c0,
+	/*06a0*/ 0x03421342,
+	/*06a1*/ 0x00000342,
+	/*06a2*/ 0x00000000,
+	/*06a3*/ 0x00000000,
+	/*06a4*/ 0x05020000,
+	/*06a5*/ 0x14000000,
+	/*06a6*/ 0x027f6e00,
+	/*06a7*/ 0x047f027f,
+	/*06a8*/ 0x00027f6e,
+	/*06a9*/ 0x00047f6e,
+	/*06aa*/ 0x0003554f,
+	/*06ab*/ 0x0001554f,
+	/*06ac*/ 0x0001554f,
+	/*06ad*/ 0x0001554f,
+	/*06ae*/ 0x0001554f,
+	/*06af*/ 0x00003fee,
+	/*06b0*/ 0x0001554f,
+	/*06b1*/ 0x00003fee,
+	/*06b2*/ 0x0001554f,
+	/*06b3*/ 0x00027f6e,
+	/*06b4*/ 0x0001554f,
+	/*06b5*/ 0x00004011,
+	/*06b6*/ 0x00004410,
+	/*06b7*/ 0x00000000,
+	/*06b8*/ 0x00000000,
+	/*06b9*/ 0x00000000,
+	/*06ba*/ 0x00000065,
+	/*06bb*/ 0x00000000,
+	/*06bc*/ 0x00020201,
+	/*06bd*/ 0x00000000,
+	/*06be*/ 0x03000000,
+	/*06bf*/ 0x00000008,
+	/*06c0*/ 0x00000000,
+	/*06c1*/ 0x00000000,
+	/*06c2*/ 0x00000000,
+	/*06c3*/ 0x00000000,
+	/*06c4*/ 0x00000001,
+	/*06c5*/ 0x00000000,
+	/*06c6*/ 0x00000000,
+	/*06c7*/ 0x00000000,
+	/*06c8*/ 0x000000e4,
+	/*06c9*/ 0x00010198,
+	/*06ca*/ 0x00000000,
+	/*06cb*/ 0x00000000,
+	/*06cc*/ 0x07010000,
+	/*06cd*/ 0x00000104,
+	/*06ce*/ 0x00000000
+};
+
+static const uint32_t DDR_PI_REGSET_H3VER2[DDR_PI_REGSET_NUM_H3VER2] = {
+	/*0200*/ 0x00000b00,
+	/*0201*/ 0x00000100,
+	/*0202*/ 0x00640000,
+	/*0203*/ 0x00000000,
+	/*0204*/ 0x0000ffff,
+	/*0205*/ 0x00000000,
+	/*0206*/ 0x0000ffff,
+	/*0207*/ 0x00000000,
+	/*0208*/ 0x0000ffff,
+	/*0209*/ 0x0000304c,
+	/*020a*/ 0x00000200,
+	/*020b*/ 0x00000200,
+	/*020c*/ 0x00000200,
+	/*020d*/ 0x00000200,
+	/*020e*/ 0x0000304c,
+	/*020f*/ 0x00000200,
+	/*0210*/ 0x00000200,
+	/*0211*/ 0x00000200,
+	/*0212*/ 0x00000200,
+	/*0213*/ 0x0000304c,
+	/*0214*/ 0x00000200,
+	/*0215*/ 0x00000200,
+	/*0216*/ 0x00000200,
+	/*0217*/ 0x00000200,
+	/*0218*/ 0x00010000,
+	/*0219*/ 0x00000003,
+	/*021a*/ 0x01000001,
+	/*021b*/ 0x00000000,
+	/*021c*/ 0x00000000,
+	/*021d*/ 0x00000000,
+	/*021e*/ 0x00000000,
+	/*021f*/ 0x00000000,
+	/*0220*/ 0x00000000,
+	/*0221*/ 0x00000000,
+	/*0222*/ 0x00000000,
+	/*0223*/ 0x00000000,
+	/*0224*/ 0x00000000,
+	/*0225*/ 0x00000000,
+	/*0226*/ 0x00000000,
+	/*0227*/ 0x00000000,
+	/*0228*/ 0x00000000,
+	/*0229*/ 0x00000000,
+	/*022a*/ 0x00000000,
+	/*022b*/ 0x0f000101,
+	/*022c*/ 0x08492d25,
+	/*022d*/ 0x500e0c04,
+	/*022e*/ 0x0002500e,
+	/*022f*/ 0x00000301,
+	/*0230*/ 0x00000046,
+	/*0231*/ 0x000000cf,
+	/*0232*/ 0x00001826,
+	/*0233*/ 0x000000cf,
+	/*0234*/ 0x00001826,
+	/*0235*/ 0x00000005,
+	/*0236*/ 0x00000000,
+	/*0237*/ 0x00000000,
+	/*0238*/ 0x00000000,
+	/*0239*/ 0x00000000,
+	/*023a*/ 0x00000000,
+	/*023b*/ 0x00000000,
+	/*023c*/ 0x00000000,
+	/*023d*/ 0x00000000,
+	/*023e*/ 0x04010000,
+	/*023f*/ 0x00000404,
+	/*0240*/ 0x0101280a,
+	/*0241*/ 0x00000000,
+	/*0242*/ 0x00000000,
+	/*0243*/ 0x0003000f,
+	/*0244*/ 0x00000018,
+	/*0245*/ 0x00000000,
+	/*0246*/ 0x00000000,
+	/*0247*/ 0x00060002,
+	/*0248*/ 0x00010001,
+	/*0249*/ 0x01000101,
+	/*024a*/ 0x04020201,
+	/*024b*/ 0x00080804,
+	/*024c*/ 0x00000000,
+	/*024d*/ 0x08030000,
+	/*024e*/ 0x15150408,
+	/*024f*/ 0x00000000,
+	/*0250*/ 0x00000000,
+	/*0251*/ 0x00000000,
+	/*0252*/ 0x0f0f0000,
+	/*0253*/ 0x0000001e,
+	/*0254*/ 0x00000000,
+	/*0255*/ 0x01000300,
+	/*0256*/ 0x00000100,
+	/*0257*/ 0x00000000,
+	/*0258*/ 0x00000000,
+	/*0259*/ 0x01000000,
+	/*025a*/ 0x00000101,
+	/*025b*/ 0x55555a5a,
+	/*025c*/ 0x55555a5a,
+	/*025d*/ 0x55555a5a,
+	/*025e*/ 0x55555a5a,
+	/*025f*/ 0x0e0e0001,
+	/*0260*/ 0x0c0c000e,
+	/*0261*/ 0x0601000c,
+	/*0262*/ 0x17170106,
+	/*0263*/ 0x00020202,
+	/*0264*/ 0x03000000,
+	/*0265*/ 0x00000000,
+	/*0266*/ 0x00181703,
+	/*0267*/ 0x00280006,
+	/*0268*/ 0x00280016,
+	/*0269*/ 0x00000016,
+	/*026a*/ 0x00000000,
+	/*026b*/ 0x00000000,
+	/*026c*/ 0x00000000,
+	/*026d*/ 0x0a000000,
+	/*026e*/ 0x00010a14,
+	/*026f*/ 0x00030005,
+	/*0270*/ 0x0003018d,
+	/*0271*/ 0x000a018d,
+	/*0272*/ 0x00060100,
+	/*0273*/ 0x01000006,
+	/*0274*/ 0x018e018e,
+	/*0275*/ 0x018e0100,
+	/*0276*/ 0x1111018e,
+	/*0277*/ 0x10010204,
+	/*0278*/ 0x09090650,
+	/*0279*/ 0xff110202,
+	/*027a*/ 0x00ff1000,
+	/*027b*/ 0x00ff1000,
+	/*027c*/ 0x04041000,
+	/*027d*/ 0x18020100,
+	/*027e*/ 0x01010018,
+	/*027f*/ 0x004a004a,
+	/*0280*/ 0x004b004a,
+	/*0281*/ 0x050f0000,
+	/*0282*/ 0x0c01021e,
+	/*0283*/ 0x34000000,
+	/*0284*/ 0x00000000,
+	/*0285*/ 0x00000000,
+	/*0286*/ 0x00000000,
+	/*0287*/ 0x00000000,
+	/*0288*/ 0x36312ed4,
+	/*0289*/ 0x2ed41111,
+	/*028a*/ 0x11113631,
+	/*028b*/ 0x36312ed4,
+	/*028c*/ 0xd4001111,
+	/*028d*/ 0x1136312e,
+	/*028e*/ 0x312ed411,
+	/*028f*/ 0xd4111136,
+	/*0290*/ 0x1136312e,
+	/*0291*/ 0x2ed40011,
+	/*0292*/ 0x11113631,
+	/*0293*/ 0x36312ed4,
+	/*0294*/ 0x2ed41111,
+	/*0295*/ 0x11113631,
+	/*0296*/ 0x312ed400,
+	/*0297*/ 0xd4111136,
+	/*0298*/ 0x1136312e,
+	/*0299*/ 0x312ed411,
+	/*029a*/ 0x00111136,
+	/*029b*/ 0x018d0200,
+	/*029c*/ 0x018d018d,
+	/*029d*/ 0x1d220c08,
+	/*029e*/ 0x00001f12,
+	/*029f*/ 0x4301b344,
+	/*02a0*/ 0x10172006,
+	/*02a1*/ 0x121d220c,
+	/*02a2*/ 0x01b3441f,
+	/*02a3*/ 0x17200643,
+	/*02a4*/ 0x1d220c10,
+	/*02a5*/ 0x00001f12,
+	/*02a6*/ 0x4301b344,
+	/*02a7*/ 0x10172006,
+	/*02a8*/ 0x00020002,
+	/*02a9*/ 0x00020002,
+	/*02aa*/ 0x00020002,
+	/*02ab*/ 0x00020002,
+	/*02ac*/ 0x00020002,
+	/*02ad*/ 0x00000000,
+	/*02ae*/ 0x00000000,
+	/*02af*/ 0x00000000,
+	/*02b0*/ 0x00000000,
+	/*02b1*/ 0x00000000,
+	/*02b2*/ 0x00000000,
+	/*02b3*/ 0x00000000,
+	/*02b4*/ 0x00000000,
+	/*02b5*/ 0x00000000,
+	/*02b6*/ 0x00000000,
+	/*02b7*/ 0x00000000,
+	/*02b8*/ 0x00000000,
+	/*02b9*/ 0x00000400,
+	/*02ba*/ 0x05040302,
+	/*02bb*/ 0x01000f0e,
+	/*02bc*/ 0x07060504,
+	/*02bd*/ 0x03020100,
+	/*02be*/ 0x02010000,
+	/*02bf*/ 0x00000103,
+	/*02c0*/ 0x0000304c,
+	/*02c1*/ 0x0001e2f8,
+	/*02c2*/ 0x0000304c,
+	/*02c3*/ 0x0001e2f8,
+	/*02c4*/ 0x0000304c,
+	/*02c5*/ 0x0001e2f8,
+	/*02c6*/ 0x08000000,
+	/*02c7*/ 0x00000100,
+	/*02c8*/ 0x00000000,
+	/*02c9*/ 0x00000000,
+	/*02ca*/ 0x00000000,
+	/*02cb*/ 0x00000000,
+	/*02cc*/ 0x00010000,
+	/*02cd*/ 0x00000000,
+	/*02ce*/ 0x00000000,
+	/*02cf*/ 0x00000000,
+	/*02d0*/ 0x00000000,
+	/*02d1*/ 0x00000000,
+	/*02d2*/ 0x00000000,
+	/*02d3*/ 0x00000000,
+	/*02d4*/ 0x00000000,
+	/*02d5*/ 0x00000000,
+	/*02d6*/ 0x00000000,
+	/*02d7*/ 0x00000000,
+	/*02d8*/ 0x00000000,
+	/*02d9*/ 0x00000000,
+	/*02da*/ 0x00000000,
+	/*02db*/ 0x00000000,
+	/*02dc*/ 0x00000000,
+	/*02dd*/ 0x00000000,
+	/*02de*/ 0x00000000,
+	/*02df*/ 0x00000000,
+	/*02e0*/ 0x00000000,
+	/*02e1*/ 0x00000000,
+	/*02e2*/ 0x00000000,
+	/*02e3*/ 0x00000000,
+	/*02e4*/ 0x00000000,
+	/*02e5*/ 0x00000000,
+	/*02e6*/ 0x00000000,
+	/*02e7*/ 0x00000000,
+	/*02e8*/ 0x00000000,
+	/*02e9*/ 0x00000000,
+	/*02ea*/ 0x00000000,
+	/*02eb*/ 0x00000000,
+	/*02ec*/ 0x00000000,
+	/*02ed*/ 0x00000000,
+	/*02ee*/ 0x00000002,
+	/*02ef*/ 0x00000000,
+	/*02f0*/ 0x00000000,
+	/*02f1*/ 0x00000000,
+	/*02f2*/ 0x00000000,
+	/*02f3*/ 0x00000000,
+	/*02f4*/ 0x00000000
+};
diff --git a/drivers/renesas/rcar/ddr/ddr_b/init_dram_tbl_m3.h b/drivers/renesas/rcar/ddr/ddr_b/init_dram_tbl_m3.h
new file mode 100644
index 000000000..b491f0e91
--- /dev/null
+++ b/drivers/renesas/rcar/ddr/ddr_b/init_dram_tbl_m3.h
@@ -0,0 +1,468 @@
+/*
+ * Copyright (c) 2015-2019, Renesas Electronics Corporation.
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#define DDR_PHY_SLICE_REGSET_OFS_M3  0x0800
+#define DDR_PHY_ADR_V_REGSET_OFS_M3  0x0a00
+#define DDR_PHY_ADR_I_REGSET_OFS_M3  0x0a80
+#define DDR_PHY_ADR_G_REGSET_OFS_M3  0x0b80
+#define DDR_PI_REGSET_OFS_M3         0x0200
+
+#define DDR_PHY_SLICE_REGSET_SIZE_M3 0x80
+#define DDR_PHY_ADR_V_REGSET_SIZE_M3 0x80
+#define DDR_PHY_ADR_I_REGSET_SIZE_M3 0x80
+#define DDR_PHY_ADR_G_REGSET_SIZE_M3 0x80
+#define DDR_PI_REGSET_SIZE_M3        0x100
+
+#define DDR_PHY_SLICE_REGSET_NUM_M3  89
+#define DDR_PHY_ADR_V_REGSET_NUM_M3  37
+#define DDR_PHY_ADR_I_REGSET_NUM_M3  37
+#define DDR_PHY_ADR_G_REGSET_NUM_M3  64
+#define DDR_PI_REGSET_NUM_M3         202
+
+static const uint32_t DDR_PHY_SLICE_REGSET_M3[DDR_PHY_SLICE_REGSET_NUM_M3] = {
+	/*0800*/ 0x76543210,
+	/*0801*/ 0x0004f008,
+	/*0802*/ 0x00000000,
+	/*0803*/ 0x00000000,
+	/*0804*/ 0x00010000,
+	/*0805*/ 0x036e6e0e,
+	/*0806*/ 0x026e6e0e,
+	/*0807*/ 0x00010300,
+	/*0808*/ 0x04000100,
+	/*0809*/ 0x00000300,
+	/*080a*/ 0x001700c0,
+	/*080b*/ 0x00b00201,
+	/*080c*/ 0x00030020,
+	/*080d*/ 0x00000000,
+	/*080e*/ 0x00000000,
+	/*080f*/ 0x00000000,
+	/*0810*/ 0x00000000,
+	/*0811*/ 0x00000000,
+	/*0812*/ 0x00000000,
+	/*0813*/ 0x00000000,
+	/*0814*/ 0x09000000,
+	/*0815*/ 0x04080000,
+	/*0816*/ 0x04080400,
+	/*0817*/ 0x00000000,
+	/*0818*/ 0x32103210,
+	/*0819*/ 0x00800708,
+	/*081a*/ 0x000f000c,
+	/*081b*/ 0x00000100,
+	/*081c*/ 0x55aa55aa,
+	/*081d*/ 0x33cc33cc,
+	/*081e*/ 0x0ff00ff0,
+	/*081f*/ 0x0f0ff0f0,
+	/*0820*/ 0x00018e38,
+	/*0821*/ 0x00000000,
+	/*0822*/ 0x00000000,
+	/*0823*/ 0x00000000,
+	/*0824*/ 0x00000000,
+	/*0825*/ 0x00000000,
+	/*0826*/ 0x00000000,
+	/*0827*/ 0x00000000,
+	/*0828*/ 0x00000000,
+	/*0829*/ 0x00000000,
+	/*082a*/ 0x00000000,
+	/*082b*/ 0x00000000,
+	/*082c*/ 0x00000000,
+	/*082d*/ 0x00000000,
+	/*082e*/ 0x00000000,
+	/*082f*/ 0x00000000,
+	/*0830*/ 0x00000000,
+	/*0831*/ 0x00000000,
+	/*0832*/ 0x00000000,
+	/*0833*/ 0x00200000,
+	/*0834*/ 0x08200820,
+	/*0835*/ 0x08200820,
+	/*0836*/ 0x08200820,
+	/*0837*/ 0x08200820,
+	/*0838*/ 0x08200820,
+	/*0839*/ 0x00000820,
+	/*083a*/ 0x03000300,
+	/*083b*/ 0x03000300,
+	/*083c*/ 0x03000300,
+	/*083d*/ 0x03000300,
+	/*083e*/ 0x00000300,
+	/*083f*/ 0x00000000,
+	/*0840*/ 0x00000000,
+	/*0841*/ 0x00000000,
+	/*0842*/ 0x00000000,
+	/*0843*/ 0x00a00000,
+	/*0844*/ 0x00a000a0,
+	/*0845*/ 0x00a000a0,
+	/*0846*/ 0x00a000a0,
+	/*0847*/ 0x00a000a0,
+	/*0848*/ 0x00a000a0,
+	/*0849*/ 0x00a000a0,
+	/*084a*/ 0x00a000a0,
+	/*084b*/ 0x00a000a0,
+	/*084c*/ 0x010900a0,
+	/*084d*/ 0x02000104,
+	/*084e*/ 0x00000000,
+	/*084f*/ 0x00010000,
+	/*0850*/ 0x00000200,
+	/*0851*/ 0x4041a151,
+	/*0852*/ 0xc00141a0,
+	/*0853*/ 0x0e0100c0,
+	/*0854*/ 0x0010000c,
+	/*0855*/ 0x0c064208,
+	/*0856*/ 0x000f0c18,
+	/*0857*/ 0x00e00140,
+	/*0858*/ 0x00000c20
+};
+
+static const uint32_t DDR_PHY_ADR_V_REGSET_M3[DDR_PHY_ADR_V_REGSET_NUM_M3] = {
+	/*0a00*/ 0x00000000,
+	/*0a01*/ 0x00000000,
+	/*0a02*/ 0x00000000,
+	/*0a03*/ 0x00000000,
+	/*0a04*/ 0x00000000,
+	/*0a05*/ 0x00000000,
+	/*0a06*/ 0x00000002,
+	/*0a07*/ 0x00000000,
+	/*0a08*/ 0x00000000,
+	/*0a09*/ 0x00000000,
+	/*0a0a*/ 0x00400320,
+	/*0a0b*/ 0x00000040,
+	/*0a0c*/ 0x00dcba98,
+	/*0a0d*/ 0x00000000,
+	/*0a0e*/ 0x00dcba98,
+	/*0a0f*/ 0x01000000,
+	/*0a10*/ 0x00020003,
+	/*0a11*/ 0x00000000,
+	/*0a12*/ 0x00000000,
+	/*0a13*/ 0x00000000,
+	/*0a14*/ 0x0000002a,
+	/*0a15*/ 0x00000015,
+	/*0a16*/ 0x00000015,
+	/*0a17*/ 0x0000002a,
+	/*0a18*/ 0x00000033,
+	/*0a19*/ 0x0000000c,
+	/*0a1a*/ 0x0000000c,
+	/*0a1b*/ 0x00000033,
+	/*0a1c*/ 0x0a418820,
+	/*0a1d*/ 0x003f0000,
+	/*0a1e*/ 0x0000003f,
+	/*0a1f*/ 0x0002c06e,
+	/*0a20*/ 0x02c002c0,
+	/*0a21*/ 0x02c002c0,
+	/*0a22*/ 0x000002c0,
+	/*0a23*/ 0x42080010,
+	/*0a24*/ 0x00000003
+};
+
+static const uint32_t DDR_PHY_ADR_I_REGSET_M3[DDR_PHY_ADR_I_REGSET_NUM_M3] = {
+	/*0a80*/ 0x04040404,
+	/*0a81*/ 0x00000404,
+	/*0a82*/ 0x00000000,
+	/*0a83*/ 0x00000000,
+	/*0a84*/ 0x00000000,
+	/*0a85*/ 0x00000000,
+	/*0a86*/ 0x00000002,
+	/*0a87*/ 0x00000000,
+	/*0a88*/ 0x00000000,
+	/*0a89*/ 0x00000000,
+	/*0a8a*/ 0x00400320,
+	/*0a8b*/ 0x00000040,
+	/*0a8c*/ 0x00000000,
+	/*0a8d*/ 0x00000000,
+	/*0a8e*/ 0x00000000,
+	/*0a8f*/ 0x01000000,
+	/*0a90*/ 0x00020003,
+	/*0a91*/ 0x00000000,
+	/*0a92*/ 0x00000000,
+	/*0a93*/ 0x00000000,
+	/*0a94*/ 0x0000002a,
+	/*0a95*/ 0x00000015,
+	/*0a96*/ 0x00000015,
+	/*0a97*/ 0x0000002a,
+	/*0a98*/ 0x00000033,
+	/*0a99*/ 0x0000000c,
+	/*0a9a*/ 0x0000000c,
+	/*0a9b*/ 0x00000033,
+	/*0a9c*/ 0x00000000,
+	/*0a9d*/ 0x00000000,
+	/*0a9e*/ 0x00000000,
+	/*0a9f*/ 0x0002c06e,
+	/*0aa0*/ 0x02c002c0,
+	/*0aa1*/ 0x02c002c0,
+	/*0aa2*/ 0x000002c0,
+	/*0aa3*/ 0x42080010,
+	/*0aa4*/ 0x00000003
+};
+
+static const uint32_t DDR_PHY_ADR_G_REGSET_M3[DDR_PHY_ADR_G_REGSET_NUM_M3] = {
+	/*0b80*/ 0x00000001,
+	/*0b81*/ 0x00000000,
+	/*0b82*/ 0x00000005,
+	/*0b83*/ 0x04000f00,
+	/*0b84*/ 0x00020080,
+	/*0b85*/ 0x00020055,
+	/*0b86*/ 0x00000000,
+	/*0b87*/ 0x00000000,
+	/*0b88*/ 0x00000000,
+	/*0b89*/ 0x00000050,
+	/*0b8a*/ 0x00000000,
+	/*0b8b*/ 0x01010100,
+	/*0b8c*/ 0x00000600,
+	/*0b8d*/ 0x50640000,
+	/*0b8e*/ 0x01421142,
+	/*0b8f*/ 0x00000142,
+	/*0b90*/ 0x00000000,
+	/*0b91*/ 0x000f1600,
+	/*0b92*/ 0x0f160f16,
+	/*0b93*/ 0x0f160f16,
+	/*0b94*/ 0x00000003,
+	/*0b95*/ 0x0002c000,
+	/*0b96*/ 0x02c002c0,
+	/*0b97*/ 0x000002c0,
+	/*0b98*/ 0x03421342,
+	/*0b99*/ 0x00000342,
+	/*0b9a*/ 0x00000000,
+	/*0b9b*/ 0x00000000,
+	/*0b9c*/ 0x05020000,
+	/*0b9d*/ 0x00000000,
+	/*0b9e*/ 0x00027f6e,
+	/*0b9f*/ 0x047f027f,
+	/*0ba0*/ 0x00027f6e,
+	/*0ba1*/ 0x00047f6e,
+	/*0ba2*/ 0x0003554f,
+	/*0ba3*/ 0x0001554f,
+	/*0ba4*/ 0x0001554f,
+	/*0ba5*/ 0x0001554f,
+	/*0ba6*/ 0x0001554f,
+	/*0ba7*/ 0x00003fee,
+	/*0ba8*/ 0x0001554f,
+	/*0ba9*/ 0x00003fee,
+	/*0baa*/ 0x0001554f,
+	/*0bab*/ 0x00027f6e,
+	/*0bac*/ 0x0001554f,
+	/*0bad*/ 0x00000000,
+	/*0bae*/ 0x00000000,
+	/*0baf*/ 0x00000000,
+	/*0bb0*/ 0x65000000,
+	/*0bb1*/ 0x00000000,
+	/*0bb2*/ 0x00000000,
+	/*0bb3*/ 0x00000201,
+	/*0bb4*/ 0x00000000,
+	/*0bb5*/ 0x00000000,
+	/*0bb6*/ 0x00000000,
+	/*0bb7*/ 0x00000000,
+	/*0bb8*/ 0x00000000,
+	/*0bb9*/ 0x00000000,
+	/*0bba*/ 0x00000000,
+	/*0bbb*/ 0x00000000,
+	/*0bbc*/ 0x06e40000,
+	/*0bbd*/ 0x00000000,
+	/*0bbe*/ 0x00000000,
+	/*0bbf*/ 0x00010000
+};
+
+static const uint32_t DDR_PI_REGSET_M3[DDR_PI_REGSET_NUM_M3] = {
+	/*0200*/ 0x00000b00,
+	/*0201*/ 0x00000100,
+	/*0202*/ 0x00000000,
+	/*0203*/ 0x0000ffff,
+	/*0204*/ 0x00000000,
+	/*0205*/ 0x0000ffff,
+	/*0206*/ 0x00000000,
+	/*0207*/ 0x304cffff,
+	/*0208*/ 0x00000200,
+	/*0209*/ 0x00000200,
+	/*020a*/ 0x00000200,
+	/*020b*/ 0x00000200,
+	/*020c*/ 0x0000304c,
+	/*020d*/ 0x00000200,
+	/*020e*/ 0x00000200,
+	/*020f*/ 0x00000200,
+	/*0210*/ 0x00000200,
+	/*0211*/ 0x0000304c,
+	/*0212*/ 0x00000200,
+	/*0213*/ 0x00000200,
+	/*0214*/ 0x00000200,
+	/*0215*/ 0x00000200,
+	/*0216*/ 0x00010000,
+	/*0217*/ 0x00000003,
+	/*0218*/ 0x01000001,
+	/*0219*/ 0x00000000,
+	/*021a*/ 0x00000000,
+	/*021b*/ 0x00000000,
+	/*021c*/ 0x00000000,
+	/*021d*/ 0x00000000,
+	/*021e*/ 0x00000000,
+	/*021f*/ 0x00000000,
+	/*0220*/ 0x00000000,
+	/*0221*/ 0x00000000,
+	/*0222*/ 0x00000000,
+	/*0223*/ 0x00000000,
+	/*0224*/ 0x00000000,
+	/*0225*/ 0x00000000,
+	/*0226*/ 0x00000000,
+	/*0227*/ 0x00000000,
+	/*0228*/ 0x00000000,
+	/*0229*/ 0x0f000101,
+	/*022a*/ 0x08492d25,
+	/*022b*/ 0x0e0c0004,
+	/*022c*/ 0x000e5000,
+	/*022d*/ 0x00000250,
+	/*022e*/ 0x00460003,
+	/*022f*/ 0x182600cf,
+	/*0230*/ 0x182600cf,
+	/*0231*/ 0x00000005,
+	/*0232*/ 0x00000000,
+	/*0233*/ 0x00000000,
+	/*0234*/ 0x00000000,
+	/*0235*/ 0x00000000,
+	/*0236*/ 0x00000000,
+	/*0237*/ 0x00000000,
+	/*0238*/ 0x00000000,
+	/*0239*/ 0x01000000,
+	/*023a*/ 0x00040404,
+	/*023b*/ 0x01280a00,
+	/*023c*/ 0x00000000,
+	/*023d*/ 0x000f0000,
+	/*023e*/ 0x00001803,
+	/*023f*/ 0x00000000,
+	/*0240*/ 0x00000000,
+	/*0241*/ 0x00060002,
+	/*0242*/ 0x00010001,
+	/*0243*/ 0x01000101,
+	/*0244*/ 0x04020201,
+	/*0245*/ 0x00080804,
+	/*0246*/ 0x00000000,
+	/*0247*/ 0x08030000,
+	/*0248*/ 0x15150408,
+	/*0249*/ 0x00000000,
+	/*024a*/ 0x00000000,
+	/*024b*/ 0x00000000,
+	/*024c*/ 0x000f0f00,
+	/*024d*/ 0x0000001e,
+	/*024e*/ 0x00000000,
+	/*024f*/ 0x01000300,
+	/*0250*/ 0x00000000,
+	/*0251*/ 0x00000000,
+	/*0252*/ 0x01000000,
+	/*0253*/ 0x00010101,
+	/*0254*/ 0x000e0e0e,
+	/*0255*/ 0x000c0c0c,
+	/*0256*/ 0x02060601,
+	/*0257*/ 0x00000000,
+	/*0258*/ 0x00000003,
+	/*0259*/ 0x00181703,
+	/*025a*/ 0x00280006,
+	/*025b*/ 0x00280016,
+	/*025c*/ 0x00000016,
+	/*025d*/ 0x00000000,
+	/*025e*/ 0x00000000,
+	/*025f*/ 0x00000000,
+	/*0260*/ 0x140a0000,
+	/*0261*/ 0x0005010a,
+	/*0262*/ 0x03018d03,
+	/*0263*/ 0x000a018d,
+	/*0264*/ 0x00060100,
+	/*0265*/ 0x01000006,
+	/*0266*/ 0x018e018e,
+	/*0267*/ 0x018e0100,
+	/*0268*/ 0x1111018e,
+	/*0269*/ 0x10010204,
+	/*026a*/ 0x09090650,
+	/*026b*/ 0x20110202,
+	/*026c*/ 0x00201000,
+	/*026d*/ 0x00201000,
+	/*026e*/ 0x04041000,
+	/*026f*/ 0x18020100,
+	/*0270*/ 0x00010118,
+	/*0271*/ 0x004b004a,
+	/*0272*/ 0x050f0000,
+	/*0273*/ 0x0c01021e,
+	/*0274*/ 0x34000000,
+	/*0275*/ 0x00000000,
+	/*0276*/ 0x00000000,
+	/*0277*/ 0x00000000,
+	/*0278*/ 0x0000d400,
+	/*0279*/ 0x0031002e,
+	/*027a*/ 0x00111136,
+	/*027b*/ 0x002e00d4,
+	/*027c*/ 0x11360031,
+	/*027d*/ 0x0000d411,
+	/*027e*/ 0x0031002e,
+	/*027f*/ 0x00111136,
+	/*0280*/ 0x002e00d4,
+	/*0281*/ 0x11360031,
+	/*0282*/ 0x0000d411,
+	/*0283*/ 0x0031002e,
+	/*0284*/ 0x00111136,
+	/*0285*/ 0x002e00d4,
+	/*0286*/ 0x11360031,
+	/*0287*/ 0x00d40011,
+	/*0288*/ 0x0031002e,
+	/*0289*/ 0x00111136,
+	/*028a*/ 0x002e00d4,
+	/*028b*/ 0x11360031,
+	/*028c*/ 0x0000d411,
+	/*028d*/ 0x0031002e,
+	/*028e*/ 0x00111136,
+	/*028f*/ 0x002e00d4,
+	/*0290*/ 0x11360031,
+	/*0291*/ 0x0000d411,
+	/*0292*/ 0x0031002e,
+	/*0293*/ 0x00111136,
+	/*0294*/ 0x002e00d4,
+	/*0295*/ 0x11360031,
+	/*0296*/ 0x02000011,
+	/*0297*/ 0x018d018d,
+	/*0298*/ 0x0c08018d,
+	/*0299*/ 0x1f121d22,
+	/*029a*/ 0x4301b344,
+	/*029b*/ 0x10172006,
+	/*029c*/ 0x1d220c10,
+	/*029d*/ 0x00001f12,
+	/*029e*/ 0x4301b344,
+	/*029f*/ 0x10172006,
+	/*02a0*/ 0x1d220c10,
+	/*02a1*/ 0x00001f12,
+	/*02a2*/ 0x4301b344,
+	/*02a3*/ 0x10172006,
+	/*02a4*/ 0x02000210,
+	/*02a5*/ 0x02000200,
+	/*02a6*/ 0x02000200,
+	/*02a7*/ 0x02000200,
+	/*02a8*/ 0x02000200,
+	/*02a9*/ 0x00000000,
+	/*02aa*/ 0x00000000,
+	/*02ab*/ 0x00000000,
+	/*02ac*/ 0x00000000,
+	/*02ad*/ 0x00000000,
+	/*02ae*/ 0x00000000,
+	/*02af*/ 0x00000000,
+	/*02b0*/ 0x00000000,
+	/*02b1*/ 0x00000000,
+	/*02b2*/ 0x00000000,
+	/*02b3*/ 0x00000000,
+	/*02b4*/ 0x00000000,
+	/*02b5*/ 0x00000400,
+	/*02b6*/ 0x15141312,
+	/*02b7*/ 0x11100f0e,
+	/*02b8*/ 0x080b0c0d,
+	/*02b9*/ 0x05040a09,
+	/*02ba*/ 0x01000706,
+	/*02bb*/ 0x00000302,
+	/*02bc*/ 0x01030201,
+	/*02bd*/ 0x00304c00,
+	/*02be*/ 0x0001e2f8,
+	/*02bf*/ 0x0000304c,
+	/*02c0*/ 0x0001e2f8,
+	/*02c1*/ 0x0000304c,
+	/*02c2*/ 0x0001e2f8,
+	/*02c3*/ 0x08000000,
+	/*02c4*/ 0x00000100,
+	/*02c5*/ 0x00000000,
+	/*02c6*/ 0x00000000,
+	/*02c7*/ 0x00000000,
+	/*02c8*/ 0x00000000,
+	/*02c9*/ 0x00000002
+};
diff --git a/drivers/renesas/rcar/ddr/ddr_b/init_dram_tbl_m3n.h b/drivers/renesas/rcar/ddr/ddr_b/init_dram_tbl_m3n.h
new file mode 100644
index 000000000..8d80842fd
--- /dev/null
+++ b/drivers/renesas/rcar/ddr/ddr_b/init_dram_tbl_m3n.h
@@ -0,0 +1,587 @@
+/*
+ * Copyright (c) 2015-2019, Renesas Electronics Corporation.
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#define DDR_PHY_SLICE_REGSET_OFS_M3N  0x0800
+#define DDR_PHY_ADR_V_REGSET_OFS_M3N  0x0a00
+#define DDR_PHY_ADR_I_REGSET_OFS_M3N  0x0a80
+#define DDR_PHY_ADR_G_REGSET_OFS_M3N  0x0b80
+#define DDR_PI_REGSET_OFS_M3N         0x0200
+
+#define DDR_PHY_SLICE_REGSET_SIZE_M3N 0x80
+#define DDR_PHY_ADR_V_REGSET_SIZE_M3N 0x80
+#define DDR_PHY_ADR_I_REGSET_SIZE_M3N 0x80
+#define DDR_PHY_ADR_G_REGSET_SIZE_M3N 0x80
+#define DDR_PI_REGSET_SIZE_M3N        0x100
+
+#define DDR_PHY_SLICE_REGSET_NUM_M3N  101
+#define DDR_PHY_ADR_V_REGSET_NUM_M3N  37
+#define DDR_PHY_ADR_I_REGSET_NUM_M3N  37
+#define DDR_PHY_ADR_G_REGSET_NUM_M3N  87
+#define DDR_PI_REGSET_NUM_M3N         286
+
+static const uint32_t DDR_PHY_SLICE_REGSET_M3N[DDR_PHY_SLICE_REGSET_NUM_M3N] = {
+	/*0800*/ 0x76543210,
+	/*0801*/ 0x0004f008,
+	/*0802*/ 0x00020200,
+	/*0803*/ 0x00000000,
+	/*0804*/ 0x00000000,
+	/*0805*/ 0x00010000,
+	/*0806*/ 0x036e6e0e,
+	/*0807*/ 0x026e6e0e,
+	/*0808*/ 0x00000103,
+	/*0809*/ 0x00040001,
+	/*080a*/ 0x00000103,
+	/*080b*/ 0x00000001,
+	/*080c*/ 0x00000000,
+	/*080d*/ 0x00000000,
+	/*080e*/ 0x00000100,
+	/*080f*/ 0x001800c0,
+	/*0810*/ 0x020100b0,
+	/*0811*/ 0x00030020,
+	/*0812*/ 0x00000000,
+	/*0813*/ 0x00000000,
+	/*0814*/ 0x0000aaaa,
+	/*0815*/ 0x00005555,
+	/*0816*/ 0x0000b5b5,
+	/*0817*/ 0x00004a4a,
+	/*0818*/ 0x00000000,
+	/*0819*/ 0x09000000,
+	/*081a*/ 0x04080000,
+	/*081b*/ 0x08040000,
+	/*081c*/ 0x00000004,
+	/*081d*/ 0x00800710,
+	/*081e*/ 0x000f000c,
+	/*081f*/ 0x00000100,
+	/*0820*/ 0x55aa55aa,
+	/*0821*/ 0x33cc33cc,
+	/*0822*/ 0x0ff00ff0,
+	/*0823*/ 0x0f0ff0f0,
+	/*0824*/ 0x00018e38,
+	/*0825*/ 0x00000000,
+	/*0826*/ 0x00000000,
+	/*0827*/ 0x00000000,
+	/*0828*/ 0x00000000,
+	/*0829*/ 0x00000000,
+	/*082a*/ 0x00000000,
+	/*082b*/ 0x00000000,
+	/*082c*/ 0x00000000,
+	/*082d*/ 0x00000000,
+	/*082e*/ 0x00000000,
+	/*082f*/ 0x00000000,
+	/*0830*/ 0x00000000,
+	/*0831*/ 0x00000000,
+	/*0832*/ 0x00000000,
+	/*0833*/ 0x00000000,
+	/*0834*/ 0x00000000,
+	/*0835*/ 0x00000000,
+	/*0836*/ 0x00000000,
+	/*0837*/ 0x00000000,
+	/*0838*/ 0x00000000,
+	/*0839*/ 0x00000000,
+	/*083a*/ 0x00000104,
+	/*083b*/ 0x00082020,
+	/*083c*/ 0x08200820,
+	/*083d*/ 0x08200820,
+	/*083e*/ 0x08200820,
+	/*083f*/ 0x08200820,
+	/*0840*/ 0x08200820,
+	/*0841*/ 0x00000000,
+	/*0842*/ 0x00000000,
+	/*0843*/ 0x03000300,
+	/*0844*/ 0x03000300,
+	/*0845*/ 0x03000300,
+	/*0846*/ 0x03000300,
+	/*0847*/ 0x00000300,
+	/*0848*/ 0x00000000,
+	/*0849*/ 0x00000000,
+	/*084a*/ 0x00000000,
+	/*084b*/ 0x00000000,
+	/*084c*/ 0x00000000,
+	/*084d*/ 0x00a000a0,
+	/*084e*/ 0x00a000a0,
+	/*084f*/ 0x00a000a0,
+	/*0850*/ 0x00a000a0,
+	/*0851*/ 0x00a000a0,
+	/*0852*/ 0x00a000a0,
+	/*0853*/ 0x00a000a0,
+	/*0854*/ 0x00a000a0,
+	/*0855*/ 0x00a000a0,
+	/*0856*/ 0x01040119,
+	/*0857*/ 0x00000200,
+	/*0858*/ 0x01000000,
+	/*0859*/ 0x00000200,
+	/*085a*/ 0x00000004,
+	/*085b*/ 0x4041a151,
+	/*085c*/ 0x0141c0a0,
+	/*085d*/ 0x0000c0c0,
+	/*085e*/ 0x0e0c000e,
+	/*085f*/ 0x10001000,
+	/*0860*/ 0x0c073e42,
+	/*0861*/ 0x000f0c28,
+	/*0862*/ 0x00e00140,
+	/*0863*/ 0x000c0020,
+	/*0864*/ 0x00000203
+};
+
+static const uint32_t DDR_PHY_ADR_V_REGSET_M3N[DDR_PHY_ADR_V_REGSET_NUM_M3N] = {
+	/*0a00*/ 0x00000000,
+	/*0a01*/ 0x00000000,
+	/*0a02*/ 0x00000000,
+	/*0a03*/ 0x00000000,
+	/*0a04*/ 0x00000000,
+	/*0a05*/ 0x00000000,
+	/*0a06*/ 0x00000000,
+	/*0a07*/ 0x01000000,
+	/*0a08*/ 0x00020000,
+	/*0a09*/ 0x00000000,
+	/*0a0a*/ 0x00000000,
+	/*0a0b*/ 0x00000000,
+	/*0a0c*/ 0x00400000,
+	/*0a0d*/ 0x00000080,
+	/*0a0e*/ 0x00dcba98,
+	/*0a0f*/ 0x03000000,
+	/*0a10*/ 0x00000200,
+	/*0a11*/ 0x00000000,
+	/*0a12*/ 0x00000000,
+	/*0a13*/ 0x00000000,
+	/*0a14*/ 0x0000002a,
+	/*0a15*/ 0x00000015,
+	/*0a16*/ 0x00000015,
+	/*0a17*/ 0x0000002a,
+	/*0a18*/ 0x00000033,
+	/*0a19*/ 0x0000000c,
+	/*0a1a*/ 0x0000000c,
+	/*0a1b*/ 0x00000033,
+	/*0a1c*/ 0x0a418820,
+	/*0a1d*/ 0x003f0000,
+	/*0a1e*/ 0x0000013f,
+	/*0a1f*/ 0x0002c06e,
+	/*0a20*/ 0x02c002c0,
+	/*0a21*/ 0x02c002c0,
+	/*0a22*/ 0x000002c0,
+	/*0a23*/ 0x42080010,
+	/*0a24*/ 0x0000033e
+};
+
+static const uint32_t DDR_PHY_ADR_I_REGSET_M3N[DDR_PHY_ADR_I_REGSET_NUM_M3N] = {
+	/*0a80*/ 0x00000000,
+	/*0a81*/ 0x00000000,
+	/*0a82*/ 0x00000000,
+	/*0a83*/ 0x00000000,
+	/*0a84*/ 0x00000000,
+	/*0a85*/ 0x00000000,
+	/*0a86*/ 0x00000000,
+	/*0a87*/ 0x01000000,
+	/*0a88*/ 0x00020000,
+	/*0a89*/ 0x00000000,
+	/*0a8a*/ 0x00000000,
+	/*0a8b*/ 0x00000000,
+	/*0a8c*/ 0x00400000,
+	/*0a8d*/ 0x00000080,
+	/*0a8e*/ 0x00000000,
+	/*0a8f*/ 0x03000000,
+	/*0a90*/ 0x00000200,
+	/*0a91*/ 0x00000000,
+	/*0a92*/ 0x00000000,
+	/*0a93*/ 0x00000000,
+	/*0a94*/ 0x0000002a,
+	/*0a95*/ 0x00000015,
+	/*0a96*/ 0x00000015,
+	/*0a97*/ 0x0000002a,
+	/*0a98*/ 0x00000033,
+	/*0a99*/ 0x0000000c,
+	/*0a9a*/ 0x0000000c,
+	/*0a9b*/ 0x00000033,
+	/*0a9c*/ 0x00000000,
+	/*0a9d*/ 0x00000000,
+	/*0a9e*/ 0x00000000,
+	/*0a9f*/ 0x0002c06e,
+	/*0aa0*/ 0x02c002c0,
+	/*0aa1*/ 0x02c002c0,
+	/*0aa2*/ 0x000002c0,
+	/*0aa3*/ 0x42080010,
+	/*0aa4*/ 0x0000033e
+};
+
+static const uint32_t DDR_PHY_ADR_G_REGSET_M3N[DDR_PHY_ADR_G_REGSET_NUM_M3N] = {
+	/*0b80*/ 0x00000000,
+	/*0b81*/ 0x00000100,
+	/*0b82*/ 0x00000000,
+	/*0b83*/ 0x00050000,
+	/*0b84*/ 0x00000000,
+	/*0b85*/ 0x0004000f,
+	/*0b86*/ 0x00280080,
+	/*0b87*/ 0x02005502,
+	/*0b88*/ 0x00000000,
+	/*0b89*/ 0x00000000,
+	/*0b8a*/ 0x00000000,
+	/*0b8b*/ 0x00000050,
+	/*0b8c*/ 0x00000000,
+	/*0b8d*/ 0x01010100,
+	/*0b8e*/ 0x00010000,
+	/*0b8f*/ 0x00000000,
+	/*0b90*/ 0x00000101,
+	/*0b91*/ 0x00000000,
+	/*0b92*/ 0x00000000,
+	/*0b93*/ 0x00000000,
+	/*0b94*/ 0x00000000,
+	/*0b95*/ 0x00005064,
+	/*0b96*/ 0x01421142,
+	/*0b97*/ 0x00000142,
+	/*0b98*/ 0x00000000,
+	/*0b99*/ 0x000f1600,
+	/*0b9a*/ 0x0f160f16,
+	/*0b9b*/ 0x0f160f16,
+	/*0b9c*/ 0x00000003,
+	/*0b9d*/ 0x0002c000,
+	/*0b9e*/ 0x02c002c0,
+	/*0b9f*/ 0x000002c0,
+	/*0ba0*/ 0x08040201,
+	/*0ba1*/ 0x03421342,
+	/*0ba2*/ 0x00000342,
+	/*0ba3*/ 0x00000000,
+	/*0ba4*/ 0x00000000,
+	/*0ba5*/ 0x05030000,
+	/*0ba6*/ 0x00010700,
+	/*0ba7*/ 0x00000014,
+	/*0ba8*/ 0x00027f6e,
+	/*0ba9*/ 0x047f027f,
+	/*0baa*/ 0x00027f6e,
+	/*0bab*/ 0x00047f6e,
+	/*0bac*/ 0x0003554f,
+	/*0bad*/ 0x0001554f,
+	/*0bae*/ 0x0001554f,
+	/*0baf*/ 0x0001554f,
+	/*0bb0*/ 0x0001554f,
+	/*0bb1*/ 0x00003fee,
+	/*0bb2*/ 0x0001554f,
+	/*0bb3*/ 0x00003fee,
+	/*0bb4*/ 0x0001554f,
+	/*0bb5*/ 0x00027f6e,
+	/*0bb6*/ 0x0001554f,
+	/*0bb7*/ 0x00004011,
+	/*0bb8*/ 0x00004410,
+	/*0bb9*/ 0x00000000,
+	/*0bba*/ 0x00000000,
+	/*0bbb*/ 0x00000000,
+	/*0bbc*/ 0x00000265,
+	/*0bbd*/ 0x00000000,
+	/*0bbe*/ 0x00040401,
+	/*0bbf*/ 0x00000000,
+	/*0bc0*/ 0x03000000,
+	/*0bc1*/ 0x00000020,
+	/*0bc2*/ 0x00000000,
+	/*0bc3*/ 0x00000000,
+	/*0bc4*/ 0x04102006,
+	/*0bc5*/ 0x00041020,
+	/*0bc6*/ 0x01c98c98,
+	/*0bc7*/ 0x00400000,
+	/*0bc8*/ 0x00000000,
+	/*0bc9*/ 0x0001ffff,
+	/*0bca*/ 0x00000000,
+	/*0bcb*/ 0x00000000,
+	/*0bcc*/ 0x00000001,
+	/*0bcd*/ 0x00000000,
+	/*0bce*/ 0x00000000,
+	/*0bcf*/ 0x00000000,
+	/*0bd0*/ 0x76543210,
+	/*0bd1*/ 0x06010198,
+	/*0bd2*/ 0x00000000,
+	/*0bd3*/ 0x00000000,
+	/*0bd4*/ 0x04070000,
+	/*0bd5*/ 0x00000001,
+	/*0bd6*/ 0x00000f00
+};
+
+static const uint32_t DDR_PI_REGSET_M3N[DDR_PI_REGSET_NUM_M3N] = {
+	/*0200*/ 0x00000b00,
+	/*0201*/ 0x00000101,
+	/*0202*/ 0x01640000,
+	/*0203*/ 0x00000014,
+	/*0204*/ 0x00000014,
+	/*0205*/ 0x00000014,
+	/*0206*/ 0x00000014,
+	/*0207*/ 0x00000000,
+	/*0208*/ 0x00000000,
+	/*0209*/ 0x0000ffff,
+	/*020a*/ 0x00000000,
+	/*020b*/ 0x0000ffff,
+	/*020c*/ 0x00000000,
+	/*020d*/ 0x0000ffff,
+	/*020e*/ 0x0000304c,
+	/*020f*/ 0x00000200,
+	/*0210*/ 0x00000200,
+	/*0211*/ 0x00000200,
+	/*0212*/ 0x00000200,
+	/*0213*/ 0x0000304c,
+	/*0214*/ 0x00000200,
+	/*0215*/ 0x00000200,
+	/*0216*/ 0x00000200,
+	/*0217*/ 0x00000200,
+	/*0218*/ 0x0000304c,
+	/*0219*/ 0x00000200,
+	/*021a*/ 0x00000200,
+	/*021b*/ 0x00000200,
+	/*021c*/ 0x00000200,
+	/*021d*/ 0x00010000,
+	/*021e*/ 0x00000003,
+	/*021f*/ 0x01000001,
+	/*0220*/ 0x00000000,
+	/*0221*/ 0x00000000,
+	/*0222*/ 0x00000000,
+	/*0223*/ 0x00000000,
+	/*0224*/ 0x00000000,
+	/*0225*/ 0x00000000,
+	/*0226*/ 0x00000000,
+	/*0227*/ 0x00000000,
+	/*0228*/ 0x00000000,
+	/*0229*/ 0x00000000,
+	/*022a*/ 0x00000000,
+	/*022b*/ 0x00000000,
+	/*022c*/ 0x00000000,
+	/*022d*/ 0x00000000,
+	/*022e*/ 0x00000000,
+	/*022f*/ 0x00000000,
+	/*0230*/ 0x0f000101,
+	/*0231*/ 0x084d3129,
+	/*0232*/ 0x0e0c0004,
+	/*0233*/ 0x000e5000,
+	/*0234*/ 0x01000250,
+	/*0235*/ 0x00000003,
+	/*0236*/ 0x00000046,
+	/*0237*/ 0x000000cf,
+	/*0238*/ 0x00001826,
+	/*0239*/ 0x000000cf,
+	/*023a*/ 0x00001826,
+	/*023b*/ 0x00000000,
+	/*023c*/ 0x00000000,
+	/*023d*/ 0x00000000,
+	/*023e*/ 0x00000000,
+	/*023f*/ 0x00000000,
+	/*0240*/ 0x00000000,
+	/*0241*/ 0x00000000,
+	/*0242*/ 0x00000000,
+	/*0243*/ 0x00000000,
+	/*0244*/ 0x00000000,
+	/*0245*/ 0x01000000,
+	/*0246*/ 0x00040404,
+	/*0247*/ 0x01280a00,
+	/*0248*/ 0x00000001,
+	/*0249*/ 0x00000000,
+	/*024a*/ 0x03000f00,
+	/*024b*/ 0x00200020,
+	/*024c*/ 0x00000020,
+	/*024d*/ 0x00000000,
+	/*024e*/ 0x00000000,
+	/*024f*/ 0x00010002,
+	/*0250*/ 0x01010001,
+	/*0251*/ 0x02010100,
+	/*0252*/ 0x08040402,
+	/*0253*/ 0x00000008,
+	/*0254*/ 0x00000000,
+	/*0255*/ 0x04080803,
+	/*0256*/ 0x00001515,
+	/*0257*/ 0x00000000,
+	/*0258*/ 0x000000aa,
+	/*0259*/ 0x00000055,
+	/*025a*/ 0x000000b5,
+	/*025b*/ 0x0000004a,
+	/*025c*/ 0x00000056,
+	/*025d*/ 0x000000a9,
+	/*025e*/ 0x000000a9,
+	/*025f*/ 0x000000b5,
+	/*0260*/ 0x00000000,
+	/*0261*/ 0x00000000,
+	/*0262*/ 0x0f000000,
+	/*0263*/ 0x00001e0f,
+	/*0264*/ 0x000007d0,
+	/*0265*/ 0x01000300,
+	/*0266*/ 0x00000100,
+	/*0267*/ 0x00000000,
+	/*0268*/ 0x00000000,
+	/*0269*/ 0x01000000,
+	/*026a*/ 0x00010101,
+	/*026b*/ 0x000e0e0e,
+	/*026c*/ 0x000c0c0c,
+	/*026d*/ 0x01060601,
+	/*026e*/ 0x04041717,
+	/*026f*/ 0x00000004,
+	/*0270*/ 0x00000300,
+	/*0271*/ 0x17030000,
+	/*0272*/ 0x00060018,
+	/*0273*/ 0x00160028,
+	/*0274*/ 0x00160028,
+	/*0275*/ 0x00000000,
+	/*0276*/ 0x00000000,
+	/*0277*/ 0x00000000,
+	/*0278*/ 0x0a000000,
+	/*0279*/ 0x00010a14,
+	/*027a*/ 0x00030005,
+	/*027b*/ 0x0003018d,
+	/*027c*/ 0x000a018d,
+	/*027d*/ 0x00060100,
+	/*027e*/ 0x01000006,
+	/*027f*/ 0x018e018e,
+	/*0280*/ 0x018e0100,
+	/*0281*/ 0x1e1a018e,
+	/*0282*/ 0x1e1a1e1a,
+	/*0283*/ 0x01010204,
+	/*0284*/ 0x06501001,
+	/*0285*/ 0x090d0a07,
+	/*0286*/ 0x090d0a07,
+	/*0287*/ 0x0811180f,
+	/*0288*/ 0x00ff1102,
+	/*0289*/ 0x00ff1000,
+	/*028a*/ 0x00ff1000,
+	/*028b*/ 0x04041000,
+	/*028c*/ 0x18020100,
+	/*028d*/ 0x01010018,
+	/*028e*/ 0x005f005f,
+	/*028f*/ 0x005f005f,
+	/*0290*/ 0x050f0000,
+	/*0291*/ 0x051e051e,
+	/*0292*/ 0x0c01021e,
+	/*0293*/ 0x00000c0c,
+	/*0294*/ 0x00003400,
+	/*0295*/ 0x00000000,
+	/*0296*/ 0x00000000,
+	/*0297*/ 0x00000000,
+	/*0298*/ 0x00000000,
+	/*0299*/ 0x002e00d4,
+	/*029a*/ 0x11360031,
+	/*029b*/ 0x00d41611,
+	/*029c*/ 0x0031002e,
+	/*029d*/ 0x16111136,
+	/*029e*/ 0x002e00d4,
+	/*029f*/ 0x11360031,
+	/*02a0*/ 0x00001611,
+	/*02a1*/ 0x002e00d4,
+	/*02a2*/ 0x11360031,
+	/*02a3*/ 0x00d41611,
+	/*02a4*/ 0x0031002e,
+	/*02a5*/ 0x16111136,
+	/*02a6*/ 0x002e00d4,
+	/*02a7*/ 0x11360031,
+	/*02a8*/ 0x00001611,
+	/*02a9*/ 0x002e00d4,
+	/*02aa*/ 0x11360031,
+	/*02ab*/ 0x00d41611,
+	/*02ac*/ 0x0031002e,
+	/*02ad*/ 0x16111136,
+	/*02ae*/ 0x002e00d4,
+	/*02af*/ 0x11360031,
+	/*02b0*/ 0x00001611,
+	/*02b1*/ 0x002e00d4,
+	/*02b2*/ 0x11360031,
+	/*02b3*/ 0x00d41611,
+	/*02b4*/ 0x0031002e,
+	/*02b5*/ 0x16111136,
+	/*02b6*/ 0x002e00d4,
+	/*02b7*/ 0x11360031,
+	/*02b8*/ 0x00001611,
+	/*02b9*/ 0x00018d00,
+	/*02ba*/ 0x018d018d,
+	/*02bb*/ 0x1d220c08,
+	/*02bc*/ 0x00001f12,
+	/*02bd*/ 0x4301b344,
+	/*02be*/ 0x17032006,
+	/*02bf*/ 0x220c1010,
+	/*02c0*/ 0x001f121d,
+	/*02c1*/ 0x4301b344,
+	/*02c2*/ 0x17062006,
+	/*02c3*/ 0x220c1010,
+	/*02c4*/ 0x001f121d,
+	/*02c5*/ 0x4301b344,
+	/*02c6*/ 0x17182006,
+	/*02c7*/ 0x00021010,
+	/*02c8*/ 0x00020002,
+	/*02c9*/ 0x00020002,
+	/*02ca*/ 0x00020002,
+	/*02cb*/ 0x00020002,
+	/*02cc*/ 0x00000002,
+	/*02cd*/ 0x00000000,
+	/*02ce*/ 0x00000000,
+	/*02cf*/ 0x00000000,
+	/*02d0*/ 0x00000000,
+	/*02d1*/ 0x00000000,
+	/*02d2*/ 0x00000000,
+	/*02d3*/ 0x00000000,
+	/*02d4*/ 0x00000000,
+	/*02d5*/ 0x00000000,
+	/*02d6*/ 0x00000000,
+	/*02d7*/ 0x00000000,
+	/*02d8*/ 0x00000000,
+	/*02d9*/ 0x00000400,
+	/*02da*/ 0x15141312,
+	/*02db*/ 0x11100f0e,
+	/*02dc*/ 0x080b0c0d,
+	/*02dd*/ 0x05040a09,
+	/*02de*/ 0x01000706,
+	/*02df*/ 0x00000302,
+	/*02e0*/ 0x01030201,
+	/*02e1*/ 0x00304c08,
+	/*02e2*/ 0x0001e2f8,
+	/*02e3*/ 0x0000304c,
+	/*02e4*/ 0x0001e2f8,
+	/*02e5*/ 0x0000304c,
+	/*02e6*/ 0x0001e2f8,
+	/*02e7*/ 0x08000000,
+	/*02e8*/ 0x00000100,
+	/*02e9*/ 0x00000000,
+	/*02ea*/ 0x00000000,
+	/*02eb*/ 0x00000000,
+	/*02ec*/ 0x00000000,
+	/*02ed*/ 0x00010000,
+	/*02ee*/ 0x00000000,
+	/*02ef*/ 0x00000000,
+	/*02f0*/ 0x00000000,
+	/*02f1*/ 0x00000000,
+	/*02f2*/ 0x00000000,
+	/*02f3*/ 0x00000000,
+	/*02f4*/ 0x00000000,
+	/*02f5*/ 0x00000000,
+	/*02f6*/ 0x00000000,
+	/*02f7*/ 0x00000000,
+	/*02f8*/ 0x00000000,
+	/*02f9*/ 0x00000000,
+	/*02fa*/ 0x00000000,
+	/*02fb*/ 0x00000000,
+	/*02fc*/ 0x00000000,
+	/*02fd*/ 0x00000000,
+	/*02fe*/ 0x00000000,
+	/*02ff*/ 0x00000000,
+	/*0300*/ 0x00000000,
+	/*0301*/ 0x00000000,
+	/*0302*/ 0x00000000,
+	/*0303*/ 0x00000000,
+	/*0304*/ 0x00000000,
+	/*0305*/ 0x00000000,
+	/*0306*/ 0x00000000,
+	/*0307*/ 0x00000000,
+	/*0308*/ 0x00000000,
+	/*0309*/ 0x00000000,
+	/*030a*/ 0x00000000,
+	/*030b*/ 0x00000000,
+	/*030c*/ 0x00000000,
+	/*030d*/ 0x00000000,
+	/*030e*/ 0x00000000,
+	/*030f*/ 0x00050002,
+	/*0310*/ 0x015c0057,
+	/*0311*/ 0x01000100,
+	/*0312*/ 0x01020001,
+	/*0313*/ 0x00010300,
+	/*0314*/ 0x05000104,
+	/*0315*/ 0x01060001,
+	/*0316*/ 0x00010700,
+	/*0317*/ 0x00000000,
+	/*0318*/ 0x00000000,
+	/*0319*/ 0x00000001,
+	/*031a*/ 0x00000000,
+	/*031b*/ 0x00000000,
+	/*031c*/ 0x00000000,
+	/*031d*/ 0x20080101
+};
diff --git a/drivers/staging/renesas/rcar/ddr/ddr_b/boot_init_dram_regdef.h b/drivers/renesas/rcar/ddr/ddr_regs.h
index a1cbfbf9c..ba26c69c8 100644
--- a/drivers/staging/renesas/rcar/ddr/ddr_b/boot_init_dram_regdef.h
+++ b/drivers/renesas/rcar/ddr/ddr_regs.h
@@ -1,78 +1,18 @@
 /*
- * Copyright (c) 2015-2019, Renesas Electronics Corporation. All rights reserved.
+ * Copyright (c) 2015-2019, Renesas Electronics Corporation
+ * All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
 
-#define RCAR_DDR_VERSION	"rev.0.36"
-#define DRAM_CH_CNT		(0x04)
-#define SLICE_CNT		(0x04)
-#define CS_CNT			(0x02)
-
-/* order : CS0A, CS0B, CS1A, CS1B */
-#define CSAB_CNT		(CS_CNT * 2)
-
-/* order : CH0A, CH0B, CH1A, CH1B, CH2A, CH2B, CH3A, CH3B */
-#define CHAB_CNT		(DRAM_CH_CNT * 2)
-
-/* pll setting */
-#define CLK_DIV(a, diva, b, divb) (((a) * (divb)) /((b) * (diva)))
-#define CLK_MUL(a, diva, b, divb) (((a) * (b)) / ((diva) * (divb)))
-
-/* for ddr deisity setting */
-#define DBMEMCONF_REG(d3, row, bank, col, dw) 	\
-	((d3) << 30 | ((row) << 24) | ((bank) << 16) | ((col) << 8) | (dw))
-
-#define DBMEMCONF_REGD(density) 		\
-(DBMEMCONF_REG((density) % 2, ((density) + 1) / 2 + (29-3-10-2), 3, 10, 2))
-
-#define DBMEMCONF_VAL(ch, cs) (DBMEMCONF_REGD(DBMEMCONF_DENS(ch, cs)))
-
-/* refresh mode */
-#define DBSC_REFINTS		(0x0)
-
-/* system registers */
-#define CPG_BASE		(0xE6150000U)
-#define CPG_FRQCRB		(CPG_BASE + 0x0004U)
-
-#define CPG_PLLECR		(CPG_BASE + 0x00D0U)
-#define CPG_MSTPSR5		(CPG_BASE + 0x003CU)
-#define CPG_SRCR4		(CPG_BASE + 0x00BCU)
-#define CPG_PLL3CR		(CPG_BASE + 0x00DCU)
-#define CPG_ZB3CKCR		(CPG_BASE + 0x0380U)
-#define CPG_FRQCRD		(CPG_BASE + 0x00E4U)
-#define CPG_SMSTPCR5		(CPG_BASE + 0x0144U)
-#define CPG_CPGWPR		(CPG_BASE + 0x0900U)
-#define CPG_SRSTCLR4		(CPG_BASE + 0x0950U)
-
-#define CPG_FRQCRB_KICK_BIT	(1U<<31)
-#define CPG_PLLECR_PLL3E_BIT	(1U<<3)
-#define CPG_PLLECR_PLL3ST_BIT	(1U<<11)
-#define CPG_ZB3CKCR_ZB3ST_BIT	(1U<<11)
-
-#define RST_BASE		(0xE6160000U)
-#define RST_MODEMR		(RST_BASE + 0x0060U)
-
-#define LIFEC_CHIPID(x)		(0xE6110040U + 0x04U * (x))
-
-/* Product Register */
-#define PRR			(0xFFF00044U)
-#define PRR_PRODUCT_MASK	(0x00007F00U)
-#define PRR_CUT_MASK		(0x000000FFU)
-#define PRR_PRODUCT_H3		(0x00004F00U)	/* R-Car H3   */
-#define PRR_PRODUCT_M3		(0x00005200U)	/* R-Car M3-W */
-#define PRR_PRODUCT_M3N		(0x00005500U)	/* R-Car M3-N */
-#define PRR_PRODUCT_V3H		(0x00005600U)	/* R-Car V3H  */
-#define PRR_PRODUCT_10		(0x00U)	/*   Ver.1.0  */
-#define PRR_PRODUCT_11		(0x01U)	/*   Ver.1.1  */
-#define PRR_PRODUCT_20		(0x10U)	/*   Ver.2.0  */
-#define PRR_PRODUCT_30		(0x20U)	/*   Ver.3.0  */
+#ifndef BOOT_INIT_DRAM_REGDEF_H_
+#define BOOT_INIT_DRAM_REGDEF_H_
 
 /* DBSC registers */
+#define DBSC_DBSYSCONF0		0xE6790000U
 #define DBSC_DBSYSCONF1		0xE6790004U
 #define DBSC_DBPHYCONF0		0xE6790010U
 #define DBSC_DBKIND		0xE6790020U
-
 #define DBSC_DBMEMCONF(ch, cs)	(0xE6790030U + 0x10U * (ch) + 0x04U * (cs))
 #define DBSC_DBMEMCONF_0_0	0xE6790030U
 #define DBSC_DBMEMCONF_0_1	0xE6790034U
@@ -90,18 +30,21 @@
 #define DBSC_DBMEMCONF_3_1	0xE6790064U
 #define DBSC_DBMEMCONF_3_2	0xE6790068U
 #define DBSC_DBMEMCONF_3_3	0xE679006CU
-
 #define DBSC_DBSYSCNT0		0xE6790100U
-
+#define DBSC_DBSVCR1		0xE6790104U
+#define DBSC_DBSTATE0		0xE6790108U
+#define DBSC_DBSTATE1		0xE679010CU
+#define DBSC_DBINTEN		0xE6790180U
+#define DBSC_DBINTSTAT0		0xE6790184U
 #define DBSC_DBACEN		0xE6790200U
 #define DBSC_DBRFEN		0xE6790204U
 #define DBSC_DBCMD		0xE6790208U
 #define DBSC_DBWAIT		0xE6790210U
 #define DBSC_DBSYSCTRL0		0xE6790280U
-
 #define DBSC_DBTR(x)		(0xE6790300U + 0x04U * (x))
 #define DBSC_DBTR0		0xE6790300U
 #define DBSC_DBTR1		0xE6790304U
+#define DBSC_DBTR2		0xE6790308U
 #define DBSC_DBTR3		0xE679030CU
 #define DBSC_DBTR4		0xE6790310U
 #define DBSC_DBTR5		0xE6790314U
@@ -126,7 +69,6 @@
 #define DBSC_DBTR24		0xE6790360U
 #define DBSC_DBTR25		0xE6790364U
 #define DBSC_DBTR26		0xE6790368U
-
 #define DBSC_DBBL		0xE6790400U
 #define DBSC_DBRFCNF1		0xE6790414U
 #define DBSC_DBRFCNF2		0xE6790418U
@@ -137,55 +79,55 @@
 #define DBSC_DBRNK3		0xE679043CU
 #define DBSC_DBRNK4		0xE6790440U
 #define DBSC_DBRNK5		0xE6790444U
+#define DBSC_DBPDNCNF		0xE6790450U
 #define DBSC_DBODT(x)		(0xE6790460U + 0x04U * (x))
-
+#define DBSC_DBODT0		0xE6790460U
+#define DBSC_DBODT1		0xE6790464U
+#define DBSC_DBODT2		0xE6790468U
+#define DBSC_DBODT3		0xE679046CU
+#define DBSC_DBODT4		0xE6790470U
+#define DBSC_DBODT5		0xE6790474U
+#define DBSC_DBODT6		0xE6790478U
+#define DBSC_DBODT7		0xE679047CU
 #define DBSC_DBADJ0		0xE6790500U
 #define DBSC_DBDBICNT		0xE6790518U
 #define DBSC_DBDFIPMSTRCNF	0xE6790520U
 #define DBSC_DBDFICUPDCNF	0xE679052CU
-
 #define DBSC_DBDFISTAT(ch)	(0xE6790600U + 0x40U * (ch))
-#define DBSC_DBDFISTAT_0		0xE6790600U
-#define DBSC_DBDFISTAT_1		0xE6790640U
-#define DBSC_DBDFISTAT_2		0xE6790680U
-#define DBSC_DBDFISTAT_3		0xE67906C0U
-
+#define DBSC_DBDFISTAT_0	0xE6790600U
+#define DBSC_DBDFISTAT_1	0xE6790640U
+#define DBSC_DBDFISTAT_2	0xE6790680U
+#define DBSC_DBDFISTAT_3	0xE67906C0U
 #define DBSC_DBDFICNT(ch)	(0xE6790604U + 0x40U * (ch))
 #define DBSC_DBDFICNT_0		0xE6790604U
 #define DBSC_DBDFICNT_1		0xE6790644U
 #define DBSC_DBDFICNT_2		0xE6790684U
 #define DBSC_DBDFICNT_3		0xE67906C4U
-
 #define DBSC_DBPDCNT0(ch)	(0xE6790610U + 0x40U * (ch))
 #define DBSC_DBPDCNT0_0		0xE6790610U
 #define DBSC_DBPDCNT0_1		0xE6790650U
 #define DBSC_DBPDCNT0_2		0xE6790690U
 #define DBSC_DBPDCNT0_3		0xE67906D0U
-
 #define DBSC_DBPDCNT1(ch)	(0xE6790614U + 0x40U * (ch))
 #define DBSC_DBPDCNT1_0		0xE6790614U
 #define DBSC_DBPDCNT1_1		0xE6790654U
 #define DBSC_DBPDCNT1_2		0xE6790694U
 #define DBSC_DBPDCNT1_3		0xE67906D4U
-
 #define DBSC_DBPDCNT2(ch)	(0xE6790618U + 0x40U * (ch))
 #define DBSC_DBPDCNT2_0		0xE6790618U
 #define DBSC_DBPDCNT2_1		0xE6790658U
 #define DBSC_DBPDCNT2_2		0xE6790698U
 #define DBSC_DBPDCNT2_3		0xE67906D8U
-
 #define DBSC_DBPDCNT3(ch)	(0xE679061CU + 0x40U * (ch))
 #define DBSC_DBPDCNT3_0		0xE679061CU
 #define DBSC_DBPDCNT3_1		0xE679065CU
 #define DBSC_DBPDCNT3_2		0xE679069CU
 #define DBSC_DBPDCNT3_3		0xE67906DCU
-
 #define DBSC_DBPDLK(ch)		(0xE6790620U + 0x40U * (ch))
 #define DBSC_DBPDLK_0		0xE6790620U
 #define DBSC_DBPDLK_1		0xE6790660U
 #define DBSC_DBPDLK_2		0xE67906a0U
 #define DBSC_DBPDLK_3		0xE67906e0U
-
 #define DBSC_DBPDRGA(ch)	(0xE6790624U + 0x40U * (ch))
 #define DBSC_DBPDRGD(ch)	(0xE6790628U + 0x40U * (ch))
 #define DBSC_DBPDRGA_0		0xE6790624U
@@ -196,16 +138,13 @@
 #define DBSC_DBPDRGD_2		0xE67906A8U
 #define DBSC_DBPDRGA_3		0xE67906E4U
 #define DBSC_DBPDRGD_3		0xE67906E8U
-
 #define DBSC_DBPDSTAT(ch)	(0xE6790630U + 0x40U * (ch))
 #define DBSC_DBPDSTAT_0		0xE6790630U
 #define DBSC_DBPDSTAT_1		0xE6790670U
 #define DBSC_DBPDSTAT_2		0xE67906B0U
 #define DBSC_DBPDSTAT_3		0xE67906F0U
-
 #define DBSC_DBBUS0CNF0		0xE6790800U
 #define DBSC_DBBUS0CNF1		0xE6790804U
-
 #define DBSC_DBCAM0CNF1		0xE6790904U
 #define DBSC_DBCAM0CNF2		0xE6790908U
 #define DBSC_DBCAM0CNF3		0xE679090CU
@@ -216,21 +155,81 @@
 #define DBSC_DBSCHSZ0		0xE6791010U
 #define DBSC_DBSCHRW0		0xE6791020U
 #define DBSC_DBSCHRW1		0xE6791024U
-
-#define DBSC_DBSCHQOS_0(x)	(0xE6791030U +0x10U * (x))
-#define DBSC_DBSCHQOS_1(x)	(0xE6791034U +0x10U * (x))
-#define DBSC_DBSCHQOS_2(x)	(0xE6791038U +0x10U * (x))
-#define DBSC_DBSCHQOS_3(x)	(0xE679103CU +0x10U * (x))
-
+#define DBSC_DBSCHQOS_0(x)	(0xE6791030U + 0x10U * (x))
+#define DBSC_DBSCHQOS_1(x)	(0xE6791034U + 0x10U * (x))
+#define DBSC_DBSCHQOS_2(x)	(0xE6791038U + 0x10U * (x))
+#define DBSC_DBSCHQOS_3(x)	(0xE679103CU + 0x10U * (x))
+#define DBSC_DBSCHQOS00		0xE6791030U
+#define DBSC_DBSCHQOS01		0xE6791034U
+#define DBSC_DBSCHQOS02		0xE6791038U
+#define DBSC_DBSCHQOS03		0xE679103CU
+#define DBSC_DBSCHQOS10		0xE6791040U
+#define DBSC_DBSCHQOS11		0xE6791044U
+#define DBSC_DBSCHQOS12		0xE6791048U
+#define DBSC_DBSCHQOS13		0xE679104CU
+#define DBSC_DBSCHQOS20		0xE6791050U
+#define DBSC_DBSCHQOS21		0xE6791054U
+#define DBSC_DBSCHQOS22		0xE6791058U
+#define DBSC_DBSCHQOS23		0xE679105CU
+#define DBSC_DBSCHQOS30		0xE6791060U
+#define DBSC_DBSCHQOS31		0xE6791064U
+#define DBSC_DBSCHQOS32		0xE6791068U
+#define DBSC_DBSCHQOS33		0xE679106CU
+#define DBSC_DBSCHQOS40		0xE6791070U
+#define DBSC_DBSCHQOS41		0xE6791074U
+#define DBSC_DBSCHQOS42		0xE6791078U
+#define DBSC_DBSCHQOS43		0xE679107CU
+#define DBSC_DBSCHQOS50		0xE6791080U
+#define DBSC_DBSCHQOS51		0xE6791084U
+#define DBSC_DBSCHQOS52		0xE6791088U
+#define DBSC_DBSCHQOS53		0xE679108CU
+#define DBSC_DBSCHQOS60		0xE6791090U
+#define DBSC_DBSCHQOS61		0xE6791094U
+#define DBSC_DBSCHQOS62		0xE6791098U
+#define DBSC_DBSCHQOS63		0xE679109CU
+#define DBSC_DBSCHQOS70		0xE67910A0U
+#define DBSC_DBSCHQOS71		0xE67910A4U
+#define DBSC_DBSCHQOS72		0xE67910A8U
+#define DBSC_DBSCHQOS73		0xE67910ACU
+#define DBSC_DBSCHQOS80		0xE67910B0U
+#define DBSC_DBSCHQOS81		0xE67910B4U
+#define DBSC_DBSCHQOS82		0xE67910B8U
+#define DBSC_DBSCHQOS83		0xE67910BCU
+#define DBSC_DBSCHQOS90		0xE67910C0U
+#define DBSC_DBSCHQOS91		0xE67910C4U
+#define DBSC_DBSCHQOS92		0xE67910C8U
+#define DBSC_DBSCHQOS93		0xE67910CCU
+#define DBSC_DBSCHQOS100	0xE67910D0U
+#define DBSC_DBSCHQOS101	0xE67910D4U
+#define DBSC_DBSCHQOS102	0xE67910D8U
+#define DBSC_DBSCHQOS103	0xE67910DCU
+#define DBSC_DBSCHQOS110	0xE67910E0U
+#define DBSC_DBSCHQOS111	0xE67910E4U
+#define DBSC_DBSCHQOS112	0xE67910E8U
+#define DBSC_DBSCHQOS113	0xE67910ECU
+#define DBSC_DBSCHQOS120	0xE67910F0U
+#define DBSC_DBSCHQOS121	0xE67910F4U
+#define DBSC_DBSCHQOS122	0xE67910F8U
+#define DBSC_DBSCHQOS123	0xE67910FCU
+#define DBSC_DBSCHQOS130	0xE6791100U
+#define DBSC_DBSCHQOS131	0xE6791104U
+#define DBSC_DBSCHQOS132	0xE6791108U
+#define DBSC_DBSCHQOS133	0xE679110CU
+#define DBSC_DBSCHQOS140	0xE6791110U
+#define DBSC_DBSCHQOS141	0xE6791114U
+#define DBSC_DBSCHQOS142	0xE6791118U
+#define DBSC_DBSCHQOS143	0xE679111CU
+#define DBSC_DBSCHQOS150	0xE6791120U
+#define DBSC_DBSCHQOS151	0xE6791124U
+#define DBSC_DBSCHQOS152	0xE6791128U
+#define DBSC_DBSCHQOS153	0xE679112CU
 #define DBSC_DBSCTR0		0xE6791700U
 #define DBSC_DBSCTR1		0xE6791708U
 #define DBSC_DBSCHRW2		0xE679170CU
-
 #define DBSC_SCFCTST01(x)	(0xE6791700U + 0x08U * (x))
 #define DBSC_SCFCTST0		0xE6791700U
 #define DBSC_SCFCTST1		0xE6791708U
 #define DBSC_SCFCTST2		0xE679170CU
-
 #define DBSC_DBMRRDR(chab)	(0xE6791800U + 0x04U * (chab))
 #define DBSC_DBMRRDR_0		0xE6791800U
 #define DBSC_DBMRRDR_1		0xE6791804U
@@ -240,70 +239,19 @@
 #define DBSC_DBMRRDR_5		0xE6791814U
 #define DBSC_DBMRRDR_6		0xE6791818U
 #define DBSC_DBMRRDR_7		0xE679181CU
-
 #define DBSC_DBMEMSWAPCONF0	0xE6792000U
 
-#define DBSC_DBMONCONF4		0xE6793010U
-
-#define DBSC_PLL_LOCK(ch)	(0xE6794054U + 0x100U * (ch))
-#define DBSC_PLL_LOCK_0		0xE6794054U
-#define DBSC_PLL_LOCK_1		0xE6794154U
-#define DBSC_PLL_LOCK_2		0xE6794254U
-#define DBSC_PLL_LOCK_3		0xE6794354U
-
-/* STAT registers */
-#define MSTAT_SL_INIT		0xE67E8000U
-#define MSTAT_REF_ARS		0xE67E8004U
-#define MSTATQ_STATQC		0xE67E8008U
-#define MSTATQ_WTENABLE		0xE67E8030U
-#define MSTATQ_WTREFRESH	0xE67E8034U
-#define MSTATQ_WTSETTING0	0xE67E8038U
-#define MSTATQ_WTSETTING1	0xE67E803CU
-
-#define QOS_BASE1		(0xE67F0000U)
-#define QOSCTRL_RAS		(QOS_BASE1 + 0x0000U)
-#define QOSCTRL_FIXTH		(QOS_BASE1 + 0x0004U)
-#define QOSCTRL_RAEN		(QOS_BASE1 + 0x0018U)
-#define QOSCTRL_REGGD		(QOS_BASE1 + 0x0020U)
-#define QOSCTRL_DANN		(QOS_BASE1 + 0x0030U)
-#define QOSCTRL_DANT		(QOS_BASE1 + 0x0038U)
-#define QOSCTRL_EC		(QOS_BASE1 + 0x003CU)
-#define QOSCTRL_EMS		(QOS_BASE1 + 0x0040U)
-#define QOSCTRL_INSFC		(QOS_BASE1 + 0x0050U)
-#define QOSCTRL_BERR		(QOS_BASE1 + 0x0054U)
-#define QOSCTRL_RACNT0		(QOS_BASE1 + 0x0080U)
-#define QOSCTRL_STATGEN0	(QOS_BASE1 + 0x0088U)
-
-/* other module */
-#define THS1_THCTR		0xE6198020U
-#define THS1_TEMP		0xE6198028U
+/* CPG registers */
+#define CPG_BASE		0xE6150000U
+#define CPG_FRQCRB		(CPG_BASE + 0x0004U)
+#define CPG_PLLECR		(CPG_BASE + 0x00D0U)
+#define CPG_MSTPSR5		(CPG_BASE + 0x003CU)
+#define CPG_SRCR4		(CPG_BASE + 0x00BCU)
+#define CPG_PLL3CR		(CPG_BASE + 0x00DCU)
+#define CPG_ZB3CKCR		(CPG_BASE + 0x0380U)
+#define CPG_FRQCRD		(CPG_BASE + 0x00E4U)
+#define CPG_SMSTPCR5		(CPG_BASE + 0x0144U)
+#define CPG_CPGWPR		(CPG_BASE + 0x0900U)
+#define CPG_SRSTCLR4		(CPG_BASE + 0x0950U)
 
-#define	DBSC_BASE		(0xE6790000U)
-#define DBSC_DBSCHQOS00		(DBSC_BASE + 0x1030U)
-#define DBSC_DBSCHQOS01		(DBSC_BASE + 0x1034U)
-#define DBSC_DBSCHQOS02		(DBSC_BASE + 0x1038U)
-#define DBSC_DBSCHQOS03		(DBSC_BASE + 0x103CU)
-#define DBSC_DBSCHQOS40		(DBSC_BASE + 0x1070U)
-#define DBSC_DBSCHQOS41		(DBSC_BASE + 0x1074U)
-#define DBSC_DBSCHQOS42		(DBSC_BASE + 0x1078U)
-#define DBSC_DBSCHQOS43		(DBSC_BASE + 0x107CU)
-#define DBSC_DBSCHQOS90		(DBSC_BASE + 0x10C0U)
-#define DBSC_DBSCHQOS91		(DBSC_BASE + 0x10C4U)
-#define DBSC_DBSCHQOS92		(DBSC_BASE + 0x10C8U)
-#define DBSC_DBSCHQOS93		(DBSC_BASE + 0x10CCU)
-#define DBSC_DBSCHQOS120	(DBSC_BASE + 0x10F0U)
-#define DBSC_DBSCHQOS121	(DBSC_BASE + 0x10F4U)
-#define DBSC_DBSCHQOS122	(DBSC_BASE + 0x10F8U)
-#define DBSC_DBSCHQOS123	(DBSC_BASE + 0x10FCU)
-#define DBSC_DBSCHQOS130	(DBSC_BASE + 0x1100U)
-#define DBSC_DBSCHQOS131	(DBSC_BASE + 0x1104U)
-#define DBSC_DBSCHQOS132	(DBSC_BASE + 0x1108U)
-#define DBSC_DBSCHQOS133	(DBSC_BASE + 0x110CU)
-#define DBSC_DBSCHQOS140	(DBSC_BASE + 0x1110U)
-#define DBSC_DBSCHQOS141	(DBSC_BASE + 0x1114U)
-#define DBSC_DBSCHQOS142	(DBSC_BASE + 0x1118U)
-#define DBSC_DBSCHQOS143	(DBSC_BASE + 0x111CU)
-#define DBSC_DBSCHQOS150	(DBSC_BASE + 0x1120U)
-#define DBSC_DBSCHQOS151	(DBSC_BASE + 0x1124U)
-#define DBSC_DBSCHQOS152	(DBSC_BASE + 0x1128U)
-#define DBSC_DBSCHQOS153	(DBSC_BASE + 0x112CU)
+#endif /* BOOT_INIT_DRAM_REGDEF_H_*/
diff --git a/drivers/staging/renesas/rcar/ddr/dram_sub_func.c b/drivers/renesas/rcar/ddr/dram_sub_func.c
index 6739b0dd3..ab8eabbc6 100644
--- a/drivers/staging/renesas/rcar/ddr/dram_sub_func.c
+++ b/drivers/renesas/rcar/ddr/dram_sub_func.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2015-2018, Renesas Electronics Corporation. All rights reserved.
+ * Copyright (c) 2015-2019, Renesas Electronics Corporation. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -8,52 +8,34 @@
 #include <lib/mmio.h>
 
 #include "dram_sub_func.h"
-
-#define PRR				(0xFFF00044U)
-#define PRR_PRODUCT_MASK		(0x00007F00U)
-#define PRR_CUT_MASK			(0x000000FFU)
-#define PRR_PRODUCT_H3			(0x00004F00U)	/* R-Car H3  */
-#define PRR_PRODUCT_M3			(0x00005200U)	/* R-Car M3  */
-#define PRR_PRODUCT_M3N			(0x00005500U)	/* R-Car M3N */
-#define PRR_PRODUCT_E3			(0x00005700U)	/* R-Car E3  */
-#define PRR_PRODUCT_V3H			(0x00005600U)	/* R-Car V3H */
+#include "rcar_def.h"
 
 #if RCAR_SYSTEM_SUSPEND
 /* Local defines */
-#define DRAM_BACKUP_GPIO_USE		(0)
+#define DRAM_BACKUP_GPIO_USE		0
 #include "iic_dvfs.h"
 #if PMIC_ROHM_BD9571
-#define	PMIC_SLAVE_ADDR			(0x30U)
-#define	PMIC_BKUP_MODE_CNT		(0x20U)
-#define	PMIC_QLLM_CNT			(0x27U)
-#define	BIT_BKUP_CTRL_OUT		((uint8_t)(1U << 4U))
-#define	BIT_QLLM_DDR0_EN		((uint8_t)(1U << 0U))
-#define	BIT_QLLM_DDR1_EN		((uint8_t)(1U << 1U))
+#define	PMIC_SLAVE_ADDR			0x30U
+#define	PMIC_BKUP_MODE_CNT		0x20U
+#define	PMIC_QLLM_CNT			0x27U
+#define	BIT_BKUP_CTRL_OUT		BIT(4)
+#define	BIT_QLLM_DDR0_EN		BIT(0)
+#define	BIT_QLLM_DDR1_EN		BIT(1)
 #endif
 
-#define	GPIO_OUTDT1			(0xE6051008U)
-#define GPIO_INDT1			(0xE605100CU)
-#define GPIO_OUTDT3			(0xE6053008U)
-#define GPIO_INDT3			(0xE605300CU)
-#define GPIO_OUTDT6			(0xE6055408U)
-#define GPIO_INDT6			(0xE605540CU)
+#define GPIO_BKUP_REQB_SHIFT_SALVATOR	9U	/* GP1_9 (BKUP_REQB) */
+#define GPIO_BKUP_TRG_SHIFT_SALVATOR	8U	/* GP1_8 (BKUP_TRG) */
+#define GPIO_BKUP_REQB_SHIFT_EBISU	14U	/* GP6_14(BKUP_REQB) */
+#define GPIO_BKUP_TRG_SHIFT_EBISU	13U	/* GP6_13(BKUP_TRG) */
+#define GPIO_BKUP_REQB_SHIFT_CONDOR	1U	/* GP3_1 (BKUP_REQB) */
+#define GPIO_BKUP_TRG_SHIFT_CONDOR	0U	/* GP3_0 (BKUP_TRG) */
 
-#if DRAM_BACKUP_GPIO_USE == 1
-#define GPIO_BKUP_REQB_SHIFT_SALVATOR	(9U)	/* GP1_9 (BKUP_REQB) */
-#define GPIO_BKUP_REQB_SHIFT_EBISU	(14U)	/* GP6_14(BKUP_REQB) */
-#define GPIO_BKUP_REQB_SHIFT_CONDOR	(1U)	/* GP3_1 (BKUP_REQB) */
+#define DRAM_BKUP_TRG_LOOP_CNT		1000U
 #endif
-#define GPIO_BKUP_TRG_SHIFT_SALVATOR	(8U)	/* GP1_8 (BKUP_TRG) */
-#define GPIO_BKUP_TRG_SHIFT_EBISU	(13U)	/* GP6_13(BKUP_TRG) */
-#define GPIO_BKUP_TRG_SHIFT_CONDOR	(0U)	/* GP3_0 (BKUP_TRG) */
 
-#define DRAM_BKUP_TRG_LOOP_CNT	(1000U)
-#endif
-
-void rcar_dram_get_boot_status(uint32_t * status)
+void rcar_dram_get_boot_status(uint32_t *status)
 {
 #if RCAR_SYSTEM_SUSPEND
-
 	uint32_t reg_data;
 	uint32_t product;
 	uint32_t shift;
@@ -72,11 +54,10 @@ void rcar_dram_get_boot_status(uint32_t * status)
 	}
 
 	reg_data = mmio_read_32(gpio);
-	if (0U != (reg_data & ((uint32_t)1U << shift))) {
+	if (reg_data & BIT(shift))
 		*status = DRAM_BOOT_STATUS_WARM;
-	} else {
+	else
 		*status = DRAM_BOOT_STATUS_COLD;
-	}
 #else	/* RCAR_SYSTEM_SUSPEND */
 	*status = DRAM_BOOT_STATUS_COLD;
 #endif	/* RCAR_SYSTEM_SUSPEND */
@@ -126,55 +107,55 @@ int32_t rcar_dram_update_boot_status(uint32_t status)
 	}
 
 	if (status == DRAM_BOOT_STATUS_WARM) {
-#if DRAM_BACKUP_GPIO_USE==1
-	mmio_setbits_32(outd, 1U << reqb);
+#if DRAM_BACKUP_GPIO_USE == 1
+		mmio_setbits_32(outd, BIT(reqb));
 #else
 #if PMIC_ROHM_BD9571
 		/* Set BKUP_CRTL_OUT=High (BKUP mode cnt register) */
 		i2c_dvfs_ret = rcar_iic_dvfs_receive(PMIC_SLAVE_ADDR,
-				PMIC_BKUP_MODE_CNT, &bkup_mode_cnt);
-		if (0 != i2c_dvfs_ret) {
+						     PMIC_BKUP_MODE_CNT,
+						     &bkup_mode_cnt);
+		if (i2c_dvfs_ret) {
 			ERROR("BKUP mode cnt READ ERROR.\n");
 			ret = DRAM_UPDATE_STATUS_ERR;
 		} else {
 			bkup_mode_cnt &= (uint8_t)~BIT_BKUP_CTRL_OUT;
 			i2c_dvfs_ret = rcar_iic_dvfs_send(PMIC_SLAVE_ADDR,
-					PMIC_BKUP_MODE_CNT, bkup_mode_cnt);
-			if (0 != i2c_dvfs_ret) {
-				ERROR("BKUP mode cnt WRITE ERROR. "
-					"value = %d\n", bkup_mode_cnt);
+							  PMIC_BKUP_MODE_CNT,
+							  bkup_mode_cnt);
+			if (i2c_dvfs_ret) {
+				ERROR("BKUP mode cnt WRITE ERROR. value = %d\n",
+				      bkup_mode_cnt);
 				ret = DRAM_UPDATE_STATUS_ERR;
 			}
 		}
 #endif /* PMIC_ROHM_BD9571 */
-#endif /* DRAM_BACKUP_GPIO_USE==1 */
+#endif /* DRAM_BACKUP_GPIO_USE == 1 */
 		/* Wait BKUP_TRG=Low */
 		loop_count = DRAM_BKUP_TRG_LOOP_CNT;
-		while (0U < loop_count) {
+		while (loop_count > 0) {
 			reg_data = mmio_read_32(gpio);
-			if ((reg_data &
-				((uint32_t)1U << trg)) == 0U) {
+			if (!(reg_data & BIT(trg)))
 				break;
-			}
 			loop_count--;
 		}
-		if (0U == loop_count) {
-			ERROR(	"\nWarm booting...\n" \
-				" The potential of BKUP_TRG did not switch " \
-				"to Low.\n If you expect the operation of " \
-				"cold boot,\n check the board configuration" \
-				" (ex, Dip-SW) and/or the H/W failure.\n");
+
+		if (!loop_count) {
+			ERROR("\nWarm booting...\n"
+			      " The potential of BKUP_TRG did not switch to Low.\n"
+			      " If you expect the operation of cold boot,\n"
+			      " check the board configuration (ex, Dip-SW) and/or the H/W failure.\n");
 			ret = DRAM_UPDATE_STATUS_ERR;
 		}
 	}
 #if PMIC_ROHM_BD9571
-	if(0 == ret) {
-		qllm_cnt = (BIT_QLLM_DDR0_EN | BIT_QLLM_DDR1_EN);
+	if (!ret) {
+		qllm_cnt = BIT_QLLM_DDR0_EN | BIT_QLLM_DDR1_EN;
 		i2c_dvfs_ret = rcar_iic_dvfs_send(PMIC_SLAVE_ADDR,
-				PMIC_QLLM_CNT, qllm_cnt);
-		if (0 != i2c_dvfs_ret) {
-			ERROR("QLLM cnt WRITE ERROR. "
-				"value = %d\n", qllm_cnt);
+						  PMIC_QLLM_CNT,
+						  qllm_cnt);
+		if (i2c_dvfs_ret) {
+			ERROR("QLLM cnt WRITE ERROR. value = %d\n", qllm_cnt);
 			ret = DRAM_UPDATE_STATUS_ERR;
 		}
 	}
diff --git a/drivers/renesas/rcar/ddr/dram_sub_func.h b/drivers/renesas/rcar/ddr/dram_sub_func.h
new file mode 100644
index 000000000..69c4d8605
--- /dev/null
+++ b/drivers/renesas/rcar/ddr/dram_sub_func.h
@@ -0,0 +1,17 @@
+/*
+ * Copyright (c) 2015-2019, Renesas Electronics Corporation. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef DRAM_SUB_FUNC_H
+#define DRAM_SUB_FUNC_H
+
+#define DRAM_UPDATE_STATUS_ERR	-1
+#define DRAM_BOOT_STATUS_COLD	0
+#define DRAM_BOOT_STATUS_WARM	1
+
+int32_t rcar_dram_update_boot_status(uint32_t status);
+void rcar_dram_get_boot_status(uint32_t *status);
+
+#endif /* DRAM_SUB_FUNC_H */
diff --git a/drivers/renesas/rcar/emmc/emmc_interrupt.c b/drivers/renesas/rcar/emmc/emmc_interrupt.c
index 37a3cf9d4..2557280cf 100644
--- a/drivers/renesas/rcar/emmc/emmc_interrupt.c
+++ b/drivers/renesas/rcar/emmc/emmc_interrupt.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2015-2018, Renesas Electronics Corporation. All rights
+ * Copyright (c) 2015-2019, Renesas Electronics Corporation. All rights
  * reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
@@ -26,17 +26,17 @@ uint32_t emmc_interrupt(void)
 	uint32_t end_bit;
 
 	prr_data = mmio_read_32((uintptr_t) RCAR_PRR);
-	cut_ver = prr_data & RCAR_CUT_MASK;
-	if ((prr_data & RCAR_PRODUCT_MASK) == RCAR_PRODUCT_H3) {
-		if (cut_ver == RCAR_CUT_VER10) {
+	cut_ver = prr_data & PRR_CUT_MASK;
+	if ((prr_data & PRR_PRODUCT_MASK) == PRR_PRODUCT_H3) {
+		if (cut_ver == PRR_PRODUCT_10) {
 			end_bit = BIT17;
-		} else if (cut_ver == RCAR_CUT_VER11) {
+		} else if (cut_ver == PRR_PRODUCT_11) {
 			end_bit = BIT17;
 		} else {
 			end_bit = BIT20;
 		}
-	} else if ((prr_data & RCAR_PRODUCT_MASK) == RCAR_PRODUCT_M3) {
-		if (cut_ver == RCAR_CUT_VER10) {
+	} else if ((prr_data & PRR_PRODUCT_MASK) == PRR_PRODUCT_M3) {
+		if (cut_ver == PRR_PRODUCT_10) {
 			end_bit = BIT17;
 		} else {
 			end_bit = BIT20;
diff --git a/drivers/renesas/rcar/emmc/emmc_mount.c b/drivers/renesas/rcar/emmc/emmc_mount.c
index dd57b0c24..df8203ea8 100644
--- a/drivers/renesas/rcar/emmc/emmc_mount.c
+++ b/drivers/renesas/rcar/emmc/emmc_mount.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2015-2017, Renesas Electronics Corporation. All rights reserved.
+ * Copyright (c) 2015-2019, Renesas Electronics Corporation. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -29,14 +29,14 @@ static void emmc_set_bootpartition(void)
 {
 	uint32_t reg;
 
-	reg = mmio_read_32(RCAR_PRR) & (RCAR_PRODUCT_MASK | RCAR_CUT_MASK);
-	if (reg == RCAR_PRODUCT_M3_CUT10) {
+	reg = mmio_read_32(RCAR_PRR) & (PRR_PRODUCT_MASK | PRR_CUT_MASK);
+	if (reg == PRR_PRODUCT_M3_CUT10) {
 		mmc_drv_obj.boot_partition_en =
 		    (EMMC_PARTITION_ID) ((mmc_drv_obj.ext_csd_data[179] &
 					  EMMC_BOOT_PARTITION_EN_MASK) >>
 					 EMMC_BOOT_PARTITION_EN_SHIFT);
-	} else if ((reg == RCAR_PRODUCT_H3_CUT20)
-		   || (reg == RCAR_PRODUCT_M3_CUT11)) {
+	} else if ((reg == PRR_PRODUCT_H3_CUT20)
+		   || (reg == PRR_PRODUCT_M3_CUT11)) {
 		mmc_drv_obj.boot_partition_en = mmc_drv_obj.partition_access;
 	} else {
 		if ((mmio_read_32(MFISBTSTSR) & MFISBTSTSR_BOOT_PARTITION) !=
@@ -460,8 +460,8 @@ static void emmc_get_partition_access(void)
 	uint32_t reg;
 	EMMC_ERROR_CODE result;
 
-	reg = mmio_read_32(RCAR_PRR) & (RCAR_PRODUCT_MASK | RCAR_CUT_MASK);
-	if ((reg == RCAR_PRODUCT_H3_CUT20) || (reg == RCAR_PRODUCT_M3_CUT11)) {
+	reg = mmio_read_32(RCAR_PRR) & (PRR_PRODUCT_MASK | PRR_CUT_MASK);
+	if ((reg == PRR_PRODUCT_H3_CUT20) || (reg == PRR_PRODUCT_M3_CUT11)) {
 		SETR_32(SD_OPTION, 0x000060EEU);	/* 8 bits width */
 		/* CMD8 (EXT_CSD) */
 		emmc_make_trans_cmd(CMD8_SEND_EXT_CSD, 0x00000000U,
diff --git a/drivers/renesas/rcar/iic_dvfs/iic_dvfs.c b/drivers/renesas/rcar/iic_dvfs/iic_dvfs.c
index 39b9bb4e3..28b56c10e 100644
--- a/drivers/renesas/rcar/iic_dvfs/iic_dvfs.c
+++ b/drivers/renesas/rcar/iic_dvfs/iic_dvfs.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2015-2018, Renesas Electronics Corporation. All rights reserved.
+ * Copyright (c) 2015-2019, Renesas Electronics Corporation. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -189,8 +189,8 @@ IIC_DVFS_FUNC(start, DVFS_STATE_T * state)
 	mode = mmio_read_8(IIC_DVFS_REG_ICCR) | IIC_DVFS_BIT_ICCR_ENABLE;
 	mmio_write_8(IIC_DVFS_REG_ICCR, mode);
 
-	lsi_product = mmio_read_32(RCAR_PRR) & RCAR_PRODUCT_MASK;
-	if (lsi_product == RCAR_PRODUCT_E3)
+	lsi_product = mmio_read_32(RCAR_PRR) & PRR_PRODUCT_MASK;
+	if (lsi_product == PRR_PRODUCT_E3)
 		goto start;
 
 	reg = mmio_read_32(RCAR_MODEMR) & CHECK_MD13_MD14;
diff --git a/drivers/renesas/rcar/io/io_emmcdrv.c b/drivers/renesas/rcar/io/io_emmcdrv.c
index 4b464fb3e..84240d260 100644
--- a/drivers/renesas/rcar/io/io_emmcdrv.c
+++ b/drivers/renesas/rcar/io/io_emmcdrv.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2015-2017, Renesas Electronics Corporation. All rights reserved.
+ * Copyright (c) 2015-2019, Renesas Electronics Corporation. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -25,7 +25,7 @@ static int32_t emmcdrv_dev_close(io_dev_info_t *dev_info);
 typedef struct {
 	uint32_t in_use;
 	uintptr_t base;
-	ssize_t file_pos;
+	signed long long file_pos;
 	EMMC_PARTITION_ID partition;
 } file_state_t;
 
@@ -39,7 +39,7 @@ static io_type_t device_type_emmcdrv(void)
 }
 
 static int32_t emmcdrv_block_seek(io_entity_t *entity, int32_t mode,
-				  ssize_t offset)
+				  signed long long offset)
 {
 	if (mode != IO_SEEK_SET)
 		return IO_FAIL;
@@ -59,12 +59,12 @@ static int32_t emmcdrv_block_read(io_entity_t *entity, uintptr_t buffer,
 	sector_add = current_file.file_pos >> EMMC_SECTOR_SIZE_SHIFT;
 	sector_num = (length + EMMC_SECTOR_SIZE - 1U) >> EMMC_SECTOR_SIZE_SHIFT;
 
-	NOTICE("BL2: Load dst=0x%lx src=(p:%d)0x%lx(%d) len=0x%lx(%d)\n",
+	NOTICE("BL2: Load dst=0x%lx src=(p:%d)0x%llx(%d) len=0x%lx(%d)\n",
 	       buffer,
 	       current_file.partition, current_file.file_pos,
 	       sector_add, length, sector_num);
 
-	if (buffer + length - 1 <= UINT32_MAX)
+	if ((buffer + length - 1U) <= (uintptr_t)UINT32_MAX)
 		emmc_dma = LOADIMAGE_FLAGS_DMA_ENABLE;
 
 	if (emmc_read_sector((uint32_t *) buffer, sector_add, sector_num,
@@ -72,7 +72,7 @@ static int32_t emmcdrv_block_read(io_entity_t *entity, uintptr_t buffer,
 		result = IO_FAIL;
 
 	*length_read = length;
-	fp->file_pos += length;
+	fp->file_pos += (signed long long)length;
 
 	return result;
 }
@@ -82,7 +82,7 @@ static int32_t emmcdrv_block_open(io_dev_info_t *dev_info,
 {
 	const io_drv_spec_t *block_spec = (io_drv_spec_t *) spec;
 
-	if (current_file.in_use) {
+	if (current_file.in_use != 0U) {
 		WARN("mmc_block: Only one open spec at a time\n");
 		return IO_RESOURCES_EXHAUSTED;
 	}
@@ -103,9 +103,9 @@ static int32_t emmcdrv_block_open(io_dev_info_t *dev_info,
 		return IO_FAIL;
 	}
 
-	if (PARTITION_ID_USER == block_spec->partition ||
-	    PARTITION_ID_BOOT_1 == block_spec->partition ||
-	    PARTITION_ID_BOOT_2 == block_spec->partition)
+	if ((PARTITION_ID_USER == block_spec->partition) ||
+	    (PARTITION_ID_BOOT_1 == block_spec->partition) ||
+	    (PARTITION_ID_BOOT_2 == block_spec->partition))
 		current_file.partition = block_spec->partition;
 	else
 		current_file.partition = emmcdrv_bootpartition;
diff --git a/drivers/renesas/rcar/io/io_memdrv.c b/drivers/renesas/rcar/io/io_memdrv.c
index 3f6b4c71b..7e8c1d3a6 100644
--- a/drivers/renesas/rcar/io/io_memdrv.c
+++ b/drivers/renesas/rcar/io/io_memdrv.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2015-2018, Renesas Electronics Corporation. All rights reserved.
+ * Copyright (c) 2015-2019, Renesas Electronics Corporation. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -28,7 +28,7 @@ static int32_t memdrv_dev_close(io_dev_info_t *dev_info);
 typedef struct {
 	uint32_t in_use;
 	uintptr_t base;
-	ssize_t file_pos;
+	signed long long file_pos;
 } file_state_t;
 
 static file_state_t current_file = { 0 };
@@ -47,7 +47,7 @@ static int32_t memdrv_block_open(io_dev_info_t *dev_info, const uintptr_t spec,
 	 * spec at a time. When we have dynamic memory we can malloc and set
 	 * entity->info.
 	 */
-	if (current_file.in_use)
+	if (current_file.in_use != 0U)
 		return IO_RESOURCES_EXHAUSTED;
 
 	/* File cursor offset for seek and incremental reads etc. */
@@ -61,7 +61,7 @@ static int32_t memdrv_block_open(io_dev_info_t *dev_info, const uintptr_t spec,
 }
 
 static int32_t memdrv_block_seek(io_entity_t *entity, int32_t mode,
-				 ssize_t offset)
+				 signed long long offset)
 {
 	if (mode != IO_SEEK_SET)
 		return IO_FAIL;
@@ -78,16 +78,17 @@ static int32_t memdrv_block_read(io_entity_t *entity, uintptr_t buffer,
 
 	fp = (file_state_t *) entity->info;
 
-	NOTICE("BL2: dst=0x%lx src=0x%lx len=%ld(0x%lx)\n",
-	       buffer, fp->base + fp->file_pos, length, length);
+	NOTICE("BL2: dst=0x%lx src=0x%llx len=%ld(0x%lx)\n",
+	       buffer, (unsigned long long)fp->base +
+	       (unsigned long long)fp->file_pos, length, length);
 
-	if (FLASH_MEMORY_SIZE < fp->file_pos + length) {
+	if (FLASH_MEMORY_SIZE < (fp->file_pos + (signed long long)length)) {
 		ERROR("BL2: check load image (source address)\n");
 		return IO_FAIL;
 	}
 
-	rcar_dma_exec(buffer, fp->base + fp->file_pos, length);
-	fp->file_pos += length;
+	rcar_dma_exec(buffer, fp->base + (uintptr_t)fp->file_pos, length);
+	fp->file_pos += (signed long long)length;
 	*cnt = length;
 
 	return IO_SUCCESS;
diff --git a/drivers/renesas/rcar/io/io_rcar.c b/drivers/renesas/rcar/io/io_rcar.c
index 650931bb4..b82c51078 100644
--- a/drivers/renesas/rcar/io/io_rcar.c
+++ b/drivers/renesas/rcar/io/io_rcar.c
@@ -28,9 +28,6 @@
 extern int32_t plat_get_drv_source(uint32_t id, uintptr_t *dev,
 				   uintptr_t *image_spec);
 
-extern int auth_mod_verify_img(unsigned int img_id, void *ptr,
-				unsigned int len);
-
 static int32_t rcar_dev_open(const uintptr_t dev_spec __attribute__ ((unused)),
 			     io_dev_info_t **dev_info);
 static int32_t rcar_dev_close(io_dev_info_t *dev_info);
diff --git a/drivers/renesas/rcar/pfc/M3/pfc_init_m3.c b/drivers/renesas/rcar/pfc/M3/pfc_init_m3.c
index 0aa3bffce..7684c624a 100644
--- a/drivers/renesas/rcar/pfc/M3/pfc_init_m3.c
+++ b/drivers/renesas/rcar/pfc/M3/pfc_init_m3.c
@@ -615,8 +615,8 @@ static void start_rtdma0_descriptor(void)
 	uint32_t reg;
 
 	reg = mmio_read_32(RCAR_PRR);
-	reg &= (RCAR_PRODUCT_MASK | RCAR_CUT_MASK);
-	if (reg == (RCAR_PRODUCT_M3_CUT10)) {
+	reg &= (PRR_PRODUCT_MASK | PRR_CUT_MASK);
+	if (reg == (PRR_PRODUCT_M3_CUT10)) {
 		/* Enable clock supply to RTDMAC. */
 		mstpcr_write(CPG_SCMSTPCR0, CPG_MSTPSR0, SCMSTPCR0_RTDMAC);
 
@@ -654,14 +654,14 @@ static void pfc_reg_write(uint32_t addr, uint32_t data)
 	uint32_t prr;
 
 	prr = mmio_read_32(RCAR_PRR);
-	prr &= (RCAR_PRODUCT_MASK | RCAR_CUT_MASK);
+	prr &= (PRR_PRODUCT_MASK | PRR_CUT_MASK);
 
 	mmio_write_32(PFC_PMMR, ~data);
-	if (prr == (RCAR_PRODUCT_M3_CUT10)) {
+	if (prr == (PRR_PRODUCT_M3_CUT10)) {
 		mmio_write_16(SCIF3_SCFCR, SCFCR_DATA);	/* Dummy write */
 	}
 	mmio_write_32((uintptr_t)addr, data);
-	if (prr == (RCAR_PRODUCT_M3_CUT10)) {
+	if (prr == (PRR_PRODUCT_M3_CUT10)) {
 		mmio_write_16(SCIF3_SCFCR, SCFCR_DATA);	/* Dummy write */
 	}
 }
diff --git a/drivers/renesas/rcar/pfc/pfc_init.c b/drivers/renesas/rcar/pfc/pfc_init.c
index e9455af51..88106676a 100644
--- a/drivers/renesas/rcar/pfc/pfc_init.c
+++ b/drivers/renesas/rcar/pfc/pfc_init.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2015-2018, Renesas Electronics Corporation. All rights reserved.
+ * Copyright (c) 2015-2019, Renesas Electronics Corporation. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -37,20 +37,6 @@
 #include "D3/pfc_init_d3.h"
 #endif
 
- /* Product Register */
-#define PRR			(0xFFF00044U)
-#define PRR_PRODUCT_MASK	(0x00007F00U)
-#define PRR_CUT_MASK		(0x000000FFU)
-#define PRR_PRODUCT_H3		(0x00004F00U)	/* R-Car H3 */
-#define PRR_PRODUCT_M3		(0x00005200U)	/* R-Car M3 */
-#define PRR_PRODUCT_V3M		(0x00005400U)	/* R-Car V3M */
-#define PRR_PRODUCT_M3N		(0x00005500U)	/* R-Car M3N */
-#define PRR_PRODUCT_E3		(0x00005700U)	/* R-Car E3 */
-#define PRR_PRODUCT_D3		(0x00005800U)	/* R-Car D3 */
-#define PRR_PRODUCT_10		(0x00U)
-#define PRR_PRODUCT_11		(0x01U)
-#define PRR_PRODUCT_20		(0x10U)
-
 #define PRR_PRODUCT_ERR(reg)				\
 	do {						\
 		ERROR("LSI Product ID(PRR=0x%x) PFC initialize not supported.\n", \
@@ -71,8 +57,8 @@ void rcar_pfc_init(void)
 
 	reg = mmio_read_32(RCAR_PRR);
 #if RCAR_LSI == RCAR_AUTO
-	switch (reg & RCAR_PRODUCT_MASK) {
-	case RCAR_PRODUCT_H3:
+	switch (reg & PRR_PRODUCT_MASK) {
+	case PRR_PRODUCT_H3:
 		switch (reg & PRR_CUT_MASK) {
 		case PRR_PRODUCT_10:	/* H3 Ver.1.0 */
 			pfc_init_h3_v1();
@@ -85,13 +71,13 @@ void rcar_pfc_init(void)
 			break;
 		}
 		break;
-	case RCAR_PRODUCT_M3:
+	case PRR_PRODUCT_M3:
 		pfc_init_m3();
 		break;
-	case RCAR_PRODUCT_M3N:
+	case PRR_PRODUCT_M3N:
 		pfc_init_m3n();
 		break;
-	case RCAR_PRODUCT_V3M:
+	case PRR_PRODUCT_V3M:
 		pfc_init_v3m();
 		break;
 	default:
diff --git a/drivers/renesas/rcar/pfc/pfc_regs.h b/drivers/renesas/rcar/pfc/pfc_regs.h
index e7dd54397..418773366 100644
--- a/drivers/renesas/rcar/pfc/pfc_regs.h
+++ b/drivers/renesas/rcar/pfc/pfc_regs.h
@@ -115,7 +115,6 @@
 #define GPIO_IOINTSEL6		(GPIO_BASE + 0x5400U)
 #define GPIO_INOUTSEL6		(GPIO_BASE + 0x5404U)
 #define GPIO_OUTDT6		(GPIO_BASE + 0x5408U)
-#define GPIO_INDT6		(GPIO_BASE + 0x540CU)
 #define GPIO_INTDT6		(GPIO_BASE + 0x5410U)
 #define GPIO_INTCLR6		(GPIO_BASE + 0x5414U)
 #define GPIO_INTMSK6		(GPIO_BASE + 0x5418U)
diff --git a/drivers/renesas/rcar/pwrc/pwrc.c b/drivers/renesas/rcar/pwrc/pwrc.c
index 32e04a73a..2ce6b6139 100644
--- a/drivers/renesas/rcar/pwrc/pwrc.c
+++ b/drivers/renesas/rcar/pwrc/pwrc.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2015-2018, Renesas Electronics Corporation. All rights reserved.
+ * Copyright (c) 2015-2019, Renesas Electronics Corporation. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -314,16 +314,16 @@ void rcar_pwrc_clusteroff(uint64_t mpidr)
 	rcar_lock_get();
 
 	reg = mmio_read_32(RCAR_PRR);
-	product = reg & RCAR_PRODUCT_MASK;
-	cut = reg & RCAR_CUT_MASK;
+	product = reg & PRR_PRODUCT_MASK;
+	cut = reg & PRR_CUT_MASK;
 
 	c = rcar_pwrc_get_mpidr_cluster(mpidr);
 	dst = IS_CA53(c) ? RCAR_CA53CPUCMCR : RCAR_CA57CPUCMCR;
 
-	if (RCAR_PRODUCT_M3 == product && cut < RCAR_CUT_VER30)
+	if (PRR_PRODUCT_M3 == product && cut < PRR_PRODUCT_30)
 		goto done;
 
-	if (RCAR_PRODUCT_H3 == product && cut <= RCAR_CUT_VER20)
+	if (PRR_PRODUCT_H3 == product && cut <= PRR_PRODUCT_20)
 		goto done;
 
 	/* all of the CPUs in the cluster is in the CoreStandby mode */
@@ -424,13 +424,13 @@ static void __attribute__ ((section(".system_ram")))
 	uint32_t reg = mmio_read_32(RCAR_PRR);
 	uint32_t cut, product;
 
-	product = reg & RCAR_PRODUCT_MASK;
-	cut = reg & RCAR_CUT_MASK;
+	product = reg & PRR_PRODUCT_MASK;
+	cut = reg & PRR_CUT_MASK;
 
-	if (product == RCAR_PRODUCT_M3 && cut < RCAR_CUT_VER30)
+	if (product == PRR_PRODUCT_M3 && cut < PRR_PRODUCT_30)
 		goto self_refresh;
 
-	if (product == RCAR_PRODUCT_H3 && cut < RCAR_CUT_VER20)
+	if (product == PRR_PRODUCT_H3 && cut < PRR_PRODUCT_20)
 		goto self_refresh;
 
 	mmio_write_32(DBSC4_REG_DBSYSCNT0, DBSC4_SET_DBSYSCNT0_WRITE_ENABLE);
@@ -445,16 +445,16 @@ self_refresh:
 	/* Set the Self-Refresh mode */
 	mmio_write_32(DBSC4_REG_DBACEN, 0);
 
-	if (product == RCAR_PRODUCT_H3 && cut < RCAR_CUT_VER20)
+	if (product == PRR_PRODUCT_H3 && cut < PRR_PRODUCT_20)
 		rcar_micro_delay(100);
-	else if (product == RCAR_PRODUCT_H3) {
+	else if (product == PRR_PRODUCT_H3) {
 		mmio_write_32(DBSC4_REG_DBCAM0CTRL0, 1);
 		DBCAM_FLUSH(0);
 		DBCAM_FLUSH(1);
 		DBCAM_FLUSH(2);
 		DBCAM_FLUSH(3);
 		mmio_write_32(DBSC4_REG_DBCAM0CTRL0, 0);
-	} else if (product == RCAR_PRODUCT_M3) {
+	} else if (product == PRR_PRODUCT_M3) {
 		mmio_write_32(DBSC4_REG_DBCAM0CTRL0, 1);
 		DBCAM_FLUSH(0);
 		DBCAM_FLUSH(1);
@@ -499,10 +499,10 @@ self_refresh:
 	mmio_write_32(DBSC4_REG_DBRFEN, 0U);
 	rcar_micro_delay(1U);
 
-	if (product == RCAR_PRODUCT_M3 && cut < RCAR_CUT_VER30)
+	if (product == PRR_PRODUCT_M3 && cut < PRR_PRODUCT_30)
 		return;
 
-	if (product == RCAR_PRODUCT_H3 && cut < RCAR_CUT_VER20)
+	if (product == PRR_PRODUCT_H3 && cut < PRR_PRODUCT_20)
 		return;
 
 	mmio_write_32(DBSC4_REG_DBSYSCNT0, DBSC4_SET_DBSYSCNT0_WRITE_DISABLE);
@@ -648,9 +648,9 @@ void __attribute__ ((section(".system_ram"))) __attribute__ ((noinline))
 	uint32_t reg, product;
 
 	reg = mmio_read_32(RCAR_PRR);
-	product = reg & RCAR_PRODUCT_MASK;
+	product = reg & PRR_PRODUCT_MASK;
 
-	if (product != RCAR_PRODUCT_E3)
+	if (product != PRR_PRODUCT_E3)
 		rcar_pwrc_set_self_refresh();
 	else
 		rcar_pwrc_set_self_refresh_e3();
diff --git a/drivers/renesas/rcar/qos/M3/qos_init_m3_v30.c b/drivers/renesas/rcar/qos/M3/qos_init_m3_v30.c
index e300fd541..43d21d71c 100644
--- a/drivers/renesas/rcar/qos/M3/qos_init_m3_v30.c
+++ b/drivers/renesas/rcar/qos/M3/qos_init_m3_v30.c
@@ -12,7 +12,7 @@
 #include "../qos_reg.h"
 #include "qos_init_m3_v30.h"
 
-#define	RCAR_QOS_VERSION			"rev.0.03"
+#define	RCAR_QOS_VERSION			"rev.0.04"
 
 #define QOSWT_TIME_BANK0			20000000U	/* unit:ns */
 
diff --git a/drivers/renesas/rcar/qos/M3/qos_init_m3_v30_mstat195.h b/drivers/renesas/rcar/qos/M3/qos_init_m3_v30_mstat195.h
index cd820e85e..2ab14dad3 100644
--- a/drivers/renesas/rcar/qos/M3/qos_init_m3_v30_mstat195.h
+++ b/drivers/renesas/rcar/qos/M3/qos_init_m3_v30_mstat195.h
@@ -32,8 +32,8 @@ static uint64_t mstat_fix[] = {
 	/* 0x00c0, */ 0x000C04020000FFFFUL,
 	/* 0x00c8, */ 0x000C04010000FFFFUL,
 	/* 0x00d0, */ 0x000C04010000FFFFUL,
-	/* 0x00d8, */ 0x000C100D0000FFFFUL,
-	/* 0x00e0, */ 0x000C1C1B0000FFFFUL,
+	/* 0x00d8, */ 0x000C08050000FFFFUL,
+	/* 0x00e0, */ 0x000C10100000FFFFUL,
 	/* 0x00e8, */ 0x0000000000000000UL,
 	/* 0x00f0, */ 0x001024090000FFFFUL,
 	/* 0x00f8, */ 0x0000000000000000UL,
@@ -41,7 +41,7 @@ static uint64_t mstat_fix[] = {
 	/* 0x0108, */ 0x0000000000000000UL,
 	/* 0x0110, */ 0x00100C090000FFFFUL,
 	/* 0x0118, */ 0x0000000000000000UL,
-	/* 0x0120, */ 0x000C1C1B0000FFFFUL,
+	/* 0x0120, */ 0x000C10100000FFFFUL,
 	/* 0x0128, */ 0x0000000000000000UL,
 	/* 0x0130, */ 0x0000000000000000UL,
 	/* 0x0138, */ 0x00100C0B0000FFFFUL,
diff --git a/drivers/renesas/rcar/qos/M3/qos_init_m3_v30_mstat390.h b/drivers/renesas/rcar/qos/M3/qos_init_m3_v30_mstat390.h
index e9037e1fd..faac3d9fb 100644
--- a/drivers/renesas/rcar/qos/M3/qos_init_m3_v30_mstat390.h
+++ b/drivers/renesas/rcar/qos/M3/qos_init_m3_v30_mstat390.h
@@ -32,8 +32,8 @@ static uint64_t mstat_fix[] = {
 	/* 0x00c0, */ 0x000C08040000FFFFUL,
 	/* 0x00c8, */ 0x000C04020000FFFFUL,
 	/* 0x00d0, */ 0x000C04020000FFFFUL,
-	/* 0x00d8, */ 0x000C1C1A0000FFFFUL,
-	/* 0x00e0, */ 0x000C38360000FFFFUL,
+	/* 0x00d8, */ 0x000C0C0A0000FFFFUL,
+	/* 0x00e0, */ 0x000C201F0000FFFFUL,
 	/* 0x00e8, */ 0x0000000000000000UL,
 	/* 0x00f0, */ 0x001044110000FFFFUL,
 	/* 0x00f8, */ 0x0000000000000000UL,
@@ -41,7 +41,7 @@ static uint64_t mstat_fix[] = {
 	/* 0x0108, */ 0x0000000000000000UL,
 	/* 0x0110, */ 0x001014110000FFFFUL,
 	/* 0x0118, */ 0x0000000000000000UL,
-	/* 0x0120, */ 0x000C38360000FFFFUL,
+	/* 0x0120, */ 0x000C201F0000FFFFUL,
 	/* 0x0128, */ 0x0000000000000000UL,
 	/* 0x0130, */ 0x0000000000000000UL,
 	/* 0x0138, */ 0x001018150000FFFFUL,
diff --git a/drivers/renesas/rcar/qos/qos_init.c b/drivers/renesas/rcar/qos/qos_init.c
index 884e031ca..d0f17309b 100644
--- a/drivers/renesas/rcar/qos/qos_init.c
+++ b/drivers/renesas/rcar/qos/qos_init.c
@@ -12,6 +12,7 @@
 #include "qos_init.h"
 #include "qos_common.h"
 #include "qos_reg.h"
+#include "rcar_def.h"
 #if RCAR_LSI == RCAR_AUTO
 #include "H3/qos_init_h3_v10.h"
 #include "H3/qos_init_h3_v11.h"
@@ -50,22 +51,6 @@
 #include "D3/qos_init_d3.h"
 #endif
 
- /* Product Register */
-#define PRR			0xFFF00044U
-#define PRR_PRODUCT_MASK	0x00007F00U
-#define PRR_CUT_MASK		0x000000FFU
-#define PRR_PRODUCT_H3		0x00004F00U	/* R-Car H3 */
-#define PRR_PRODUCT_M3		0x00005200U	/* R-Car M3 */
-#define PRR_PRODUCT_V3M		0x00005400U	/* R-Car V3M */
-#define PRR_PRODUCT_M3N		0x00005500U	/* R-Car M3N */
-#define PRR_PRODUCT_E3		0x00005700U	/* R-Car E3 */
-#define PRR_PRODUCT_D3		0x00005800U	/* R-Car D3 */
-#define PRR_PRODUCT_10		0x00U
-#define PRR_PRODUCT_11		0x01U
-#define PRR_PRODUCT_20		0x10U
-#define PRR_PRODUCT_21		0x11U
-#define PRR_PRODUCT_30		0x20U
-
 #if (RCAR_LSI != RCAR_E3) && (RCAR_LSI != RCAR_D3) && (RCAR_LSI != RCAR_V3M)
 
 #define DRAM_CH_CNT			0x04
diff --git a/drivers/renesas/rcar/rom/rom_api.c b/drivers/renesas/rcar/rom/rom_api.c
index c9f8f5fe8..fda28150e 100644
--- a/drivers/renesas/rcar/rom/rom_api.c
+++ b/drivers/renesas/rcar/rom/rom_api.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2015-2018, Renesas Electronics Corporation. All rights reserved.
+ * Copyright (c) 2015-2019, Renesas Electronics Corporation. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -30,30 +30,30 @@ static uint32_t get_table_index(void)
 	uint32_t cut_ver;
 	uint32_t index;
 
-	product = mmio_read_32(RCAR_PRR) & RCAR_PRODUCT_MASK;
-	cut_ver = mmio_read_32(RCAR_PRR) & RCAR_CUT_MASK;
+	product = mmio_read_32(RCAR_PRR) & PRR_PRODUCT_MASK;
+	cut_ver = mmio_read_32(RCAR_PRR) & PRR_CUT_MASK;
 
 	switch (product) {
-	case RCAR_PRODUCT_H3:
-		if (cut_ver == RCAR_CUT_VER10)
+	case PRR_PRODUCT_H3:
+		if (cut_ver == PRR_PRODUCT_10)
 			index = OLD_API_TABLE1;
-		else if (cut_ver == RCAR_CUT_VER11)
+		else if (cut_ver == PRR_PRODUCT_11)
 			index = OLD_API_TABLE1;
-		else if (cut_ver == RCAR_CUT_VER20)
+		else if (cut_ver == PRR_PRODUCT_20)
 			index = OLD_API_TABLE2;
 		else
 			/* Later than H3 Ver.2.0 */
 			index = NEW_API_TABLE;
 		break;
-	case RCAR_PRODUCT_M3:
-		if (cut_ver == RCAR_CUT_VER10)
+	case PRR_PRODUCT_M3:
+		if (cut_ver == PRR_PRODUCT_10)
 			index = OLD_API_TABLE3;
 		else
 			/* M3 Ver.1.1 or later */
 			index = NEW_API_TABLE;
 		break;
-	case RCAR_PRODUCT_V3M:
-		if (cut_ver == RCAR_CUT_VER10)
+	case PRR_PRODUCT_V3M:
+		if (cut_ver == PRR_PRODUCT_10)
 			/* V3M WS1.0 */
 			index = NEW_API_TABLE2;
 		else
diff --git a/drivers/renesas/rcar/rpc/rpc_driver.c b/drivers/renesas/rcar/rpc/rpc_driver.c
index 5c11b62de..63de5b851 100644
--- a/drivers/renesas/rcar/rpc/rpc_driver.c
+++ b/drivers/renesas/rcar/rpc/rpc_driver.c
@@ -34,10 +34,10 @@ static void rpc_setup(void)
 	if (mmio_read_32(RPC_CMNCR) & RPC_CMNCR_MD_BIT)
 		mmio_clrbits_32(RPC_CMNCR, RPC_CMNCR_MD_BIT);
 
-	product = mmio_read_32(RCAR_PRR) & RCAR_PRODUCT_MASK;
-	cut = mmio_read_32(RCAR_PRR) & RCAR_CUT_MASK;
+	product = mmio_read_32(RCAR_PRR) & PRR_PRODUCT_MASK;
+	cut = mmio_read_32(RCAR_PRR) & PRR_CUT_MASK;
 
-	if ((product ==  RCAR_PRODUCT_M3) && (cut < RCAR_CUT_VER30))
+	if ((product ==  PRR_PRODUCT_M3) && (cut < PRR_PRODUCT_30))
 		phy_strtim = RPC_PHYCNT_STRTIM_M3V1;
 	else
 		phy_strtim = RPC_PHYCNT_STRTIM;
diff --git a/drivers/renesas/rcar/watchdog/swdt.c b/drivers/renesas/rcar/watchdog/swdt.c
index 8b2943cc6..111e65174 100644
--- a/drivers/renesas/rcar/watchdog/swdt.c
+++ b/drivers/renesas/rcar/watchdog/swdt.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2015-2018, Renesas Electronics Corporation. All rights reserved.
+ * Copyright (c) 2015-2019, Renesas Electronics Corporation. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -82,7 +82,7 @@ void rcar_swdt_init(void)
 	uint32_t reg, val, product_cut, chk_data;
 
 	reg = mmio_read_32(RCAR_PRR);
-	product_cut = reg & (RCAR_PRODUCT_MASK | RCAR_CUT_MASK);
+	product_cut = reg & (PRR_PRODUCT_MASK | PRR_CUT_MASK);
 
 	reg = mmio_read_32(RCAR_MODEMR);
 	chk_data = reg & CHECK_MD13_MD14;
@@ -108,7 +108,7 @@ void rcar_swdt_init(void)
 		val |= WTCNT_COUNT_8p22k;
 		break;
 	case MD14_MD13_TYPE_3:
-		val |= product_cut == (RCAR_PRODUCT_H3 | RCAR_CUT_VER10) ?
+		val |= product_cut == (PRR_PRODUCT_H3 | PRR_PRODUCT_10) ?
 		    WTCNT_COUNT_8p13k_H3VER10 : WTCNT_COUNT_8p13k;
 		break;
 	default:
diff --git a/drivers/rpi3/mailbox/rpi3_mbox.c b/drivers/rpi3/mailbox/rpi3_mbox.c
new file mode 100644
index 000000000..aef1f39a7
--- /dev/null
+++ b/drivers/rpi3/mailbox/rpi3_mbox.c
@@ -0,0 +1,82 @@
+/*
+ * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <platform_def.h>
+
+#include <arch_helpers.h>
+#include <common/debug.h>
+#include <lib/mmio.h>
+
+#include <rpi_hw.h>
+
+#include <drivers/rpi3/mailbox/rpi3_mbox.h>
+
+#define RPI3_MAILBOX_MAX_RETRIES	U(1000000)
+
+/*******************************************************************************
+ * Routine to send requests to the VideoCore using the mailboxes.
+ ******************************************************************************/
+void rpi3_vc_mailbox_request_send(rpi3_mbox_request_t *req, int req_size)
+{
+	uint32_t st, data;
+	uintptr_t resp_addr, addr;
+	unsigned int retries;
+
+	/* This is the location of the request buffer */
+	addr = (uintptr_t)req;
+
+	/* Make sure that the changes are seen by the VideoCore */
+	flush_dcache_range(addr, req_size);
+
+	/* Wait until the outbound mailbox is empty */
+	retries = 0U;
+
+	do {
+		st = mmio_read_32(RPI3_MBOX_BASE + RPI3_MBOX1_STATUS_OFFSET);
+
+		retries++;
+		if (retries == RPI3_MAILBOX_MAX_RETRIES) {
+			ERROR("rpi3: mbox: Send request timeout\n");
+			return;
+		}
+
+	} while ((st & RPI3_MBOX_STATUS_EMPTY_MASK) == 0U);
+
+	/* Send base address of this message to start request */
+	mmio_write_32(RPI3_MBOX_BASE + RPI3_MBOX1_WRITE_OFFSET,
+		      RPI3_CHANNEL_ARM_TO_VC | (uint32_t) addr);
+
+	/* Wait until the inbound mailbox isn't empty */
+	retries = 0U;
+
+	do {
+		st = mmio_read_32(RPI3_MBOX_BASE + RPI3_MBOX0_STATUS_OFFSET);
+
+		retries++;
+		if (retries == RPI3_MAILBOX_MAX_RETRIES) {
+			ERROR("rpi3: mbox: Receive response timeout\n");
+			return;
+		}
+
+	} while ((st & RPI3_MBOX_STATUS_EMPTY_MASK) != 0U);
+
+	/* Get location and channel */
+	data = mmio_read_32(RPI3_MBOX_BASE + RPI3_MBOX0_READ_OFFSET);
+
+	if ((data & RPI3_CHANNEL_MASK) != RPI3_CHANNEL_ARM_TO_VC) {
+		ERROR("rpi3: mbox: Wrong channel: 0x%08x\n", data);
+		panic();
+	}
+
+	resp_addr = (uintptr_t)(data & ~RPI3_CHANNEL_MASK);
+	if (addr != resp_addr) {
+		ERROR("rpi3: mbox: Unexpected address: 0x%08x\n", data);
+		panic();
+	}
+
+	/* Make sure that the data seen by the CPU is up to date */
+	inv_dcache_range(addr, req_size);
+}
diff --git a/drivers/rpi3/rng/rpi3_rng.c b/drivers/rpi3/rng/rpi3_rng.c
new file mode 100644
index 000000000..b6bf0052a
--- /dev/null
+++ b/drivers/rpi3/rng/rpi3_rng.c
@@ -0,0 +1,75 @@
+/*
+ * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <assert.h>
+#include <string.h>
+
+#include <lib/mmio.h>
+
+#include <rpi_hw.h>
+
+/* Initial amount of values to discard */
+#define RNG_WARMUP_COUNT	U(0x40000)
+
+static void rpi3_rng_initialize(void)
+{
+	uint32_t int_mask, ctrl;
+
+	/* Return if it is already enabled */
+	ctrl = mmio_read_32(RPI3_RNG_BASE + RPI3_RNG_CTRL_OFFSET);
+	if ((ctrl & RPI3_RNG_CTRL_ENABLE) != 0U) {
+		return;
+	}
+
+	/* Mask interrupts */
+	int_mask = mmio_read_32(RPI3_RNG_BASE + RPI3_RNG_INT_MASK_OFFSET);
+	int_mask |= RPI3_RNG_INT_MASK_DISABLE;
+	mmio_write_32(RPI3_RNG_BASE + RPI3_RNG_INT_MASK_OFFSET, int_mask);
+
+	/* Discard several values when initializing to give it time to warmup */
+	mmio_write_32(RPI3_RNG_BASE + RPI3_RNG_STATUS_OFFSET, RNG_WARMUP_COUNT);
+
+	mmio_write_32(RPI3_RNG_BASE + RPI3_RNG_CTRL_OFFSET,
+		      RPI3_RNG_CTRL_ENABLE);
+}
+
+static uint32_t rpi3_rng_get_word(void)
+{
+	size_t nwords;
+
+	do {
+		/* Get number of available words to read */
+		nwords = (mmio_read_32(RPI3_RNG_BASE + RPI3_RNG_STATUS_OFFSET)
+				       >> RPI3_RNG_STATUS_NUM_WORDS_SHIFT)
+				       & RPI3_RNG_STATUS_NUM_WORDS_MASK;
+	} while (nwords == 0U);
+
+	return mmio_read_32(RPI3_RNG_BASE + RPI3_RNG_DATA_OFFSET);
+}
+
+void rpi3_rng_read(void *buf, size_t len)
+{
+	uint32_t data;
+	size_t left = len;
+	uint32_t *dst = buf;
+
+	assert(buf != NULL);
+	assert(len != 0U);
+	assert(check_uptr_overflow((uintptr_t) buf, (uintptr_t) len) == 0);
+
+	rpi3_rng_initialize();
+
+	while (left >= sizeof(uint32_t)) {
+		data = rpi3_rng_get_word();
+		*dst++ = data;
+		left -= sizeof(uint32_t);
+	}
+
+	if (left > 0U) {
+		data = rpi3_rng_get_word();
+		memcpy(dst, &data, left);
+	}
+}
diff --git a/drivers/st/bsec/bsec.c b/drivers/st/bsec/bsec.c
index aaecf1f83..01c369edc 100644
--- a/drivers/st/bsec/bsec.c
+++ b/drivers/st/bsec/bsec.c
@@ -32,20 +32,14 @@ static uintptr_t bsec_base;
 
 static void bsec_lock(void)
 {
-	const uint32_t mask = SCTLR_M_BIT | SCTLR_C_BIT;
-
-	/* Lock is currently required only when MMU and cache are enabled */
-	if ((read_sctlr() & mask) == mask) {
+	if (stm32mp_lock_available()) {
 		spin_lock(&bsec_spinlock);
 	}
 }
 
 static void bsec_unlock(void)
 {
-	const uint32_t mask = SCTLR_M_BIT | SCTLR_C_BIT;
-
-	/* Unlock is required only when MMU and cache are enabled */
-	if ((read_sctlr() & mask) == mask) {
+	if (stm32mp_lock_available()) {
 		spin_unlock(&bsec_spinlock);
 	}
 }
@@ -847,22 +841,6 @@ static uint32_t bsec_power_safmem(bool power)
 }
 
 /*
- * bsec_mode_is_closed_device: read OTP secure sub-mode.
- * return: false if open_device and true of closed_device.
- */
-bool bsec_mode_is_closed_device(void)
-{
-	uint32_t value;
-
-	if ((bsec_shadow_register(DATA0_OTP) != BSEC_OK) ||
-	    (bsec_read_otp(&value, DATA0_OTP) != BSEC_OK)) {
-		return true;
-	}
-
-	return (value & DATA0_OTP_SECURED) == DATA0_OTP_SECURED;
-}
-
-/*
  * bsec_shadow_read_otp: Load OTP from SAFMEM and provide its value
  * otp_value: read value.
  * word: OTP number.
@@ -900,7 +878,7 @@ uint32_t bsec_check_nsec_access_rights(uint32_t otp)
 
 	if (otp >= STM32MP1_UPPER_OTP_START) {
 		/* Check if BSEC is in OTP-SECURED closed_device state. */
-		if (bsec_mode_is_closed_device()) {
+		if (stm32mp_is_closed_device()) {
 			if (!non_secure_can_access(otp)) {
 				return BSEC_ERROR;
 			}
diff --git a/drivers/st/clk/stm32mp1_clk.c b/drivers/st/clk/stm32mp1_clk.c
index 76e6e6fdc..0cc87cc71 100644
--- a/drivers/st/clk/stm32mp1_clk.c
+++ b/drivers/st/clk/stm32mp1_clk.c
@@ -541,29 +541,19 @@ static const struct stm32mp1_clk_pll *pll_ref(unsigned int idx)
 	return &stm32mp1_clk_pll[idx];
 }
 
-static int stm32mp1_lock_available(void)
-{
-	/* The spinlocks are used only when MMU is enabled */
-	return (read_sctlr() & SCTLR_M_BIT) && (read_sctlr() & SCTLR_C_BIT);
-}
-
 static void stm32mp1_clk_lock(struct spinlock *lock)
 {
-	if (stm32mp1_lock_available() == 0U) {
-		return;
+	if (stm32mp_lock_available()) {
+		/* Assume interrupts are masked */
+		spin_lock(lock);
 	}
-
-	/* Assume interrupts are masked */
-	spin_lock(lock);
 }
 
 static void stm32mp1_clk_unlock(struct spinlock *lock)
 {
-	if (stm32mp1_lock_available() == 0U) {
-		return;
+	if (stm32mp_lock_available()) {
+		spin_unlock(lock);
 	}
-
-	spin_unlock(lock);
 }
 
 bool stm32mp1_rcc_is_secure(void)
@@ -1912,9 +1902,18 @@ static void stm32mp1_osc_init(void)
 	}
 }
 
+static void sync_earlyboot_clocks_state(void)
+{
+	if (!stm32mp_is_single_core()) {
+		stm32mp1_clk_enable_secure(RTCAPB);
+	}
+}
+
 int stm32mp1_clk_probe(void)
 {
 	stm32mp1_osc_init();
 
+	sync_earlyboot_clocks_state();
+
 	return 0;
 }
diff --git a/drivers/st/crypto/stm32_hash.c b/drivers/st/crypto/stm32_hash.c
new file mode 100644
index 000000000..f72787d33
--- /dev/null
+++ b/drivers/st/crypto/stm32_hash.c
@@ -0,0 +1,330 @@
+/*
+ * Copyright (c) 2019, STMicroelectronics - All Rights Reserved
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <assert.h>
+#include <errno.h>
+#include <stdint.h>
+
+#include <libfdt.h>
+
+#include <platform_def.h>
+
+#include <arch_helpers.h>
+#include <common/debug.h>
+#include <drivers/delay_timer.h>
+#include <drivers/st/stm32_hash.h>
+#include <drivers/st/stm32mp_reset.h>
+#include <lib/mmio.h>
+#include <lib/utils.h>
+#include <plat/common/platform.h>
+
+#define DT_HASH_COMPAT			"st,stm32f756-hash"
+
+#define HASH_CR				0x00U
+#define HASH_DIN			0x04U
+#define HASH_STR			0x08U
+#define HASH_SR				0x24U
+#define HASH_HREG(x)			(0x310U + ((x) * 0x04U))
+
+/* Control Register */
+#define HASH_CR_INIT			BIT(2)
+#define HASH_CR_DATATYPE_SHIFT		U(4)
+
+#define HASH_CR_ALGO_SHA1		0x0U
+#define HASH_CR_ALGO_MD5		BIT(7)
+#define HASH_CR_ALGO_SHA224		BIT(18)
+#define HASH_CR_ALGO_SHA256		(BIT(18) | BIT(7))
+
+/* Status Flags */
+#define HASH_SR_DCIS			BIT(1)
+#define HASH_SR_BUSY			BIT(3)
+
+/* STR Register */
+#define HASH_STR_NBLW_MASK		GENMASK(4, 0)
+#define HASH_STR_DCAL			BIT(8)
+
+#define MD5_DIGEST_SIZE			16U
+#define SHA1_DIGEST_SIZE		20U
+#define SHA224_DIGEST_SIZE		28U
+#define SHA256_DIGEST_SIZE		32U
+
+#define HASH_TIMEOUT_US			10000U
+
+enum stm32_hash_data_format {
+	HASH_DATA_32_BITS,
+	HASH_DATA_16_BITS,
+	HASH_DATA_8_BITS,
+	HASH_DATA_1_BIT
+};
+
+struct stm32_hash_instance {
+	uintptr_t base;
+	unsigned int clock;
+	size_t digest_size;
+};
+
+struct stm32_hash_remain {
+	uint32_t buffer;
+	size_t length;
+};
+
+/* Expect a single HASH peripheral */
+static struct stm32_hash_instance stm32_hash;
+static struct stm32_hash_remain stm32_remain;
+
+static uintptr_t hash_base(void)
+{
+	return stm32_hash.base;
+}
+
+static int hash_wait_busy(void)
+{
+	uint64_t timeout = timeout_init_us(HASH_TIMEOUT_US);
+
+	while ((mmio_read_32(hash_base() + HASH_SR) & HASH_SR_BUSY) != 0U) {
+		if (timeout_elapsed(timeout)) {
+			ERROR("%s: busy timeout\n", __func__);
+			return -ETIMEDOUT;
+		}
+	}
+
+	return 0;
+}
+
+static int hash_wait_computation(void)
+{
+	uint64_t timeout = timeout_init_us(HASH_TIMEOUT_US);
+
+	while ((mmio_read_32(hash_base() + HASH_SR) & HASH_SR_DCIS) == 0U) {
+		if (timeout_elapsed(timeout)) {
+			ERROR("%s: busy timeout\n", __func__);
+			return -ETIMEDOUT;
+		}
+	}
+
+	return 0;
+}
+
+static int hash_write_data(uint32_t data)
+{
+	int ret;
+
+	ret = hash_wait_busy();
+	if (ret != 0) {
+		return ret;
+	}
+
+	mmio_write_32(hash_base() + HASH_DIN, data);
+
+	return 0;
+}
+
+static void hash_hw_init(enum stm32_hash_algo_mode mode)
+{
+	uint32_t reg;
+
+	reg = HASH_CR_INIT | (HASH_DATA_8_BITS << HASH_CR_DATATYPE_SHIFT);
+
+	switch (mode) {
+	case HASH_MD5SUM:
+		reg |= HASH_CR_ALGO_MD5;
+		stm32_hash.digest_size = MD5_DIGEST_SIZE;
+		break;
+	case HASH_SHA1:
+		reg |= HASH_CR_ALGO_SHA1;
+		stm32_hash.digest_size = SHA1_DIGEST_SIZE;
+		break;
+	case HASH_SHA224:
+		reg |= HASH_CR_ALGO_SHA224;
+		stm32_hash.digest_size = SHA224_DIGEST_SIZE;
+		break;
+	/* Default selected algo is SHA256 */
+	case HASH_SHA256:
+	default:
+		reg |= HASH_CR_ALGO_SHA256;
+		stm32_hash.digest_size = SHA256_DIGEST_SIZE;
+		break;
+	}
+
+	mmio_write_32(hash_base() + HASH_CR, reg);
+}
+
+static int hash_get_digest(uint8_t *digest)
+{
+	int ret;
+	uint32_t i;
+	uint32_t dsg;
+
+	ret = hash_wait_computation();
+	if (ret != 0) {
+		return ret;
+	}
+
+	for (i = 0U; i < (stm32_hash.digest_size / sizeof(uint32_t)); i++) {
+		dsg = __builtin_bswap32(mmio_read_32(hash_base() +
+						     HASH_HREG(i)));
+		memcpy(digest + (i * sizeof(uint32_t)), &dsg, sizeof(uint32_t));
+	}
+
+#if defined(IMAGE_BL2)
+	/*
+	 * Clean hardware context as HASH could be used later
+	 * by non-secure software
+	 */
+	hash_hw_init(HASH_SHA256);
+#endif
+	return 0;
+}
+
+int stm32_hash_update(const uint8_t *buffer, size_t length)
+{
+	size_t remain_length = length;
+	int ret = 0;
+
+	if ((length == 0U) || (buffer == NULL)) {
+		return 0;
+	}
+
+	stm32mp_clk_enable(stm32_hash.clock);
+
+	if (stm32_remain.length != 0U) {
+		uint32_t copysize;
+
+		copysize = MIN((sizeof(uint32_t) - stm32_remain.length),
+			       length);
+		memcpy(((uint8_t *)&stm32_remain.buffer) + stm32_remain.length,
+		       buffer, copysize);
+		remain_length -= copysize;
+		buffer += copysize;
+		if (stm32_remain.length == sizeof(uint32_t)) {
+			ret = hash_write_data(stm32_remain.buffer);
+			if (ret != 0) {
+				goto exit;
+			}
+
+			zeromem(&stm32_remain, sizeof(stm32_remain));
+		}
+	}
+
+	while (remain_length / sizeof(uint32_t) != 0U) {
+		uint32_t tmp_buf;
+
+		memcpy(&tmp_buf, buffer, sizeof(uint32_t));
+		ret = hash_write_data(tmp_buf);
+		if (ret != 0) {
+			goto exit;
+		}
+
+		buffer += sizeof(uint32_t);
+		remain_length -= sizeof(uint32_t);
+	}
+
+	if (remain_length != 0U) {
+		assert(stm32_remain.length == 0U);
+
+		memcpy((uint8_t *)&stm32_remain.buffer, buffer, remain_length);
+		stm32_remain.length = remain_length;
+	}
+
+exit:
+	stm32mp_clk_disable(stm32_hash.clock);
+
+	return ret;
+}
+
+int stm32_hash_final(uint8_t *digest)
+{
+	int ret;
+
+	stm32mp_clk_enable(stm32_hash.clock);
+
+	if (stm32_remain.length != 0U) {
+		ret = hash_write_data(stm32_remain.buffer);
+		if (ret != 0) {
+			stm32mp_clk_disable(stm32_hash.clock);
+			return ret;
+		}
+
+		mmio_clrsetbits_32(hash_base() + HASH_STR, HASH_STR_NBLW_MASK,
+				   8U * stm32_remain.length);
+		zeromem(&stm32_remain, sizeof(stm32_remain));
+	}
+
+	mmio_setbits_32(hash_base() + HASH_STR, HASH_STR_DCAL);
+
+	ret = hash_get_digest(digest);
+
+	stm32mp_clk_disable(stm32_hash.clock);
+
+	return ret;
+}
+
+int stm32_hash_final_update(const uint8_t *buffer, uint32_t length,
+			    uint8_t *digest)
+{
+	int ret;
+
+	ret = stm32_hash_update(buffer, length);
+	if (ret != 0) {
+		return ret;
+	}
+
+	return stm32_hash_final(digest);
+}
+
+void stm32_hash_init(enum stm32_hash_algo_mode mode)
+{
+	stm32mp_clk_enable(stm32_hash.clock);
+
+	hash_hw_init(mode);
+
+	stm32mp_clk_disable(stm32_hash.clock);
+
+	zeromem(&stm32_remain, sizeof(stm32_remain));
+}
+
+int stm32_hash_register(void)
+{
+	struct dt_node_info hash_info;
+	int node;
+
+	for (node = dt_get_node(&hash_info, -1, DT_HASH_COMPAT);
+	     node != -FDT_ERR_NOTFOUND;
+	     node = dt_get_node(&hash_info, node, DT_HASH_COMPAT)) {
+#if defined(IMAGE_BL2)
+		if (hash_info.status != DT_DISABLED) {
+			break;
+		}
+#else
+		if (hash_info.status == DT_SECURE) {
+			break;
+		}
+#endif
+	}
+
+	if (node == -FDT_ERR_NOTFOUND) {
+		return -ENODEV;
+	}
+
+	if (hash_info.clock < 0) {
+		return -EINVAL;
+	}
+
+	stm32_hash.base = hash_info.base;
+	stm32_hash.clock = hash_info.clock;
+
+	stm32mp_clk_enable(stm32_hash.clock);
+
+	if (hash_info.reset >= 0) {
+		stm32mp_reset_assert((unsigned long)hash_info.reset);
+		udelay(20);
+		stm32mp_reset_deassert((unsigned long)hash_info.reset);
+	}
+
+	stm32mp_clk_disable(stm32_hash.clock);
+
+	return 0;
+}
diff --git a/drivers/st/ddr/stm32mp1_ddr.c b/drivers/st/ddr/stm32mp1_ddr.c
index caf8eefa8..7d89d027e 100644
--- a/drivers/st/ddr/stm32mp1_ddr.c
+++ b/drivers/st/ddr/stm32mp1_ddr.c
@@ -717,6 +717,8 @@ void stm32mp1_ddr_init(struct ddr_info *priv,
 		ret = board_ddr_power_init(STM32MP_DDR3);
 	} else if ((config->c_reg.mstr & DDRCTRL_MSTR_LPDDR2) != 0U) {
 		ret = board_ddr_power_init(STM32MP_LPDDR2);
+	} else if ((config->c_reg.mstr & DDRCTRL_MSTR_LPDDR3) != 0U) {
+		ret = board_ddr_power_init(STM32MP_LPDDR3);
 	} else {
 		ERROR("DDR type not supported\n");
 	}
diff --git a/drivers/st/fmc/stm32_fmc2_nand.c b/drivers/st/fmc/stm32_fmc2_nand.c
new file mode 100644
index 000000000..b694fff6b
--- /dev/null
+++ b/drivers/st/fmc/stm32_fmc2_nand.c
@@ -0,0 +1,877 @@
+/*
+ * Copyright (c) 2019, STMicroelectronics - All Rights Reserved
+ *
+ * SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
+ */
+
+#include <assert.h>
+#include <errno.h>
+#include <limits.h>
+#include <stdint.h>
+
+#include <libfdt.h>
+
+#include <platform_def.h>
+
+#include <common/debug.h>
+#include <drivers/delay_timer.h>
+#include <drivers/raw_nand.h>
+#include <drivers/st/stm32_fmc2_nand.h>
+#include <drivers/st/stm32_gpio.h>
+#include <drivers/st/stm32mp_reset.h>
+#include <lib/mmio.h>
+#include <lib/utils_def.h>
+
+/* FMC2 Compatibility */
+#define DT_FMC2_COMPAT			"st,stm32mp15-fmc2"
+#define MAX_CS				2U
+
+/* FMC2 Controller Registers */
+#define FMC2_BCR1			0x00U
+#define FMC2_PCR			0x80U
+#define FMC2_SR				0x84U
+#define FMC2_PMEM			0x88U
+#define FMC2_PATT			0x8CU
+#define FMC2_HECCR			0x94U
+#define FMC2_BCHISR			0x254U
+#define FMC2_BCHDSR0			0x27CU
+#define FMC2_BCHDSR1			0x280U
+#define FMC2_BCHDSR2			0x284U
+#define FMC2_BCHDSR3			0x288U
+#define FMC2_BCHDSR4			0x28CU
+
+/* FMC2_BCR1 register */
+#define FMC2_BCR1_FMC2EN		BIT(31)
+/* FMC2_PCR register */
+#define FMC2_PCR_PWAITEN		BIT(1)
+#define FMC2_PCR_PBKEN			BIT(2)
+#define FMC2_PCR_PWID_MASK		GENMASK_32(5, 4)
+#define FMC2_PCR_PWID(x)		(((x) << 4) & FMC2_PCR_PWID_MASK)
+#define FMC2_PCR_PWID_8			0x0U
+#define FMC2_PCR_PWID_16		0x1U
+#define FMC2_PCR_ECCEN			BIT(6)
+#define FMC2_PCR_ECCALG			BIT(8)
+#define FMC2_PCR_TCLR_MASK		GENMASK_32(12, 9)
+#define FMC2_PCR_TCLR(x)		(((x) << 9) & FMC2_PCR_TCLR_MASK)
+#define FMC2_PCR_TCLR_DEFAULT		0xFU
+#define FMC2_PCR_TAR_MASK		GENMASK_32(16, 13)
+#define FMC2_PCR_TAR(x)			(((x) << 13) & FMC2_PCR_TAR_MASK)
+#define FMC2_PCR_TAR_DEFAULT		0xFU
+#define FMC2_PCR_ECCSS_MASK		GENMASK_32(19, 17)
+#define FMC2_PCR_ECCSS(x)		(((x) << 17) & FMC2_PCR_ECCSS_MASK)
+#define FMC2_PCR_ECCSS_512		0x1U
+#define FMC2_PCR_ECCSS_2048		0x3U
+#define FMC2_PCR_BCHECC			BIT(24)
+#define FMC2_PCR_WEN			BIT(25)
+/* FMC2_SR register */
+#define FMC2_SR_NWRF			BIT(6)
+/* FMC2_PMEM register*/
+#define FMC2_PMEM_MEMSET(x)		(((x) & GENMASK_32(7, 0)) << 0)
+#define FMC2_PMEM_MEMWAIT(x)		(((x) & GENMASK_32(7, 0)) << 8)
+#define FMC2_PMEM_MEMHOLD(x)		(((x) & GENMASK_32(7, 0)) << 16)
+#define FMC2_PMEM_MEMHIZ(x)		(((x) & GENMASK_32(7, 0)) << 24)
+#define FMC2_PMEM_DEFAULT		0x0A0A0A0AU
+/* FMC2_PATT register */
+#define FMC2_PATT_ATTSET(x)		(((x) & GENMASK_32(7, 0)) << 0)
+#define FMC2_PATT_ATTWAIT(x)		(((x) & GENMASK_32(7, 0)) << 8)
+#define FMC2_PATT_ATTHOLD(x)		(((x) & GENMASK_32(7, 0)) << 16)
+#define FMC2_PATT_ATTHIZ(x)		(((x) & GENMASK_32(7, 0)) << 24)
+#define FMC2_PATT_DEFAULT		0x0A0A0A0AU
+/* FMC2_BCHISR register */
+#define FMC2_BCHISR_DERF		BIT(1)
+/* FMC2_BCHDSR0 register */
+#define FMC2_BCHDSR0_DUE		BIT(0)
+#define FMC2_BCHDSR0_DEF		BIT(1)
+#define FMC2_BCHDSR0_DEN_MASK		GENMASK_32(7, 4)
+#define FMC2_BCHDSR0_DEN_SHIFT		4U
+/* FMC2_BCHDSR1 register */
+#define FMC2_BCHDSR1_EBP1_MASK		GENMASK_32(12, 0)
+#define FMC2_BCHDSR1_EBP2_MASK		GENMASK_32(28, 16)
+#define FMC2_BCHDSR1_EBP2_SHIFT		16U
+/* FMC2_BCHDSR2 register */
+#define FMC2_BCHDSR2_EBP3_MASK		GENMASK_32(12, 0)
+#define FMC2_BCHDSR2_EBP4_MASK		GENMASK_32(28, 16)
+#define FMC2_BCHDSR2_EBP4_SHIFT		16U
+/* FMC2_BCHDSR3 register */
+#define FMC2_BCHDSR3_EBP5_MASK		GENMASK_32(12, 0)
+#define FMC2_BCHDSR3_EBP6_MASK		GENMASK_32(28, 16)
+#define FMC2_BCHDSR3_EBP6_SHIFT		16U
+/* FMC2_BCHDSR4 register */
+#define FMC2_BCHDSR4_EBP7_MASK		GENMASK_32(12, 0)
+#define FMC2_BCHDSR4_EBP8_MASK		GENMASK_32(28, 16)
+#define FMC2_BCHDSR4_EBP8_SHIFT		16U
+
+/* Timings */
+#define FMC2_THIZ			0x01U
+#define FMC2_TIO			8000U
+#define FMC2_TSYNC			3000U
+#define FMC2_PCR_TIMING_MASK		GENMASK_32(3, 0)
+#define FMC2_PMEM_PATT_TIMING_MASK	GENMASK_32(7, 0)
+
+#define FMC2_BBM_LEN			2U
+#define FMC2_MAX_ECC_BYTES		14U
+#define TIMEOUT_US_10_MS		10000U
+#define FMC2_PSEC_PER_MSEC		(1000UL * 1000UL * 1000UL)
+
+enum stm32_fmc2_ecc {
+	FMC2_ECC_HAM = 1U,
+	FMC2_ECC_BCH4 = 4U,
+	FMC2_ECC_BCH8 = 8U
+};
+
+struct stm32_fmc2_cs_reg {
+	uintptr_t data_base;
+	uintptr_t cmd_base;
+	uintptr_t addr_base;
+};
+
+struct stm32_fmc2_nand_timings {
+	uint8_t tclr;
+	uint8_t tar;
+	uint8_t thiz;
+	uint8_t twait;
+	uint8_t thold_mem;
+	uint8_t tset_mem;
+	uint8_t thold_att;
+	uint8_t tset_att;
+};
+
+struct stm32_fmc2_nfc {
+	uintptr_t reg_base;
+	struct stm32_fmc2_cs_reg cs[MAX_CS];
+	unsigned long clock_id;
+	unsigned int reset_id;
+	uint8_t cs_sel;
+};
+
+static struct stm32_fmc2_nfc stm32_fmc2;
+
+static uintptr_t fmc2_base(void)
+{
+	return stm32_fmc2.reg_base;
+}
+
+static void stm32_fmc2_nand_setup_timing(void)
+{
+	struct stm32_fmc2_nand_timings tims;
+	unsigned long hclk = stm32mp_clk_get_rate(stm32_fmc2.clock_id);
+	unsigned long hclkp = FMC2_PSEC_PER_MSEC / (hclk / 1000U);
+	unsigned long timing, tar, tclr, thiz, twait;
+	unsigned long tset_mem, tset_att, thold_mem, thold_att;
+	uint32_t pcr, pmem, patt;
+
+	tar = MAX(hclkp, NAND_TAR_MIN);
+	timing = div_round_up(tar, hclkp) - 1U;
+	tims.tar = MIN(timing, (unsigned long)FMC2_PCR_TIMING_MASK);
+
+	tclr = MAX(hclkp, NAND_TCLR_MIN);
+	timing = div_round_up(tclr, hclkp) - 1U;
+	tims.tclr = MIN(timing, (unsigned long)FMC2_PCR_TIMING_MASK);
+
+	tims.thiz = FMC2_THIZ;
+	thiz = (tims.thiz + 1U) * hclkp;
+
+	/*
+	 * tWAIT > tRP
+	 * tWAIT > tWP
+	 * tWAIT > tREA + tIO
+	 */
+	twait = MAX(hclkp, NAND_TRP_MIN);
+	twait = MAX(twait, NAND_TWP_MIN);
+	twait = MAX(twait, NAND_TREA_MAX + FMC2_TIO);
+	timing = div_round_up(twait, hclkp);
+	tims.twait = CLAMP(timing, 1UL,
+			   (unsigned long)FMC2_PMEM_PATT_TIMING_MASK);
+
+	/*
+	 * tSETUP_MEM > tCS - tWAIT
+	 * tSETUP_MEM > tALS - tWAIT
+	 * tSETUP_MEM > tDS - (tWAIT - tHIZ)
+	 */
+	tset_mem = hclkp;
+	if ((twait < NAND_TCS_MIN) && (tset_mem < (NAND_TCS_MIN - twait))) {
+		tset_mem = NAND_TCS_MIN - twait;
+	}
+	if ((twait < NAND_TALS_MIN) && (tset_mem < (NAND_TALS_MIN - twait))) {
+		tset_mem = NAND_TALS_MIN - twait;
+	}
+	if ((twait > thiz) && ((twait - thiz) < NAND_TDS_MIN) &&
+	    (tset_mem < (NAND_TDS_MIN - (twait - thiz)))) {
+		tset_mem = NAND_TDS_MIN - (twait - thiz);
+	}
+	timing = div_round_up(tset_mem, hclkp);
+	tims.tset_mem = CLAMP(timing, 1UL,
+			      (unsigned long)FMC2_PMEM_PATT_TIMING_MASK);
+
+	/*
+	 * tHOLD_MEM > tCH
+	 * tHOLD_MEM > tREH - tSETUP_MEM
+	 * tHOLD_MEM > max(tRC, tWC) - (tSETUP_MEM + tWAIT)
+	 */
+	thold_mem = MAX(hclkp, NAND_TCH_MIN);
+	if ((tset_mem < NAND_TREH_MIN) &&
+	    (thold_mem < (NAND_TREH_MIN - tset_mem))) {
+		thold_mem = NAND_TREH_MIN - tset_mem;
+	}
+	if (((tset_mem + twait) < NAND_TRC_MIN) &&
+	    (thold_mem < (NAND_TRC_MIN - (tset_mem + twait)))) {
+		thold_mem = NAND_TRC_MIN  - (tset_mem + twait);
+	}
+	if (((tset_mem + twait) < NAND_TWC_MIN) &&
+	    (thold_mem < (NAND_TWC_MIN - (tset_mem + twait)))) {
+		thold_mem = NAND_TWC_MIN - (tset_mem + twait);
+	}
+	timing = div_round_up(thold_mem, hclkp);
+	tims.thold_mem = CLAMP(timing, 1UL,
+			       (unsigned long)FMC2_PMEM_PATT_TIMING_MASK);
+
+	/*
+	 * tSETUP_ATT > tCS - tWAIT
+	 * tSETUP_ATT > tCLS - tWAIT
+	 * tSETUP_ATT > tALS - tWAIT
+	 * tSETUP_ATT > tRHW - tHOLD_MEM
+	 * tSETUP_ATT > tDS - (tWAIT - tHIZ)
+	 */
+	tset_att = hclkp;
+	if ((twait < NAND_TCS_MIN) && (tset_att < (NAND_TCS_MIN - twait))) {
+		tset_att = NAND_TCS_MIN - twait;
+	}
+	if ((twait < NAND_TCLS_MIN) && (tset_att < (NAND_TCLS_MIN - twait))) {
+		tset_att = NAND_TCLS_MIN - twait;
+	}
+	if ((twait < NAND_TALS_MIN) && (tset_att < (NAND_TALS_MIN - twait))) {
+		tset_att = NAND_TALS_MIN - twait;
+	}
+	if ((thold_mem < NAND_TRHW_MIN) &&
+	    (tset_att < (NAND_TRHW_MIN - thold_mem))) {
+		tset_att = NAND_TRHW_MIN - thold_mem;
+	}
+	if ((twait > thiz) && ((twait - thiz) < NAND_TDS_MIN) &&
+	    (tset_att < (NAND_TDS_MIN - (twait - thiz)))) {
+		tset_att = NAND_TDS_MIN - (twait - thiz);
+	}
+	timing = div_round_up(tset_att, hclkp);
+	tims.tset_att = CLAMP(timing, 1UL,
+			      (unsigned long)FMC2_PMEM_PATT_TIMING_MASK);
+
+	/*
+	 * tHOLD_ATT > tALH
+	 * tHOLD_ATT > tCH
+	 * tHOLD_ATT > tCLH
+	 * tHOLD_ATT > tCOH
+	 * tHOLD_ATT > tDH
+	 * tHOLD_ATT > tWB + tIO + tSYNC - tSETUP_MEM
+	 * tHOLD_ATT > tADL - tSETUP_MEM
+	 * tHOLD_ATT > tWH - tSETUP_MEM
+	 * tHOLD_ATT > tWHR - tSETUP_MEM
+	 * tHOLD_ATT > tRC - (tSETUP_ATT + tWAIT)
+	 * tHOLD_ATT > tWC - (tSETUP_ATT + tWAIT)
+	 */
+	thold_att = MAX(hclkp, NAND_TALH_MIN);
+	thold_att = MAX(thold_att, NAND_TCH_MIN);
+	thold_att = MAX(thold_att, NAND_TCLH_MIN);
+	thold_att = MAX(thold_att, NAND_TCOH_MIN);
+	thold_att = MAX(thold_att, NAND_TDH_MIN);
+	if (((NAND_TWB_MAX + FMC2_TIO + FMC2_TSYNC) > tset_mem) &&
+	    (thold_att < (NAND_TWB_MAX + FMC2_TIO + FMC2_TSYNC - tset_mem))) {
+		thold_att = NAND_TWB_MAX + FMC2_TIO + FMC2_TSYNC - tset_mem;
+	}
+	if ((tset_mem < NAND_TADL_MIN) &&
+	    (thold_att < (NAND_TADL_MIN - tset_mem))) {
+		thold_att = NAND_TADL_MIN - tset_mem;
+	}
+	if ((tset_mem < NAND_TWH_MIN) &&
+	    (thold_att < (NAND_TWH_MIN - tset_mem))) {
+		thold_att = NAND_TWH_MIN - tset_mem;
+	}
+	if ((tset_mem < NAND_TWHR_MIN) &&
+	    (thold_att < (NAND_TWHR_MIN - tset_mem))) {
+		thold_att = NAND_TWHR_MIN - tset_mem;
+	}
+	if (((tset_att + twait) < NAND_TRC_MIN) &&
+	    (thold_att < (NAND_TRC_MIN - (tset_att + twait)))) {
+		thold_att = NAND_TRC_MIN - (tset_att + twait);
+	}
+	if (((tset_att + twait) < NAND_TWC_MIN) &&
+	    (thold_att < (NAND_TWC_MIN - (tset_att + twait)))) {
+		thold_att = NAND_TWC_MIN - (tset_att + twait);
+	}
+	timing = div_round_up(thold_att, hclkp);
+	tims.thold_att = CLAMP(timing, 1UL,
+			       (unsigned long)FMC2_PMEM_PATT_TIMING_MASK);
+
+	VERBOSE("NAND timings: %u - %u - %u - %u - %u - %u - %u - %u\n",
+		tims.tclr, tims.tar, tims.thiz, tims.twait,
+		tims.thold_mem, tims.tset_mem,
+		tims.thold_att, tims.tset_att);
+
+	/* Set tclr/tar timings */
+	pcr = mmio_read_32(fmc2_base() + FMC2_PCR);
+	pcr &= ~FMC2_PCR_TCLR_MASK;
+	pcr |= FMC2_PCR_TCLR(tims.tclr);
+	pcr &= ~FMC2_PCR_TAR_MASK;
+	pcr |= FMC2_PCR_TAR(tims.tar);
+
+	/* Set tset/twait/thold/thiz timings in common bank */
+	pmem = FMC2_PMEM_MEMSET(tims.tset_mem);
+	pmem |= FMC2_PMEM_MEMWAIT(tims.twait);
+	pmem |=	FMC2_PMEM_MEMHOLD(tims.thold_mem);
+	pmem |= FMC2_PMEM_MEMHIZ(tims.thiz);
+
+	/* Set tset/twait/thold/thiz timings in attribute bank */
+	patt = FMC2_PATT_ATTSET(tims.tset_att);
+	patt |= FMC2_PATT_ATTWAIT(tims.twait);
+	patt |= FMC2_PATT_ATTHOLD(tims.thold_att);
+	patt |= FMC2_PATT_ATTHIZ(tims.thiz);
+
+	mmio_write_32(fmc2_base() + FMC2_PCR, pcr);
+	mmio_write_32(fmc2_base() + FMC2_PMEM, pmem);
+	mmio_write_32(fmc2_base() + FMC2_PATT, patt);
+}
+
+static void stm32_fmc2_set_buswidth_16(bool set)
+{
+	mmio_clrsetbits_32(fmc2_base() + FMC2_PCR, FMC2_PCR_PWID_MASK,
+			   (set ? FMC2_PCR_PWID(FMC2_PCR_PWID_16) : 0U));
+}
+
+static void stm32_fmc2_set_ecc(bool enable)
+{
+	mmio_clrsetbits_32(fmc2_base() + FMC2_PCR, FMC2_PCR_ECCEN,
+			   (enable ? FMC2_PCR_ECCEN : 0U));
+}
+
+static int stm32_fmc2_ham_correct(uint8_t *buffer, uint8_t *eccbuffer,
+				  uint8_t *ecc)
+{
+	uint8_t xor_ecc_ones;
+	uint16_t xor_ecc_1b, xor_ecc_2b, xor_ecc_3b;
+	union {
+		uint32_t val;
+		uint8_t  bytes[4];
+	} xor_ecc;
+
+	/* Page size--------ECC_Code Size
+	 * 256---------------22 bits LSB  (ECC_CODE & 0x003FFFFF)
+	 * 512---------------24 bits      (ECC_CODE & 0x00FFFFFF)
+	 * 1024--------------26 bits      (ECC_CODE & 0x03FFFFFF)
+	 * 2048--------------28 bits      (ECC_CODE & 0x0FFFFFFF)
+	 * 4096--------------30 bits      (ECC_CODE & 0x3FFFFFFF)
+	 * 8192--------------32 bits      (ECC_CODE & 0xFFFFFFFF)
+	 */
+
+	/* For Page size 512, ECC_Code size 24 bits */
+	xor_ecc_1b = ecc[0] ^ eccbuffer[0];
+	xor_ecc_2b = ecc[1] ^ eccbuffer[1];
+	xor_ecc_3b = ecc[2] ^ eccbuffer[2];
+
+	xor_ecc.val = 0L;
+	xor_ecc.bytes[2] = xor_ecc_3b;
+	xor_ecc.bytes[1] = xor_ecc_2b;
+	xor_ecc.bytes[0] = xor_ecc_1b;
+
+	if (xor_ecc.val == 0U) {
+		return 0; /* No Error */
+	}
+
+	xor_ecc_ones = __builtin_popcount(xor_ecc.val);
+	if (xor_ecc_ones < 23U) {
+		if (xor_ecc_ones == 12U) {
+			uint16_t bit_address, byte_address;
+
+			/* Correctable ERROR */
+			bit_address = ((xor_ecc_1b >> 1) & BIT(0)) |
+				      ((xor_ecc_1b >> 2) & BIT(1)) |
+				      ((xor_ecc_1b >> 3) & BIT(2));
+
+			byte_address = ((xor_ecc_1b >> 7) & BIT(0)) |
+				       ((xor_ecc_2b) & BIT(1)) |
+				       ((xor_ecc_2b >> 1) & BIT(2)) |
+				       ((xor_ecc_2b >> 2) & BIT(3)) |
+				       ((xor_ecc_2b >> 3) & BIT(4)) |
+				       ((xor_ecc_3b << 4) & BIT(5)) |
+				       ((xor_ecc_3b << 3) & BIT(6)) |
+				       ((xor_ecc_3b << 2) & BIT(7)) |
+				       ((xor_ecc_3b << 1) & BIT(8));
+
+			/* Correct bit error in the data */
+			buffer[byte_address] =
+				buffer[byte_address] ^ BIT(bit_address);
+			VERBOSE("Hamming: 1 ECC error corrected\n");
+
+			return 0;
+		}
+
+		/* Non Correctable ERROR */
+		ERROR("%s: Uncorrectable ECC Errors\n", __func__);
+		return -1;
+	}
+
+	/* ECC ERROR */
+	ERROR("%s: Hamming correction error\n", __func__);
+	return -1;
+}
+
+
+static int stm32_fmc2_ham_calculate(uint8_t *buffer, uint8_t *ecc)
+{
+	uint32_t heccr;
+	uint64_t timeout = timeout_init_us(TIMEOUT_US_10_MS);
+
+	while ((mmio_read_32(fmc2_base() + FMC2_SR) & FMC2_SR_NWRF) == 0U) {
+		if (timeout_elapsed(timeout)) {
+			return -ETIMEDOUT;
+		}
+	}
+
+	heccr = mmio_read_32(fmc2_base() + FMC2_HECCR);
+
+	ecc[0] = heccr;
+	ecc[1] = heccr >> 8;
+	ecc[2] = heccr >> 16;
+
+	/* Disable ECC */
+	stm32_fmc2_set_ecc(false);
+
+	return 0;
+}
+
+static int stm32_fmc2_bch_correct(uint8_t *buffer, unsigned int eccsize)
+{
+	uint32_t bchdsr0, bchdsr1, bchdsr2, bchdsr3, bchdsr4;
+	uint16_t pos[8];
+	int i, den;
+	uint64_t timeout = timeout_init_us(TIMEOUT_US_10_MS);
+
+	while ((mmio_read_32(fmc2_base() + FMC2_BCHISR) &
+		FMC2_BCHISR_DERF) == 0U) {
+		if (timeout_elapsed(timeout)) {
+			return -ETIMEDOUT;
+		}
+	}
+
+	bchdsr0 = mmio_read_32(fmc2_base() + FMC2_BCHDSR0);
+	bchdsr1 = mmio_read_32(fmc2_base() + FMC2_BCHDSR1);
+	bchdsr2 = mmio_read_32(fmc2_base() + FMC2_BCHDSR2);
+	bchdsr3 = mmio_read_32(fmc2_base() + FMC2_BCHDSR3);
+	bchdsr4 = mmio_read_32(fmc2_base() + FMC2_BCHDSR4);
+
+	/* Disable ECC */
+	stm32_fmc2_set_ecc(false);
+
+	/* No error found */
+	if ((bchdsr0 & FMC2_BCHDSR0_DEF) == 0U) {
+		return 0;
+	}
+
+	/* Too many errors detected */
+	if ((bchdsr0 & FMC2_BCHDSR0_DUE) != 0U) {
+		return -EBADMSG;
+	}
+
+	pos[0] = bchdsr1 & FMC2_BCHDSR1_EBP1_MASK;
+	pos[1] = (bchdsr1 & FMC2_BCHDSR1_EBP2_MASK) >> FMC2_BCHDSR1_EBP2_SHIFT;
+	pos[2] = bchdsr2 & FMC2_BCHDSR2_EBP3_MASK;
+	pos[3] = (bchdsr2 & FMC2_BCHDSR2_EBP4_MASK) >> FMC2_BCHDSR2_EBP4_SHIFT;
+	pos[4] = bchdsr3 & FMC2_BCHDSR3_EBP5_MASK;
+	pos[5] = (bchdsr3 & FMC2_BCHDSR3_EBP6_MASK) >> FMC2_BCHDSR3_EBP6_SHIFT;
+	pos[6] = bchdsr4 & FMC2_BCHDSR4_EBP7_MASK;
+	pos[7] = (bchdsr4 & FMC2_BCHDSR4_EBP8_MASK) >> FMC2_BCHDSR4_EBP8_SHIFT;
+
+	den = (bchdsr0 & FMC2_BCHDSR0_DEN_MASK) >> FMC2_BCHDSR0_DEN_SHIFT;
+	for (i = 0; i < den; i++) {
+		if (pos[i] < (eccsize * 8U)) {
+			uint8_t bitmask = BIT(pos[i] % 8U);
+			uint32_t offset = pos[i] / 8U;
+
+			*(buffer + offset) ^= bitmask;
+		}
+	}
+
+	return 0;
+}
+
+static void stm32_fmc2_hwctl(struct nand_device *nand)
+{
+	stm32_fmc2_set_ecc(false);
+
+	if (nand->ecc.max_bit_corr != FMC2_ECC_HAM) {
+		mmio_clrbits_32(fmc2_base() + FMC2_PCR, FMC2_PCR_WEN);
+	}
+
+	stm32_fmc2_set_ecc(true);
+}
+
+static int stm32_fmc2_read_page(struct nand_device *nand,
+				unsigned int page, uintptr_t buffer)
+{
+	unsigned int eccsize = nand->ecc.size;
+	unsigned int eccbytes = nand->ecc.bytes;
+	unsigned int eccsteps = nand->page_size / eccsize;
+	uint8_t ecc_corr[FMC2_MAX_ECC_BYTES];
+	uint8_t ecc_cal[FMC2_MAX_ECC_BYTES] = {0U};
+	uint8_t *p;
+	unsigned int i;
+	unsigned int s;
+	int ret;
+
+	VERBOSE(">%s page %i buffer %lx\n", __func__, page, buffer);
+
+	ret = nand_read_page_cmd(page, 0U, 0U, 0U);
+	if (ret != 0) {
+		return ret;
+	}
+
+	for (s = 0U, i = nand->page_size + FMC2_BBM_LEN, p = (uint8_t *)buffer;
+	     s < eccsteps;
+	     s++, i += eccbytes, p += eccsize) {
+		stm32_fmc2_hwctl(nand);
+
+		/* Read the NAND page sector (512 bytes) */
+		ret = nand_change_read_column_cmd(s * eccsize, (uintptr_t)p,
+						  eccsize);
+		if (ret != 0) {
+			return ret;
+		}
+
+		if (nand->ecc.max_bit_corr == FMC2_ECC_HAM) {
+			ret = stm32_fmc2_ham_calculate(p, ecc_cal);
+			if (ret != 0) {
+				return ret;
+			}
+		}
+
+		/* Read the corresponding ECC bytes */
+		ret = nand_change_read_column_cmd(i, (uintptr_t)ecc_corr,
+						  eccbytes);
+		if (ret != 0) {
+			return ret;
+		}
+
+		/* Correct the data */
+		if (nand->ecc.max_bit_corr == FMC2_ECC_HAM) {
+			ret = stm32_fmc2_ham_correct(p, ecc_corr, ecc_cal);
+		} else {
+			ret = stm32_fmc2_bch_correct(p, eccsize);
+		}
+
+		if (ret != 0) {
+			return ret;
+		}
+	}
+
+	return 0;
+}
+
+static void stm32_fmc2_read_data(struct nand_device *nand,
+				 uint8_t *buff, unsigned int length,
+				 bool use_bus8)
+{
+	uintptr_t data_base = stm32_fmc2.cs[stm32_fmc2.cs_sel].data_base;
+
+	if (use_bus8 && (nand->buswidth == NAND_BUS_WIDTH_16)) {
+		stm32_fmc2_set_buswidth_16(false);
+	}
+
+	if ((((uintptr_t)buff & BIT(0)) != 0U) && (length != 0U)) {
+		*buff = mmio_read_8(data_base);
+		buff += sizeof(uint8_t);
+		length -= sizeof(uint8_t);
+	}
+
+	if ((((uintptr_t)buff & GENMASK_32(1, 0)) != 0U) &&
+	    (length >= sizeof(uint16_t))) {
+		*(uint16_t *)buff = mmio_read_16(data_base);
+		buff += sizeof(uint16_t);
+		length -= sizeof(uint16_t);
+	}
+
+	/* 32bit aligned */
+	while (length >= sizeof(uint32_t)) {
+		*(uint32_t *)buff = mmio_read_32(data_base);
+		buff += sizeof(uint32_t);
+		length -= sizeof(uint32_t);
+	}
+
+	/* Read remaining bytes */
+	if (length >= sizeof(uint16_t)) {
+		*(uint16_t *)buff = mmio_read_16(data_base);
+		buff += sizeof(uint16_t);
+		length -= sizeof(uint16_t);
+	}
+
+	if (length != 0U) {
+		*buff = mmio_read_8(data_base);
+	}
+
+	if (use_bus8 && (nand->buswidth == NAND_BUS_WIDTH_16)) {
+		/* Reconfigure bus width to 16-bit */
+		stm32_fmc2_set_buswidth_16(true);
+	}
+}
+
+static void stm32_fmc2_write_data(struct nand_device *nand,
+				  uint8_t *buff, unsigned int length,
+				  bool use_bus8)
+{
+	uintptr_t data_base = stm32_fmc2.cs[stm32_fmc2.cs_sel].data_base;
+
+	if (use_bus8 && (nand->buswidth == NAND_BUS_WIDTH_16)) {
+		/* Reconfigure bus width to 8-bit */
+		stm32_fmc2_set_buswidth_16(false);
+	}
+
+	if ((((uintptr_t)buff & BIT(0)) != 0U) && (length != 0U)) {
+		mmio_write_8(data_base, *buff);
+		buff += sizeof(uint8_t);
+		length -= sizeof(uint8_t);
+	}
+
+	if ((((uintptr_t)buff & GENMASK_32(1, 0)) != 0U) &&
+	    (length >= sizeof(uint16_t))) {
+		mmio_write_16(data_base, *(uint16_t *)buff);
+		buff += sizeof(uint16_t);
+		length -= sizeof(uint16_t);
+	}
+
+	/* 32bits aligned */
+	while (length >= sizeof(uint32_t)) {
+		mmio_write_32(data_base, *(uint32_t *)buff);
+		buff += sizeof(uint32_t);
+		length -= sizeof(uint32_t);
+	}
+
+	/* Read remaining bytes */
+	if (length >= sizeof(uint16_t)) {
+		mmio_write_16(data_base, *(uint16_t *)buff);
+		buff += sizeof(uint16_t);
+		length -= sizeof(uint16_t);
+	}
+
+	if (length != 0U) {
+		mmio_write_8(data_base, *buff);
+	}
+
+	if (use_bus8 && (nand->buswidth == NAND_BUS_WIDTH_16)) {
+		/* Reconfigure bus width to 16-bit */
+		stm32_fmc2_set_buswidth_16(true);
+	}
+}
+
+static void stm32_fmc2_ctrl_init(void)
+{
+	uint32_t pcr = mmio_read_32(fmc2_base() + FMC2_PCR);
+	uint32_t bcr1 = mmio_read_32(fmc2_base() + FMC2_BCR1);
+
+	/* Enable wait feature and NAND flash memory bank */
+	pcr |= FMC2_PCR_PWAITEN;
+	pcr |= FMC2_PCR_PBKEN;
+
+	/* Set buswidth to 8 bits mode for identification */
+	pcr &= ~FMC2_PCR_PWID_MASK;
+
+	/* ECC logic is disabled */
+	pcr &= ~FMC2_PCR_ECCEN;
+
+	/* Default mode */
+	pcr &= ~FMC2_PCR_ECCALG;
+	pcr &= ~FMC2_PCR_BCHECC;
+	pcr &= ~FMC2_PCR_WEN;
+
+	/* Set default ECC sector size */
+	pcr &= ~FMC2_PCR_ECCSS_MASK;
+	pcr |= FMC2_PCR_ECCSS(FMC2_PCR_ECCSS_2048);
+
+	/* Set default TCLR/TAR timings */
+	pcr &= ~FMC2_PCR_TCLR_MASK;
+	pcr |= FMC2_PCR_TCLR(FMC2_PCR_TCLR_DEFAULT);
+	pcr &= ~FMC2_PCR_TAR_MASK;
+	pcr |= FMC2_PCR_TAR(FMC2_PCR_TAR_DEFAULT);
+
+	/* Enable FMC2 controller */
+	bcr1 |= FMC2_BCR1_FMC2EN;
+
+	mmio_write_32(fmc2_base() + FMC2_BCR1, bcr1);
+	mmio_write_32(fmc2_base() + FMC2_PCR, pcr);
+	mmio_write_32(fmc2_base() + FMC2_PMEM, FMC2_PMEM_DEFAULT);
+	mmio_write_32(fmc2_base() + FMC2_PATT, FMC2_PATT_DEFAULT);
+}
+
+static int stm32_fmc2_exec(struct nand_req *req)
+{
+	int ret = 0;
+
+	switch (req->type & NAND_REQ_MASK) {
+	case NAND_REQ_CMD:
+		VERBOSE("Write CMD %x\n", (uint8_t)req->type);
+		mmio_write_8(stm32_fmc2.cs[stm32_fmc2.cs_sel].cmd_base,
+			     (uint8_t)req->type);
+		break;
+	case NAND_REQ_ADDR:
+		VERBOSE("Write ADDR %x\n", *(req->addr));
+		mmio_write_8(stm32_fmc2.cs[stm32_fmc2.cs_sel].addr_base,
+			     *(req->addr));
+		break;
+	case NAND_REQ_DATAIN:
+		VERBOSE("Read data\n");
+		stm32_fmc2_read_data(req->nand, req->addr, req->length,
+				     ((req->type & NAND_REQ_BUS_WIDTH_8) !=
+				      0U));
+		break;
+	case NAND_REQ_DATAOUT:
+		VERBOSE("Write data\n");
+		stm32_fmc2_write_data(req->nand, req->addr, req->length,
+				      ((req->type & NAND_REQ_BUS_WIDTH_8) !=
+				      0U));
+		break;
+	case NAND_REQ_WAIT:
+		VERBOSE("WAIT Ready\n");
+		ret = nand_wait_ready(req->delay_ms);
+		break;
+	default:
+		ret = -EINVAL;
+		break;
+	};
+
+	return ret;
+}
+
+static void stm32_fmc2_setup(struct nand_device *nand)
+{
+	uint32_t pcr = mmio_read_32(fmc2_base() + FMC2_PCR);
+
+	/* Set buswidth */
+	pcr &= ~FMC2_PCR_PWID_MASK;
+	if (nand->buswidth == NAND_BUS_WIDTH_16) {
+		pcr |= FMC2_PCR_PWID(FMC2_PCR_PWID_16);
+	}
+
+	if (nand->ecc.mode == NAND_ECC_HW) {
+		nand->mtd_read_page = stm32_fmc2_read_page;
+
+		pcr &= ~FMC2_PCR_ECCALG;
+		pcr &= ~FMC2_PCR_BCHECC;
+
+		pcr &= ~FMC2_PCR_ECCSS_MASK;
+		pcr |= FMC2_PCR_ECCSS(FMC2_PCR_ECCSS_512);
+
+		switch (nand->ecc.max_bit_corr) {
+		case FMC2_ECC_HAM:
+			nand->ecc.bytes = 3;
+			break;
+		case FMC2_ECC_BCH8:
+			pcr |= FMC2_PCR_ECCALG;
+			pcr |= FMC2_PCR_BCHECC;
+			nand->ecc.bytes = 13;
+			break;
+		default:
+			/* Use FMC2 ECC BCH4 */
+			pcr |= FMC2_PCR_ECCALG;
+			nand->ecc.bytes = 7;
+			break;
+		}
+
+		if ((nand->buswidth & NAND_BUS_WIDTH_16) != 0) {
+			nand->ecc.bytes++;
+		}
+	}
+
+	mmio_write_32(stm32_fmc2.reg_base + FMC2_PCR, pcr);
+}
+
+static const struct nand_ctrl_ops ctrl_ops = {
+	.setup = stm32_fmc2_setup,
+	.exec = stm32_fmc2_exec
+};
+
+int stm32_fmc2_init(void)
+{
+	int fmc_node;
+	int fmc_subnode = 0;
+	int nchips = 0;
+	unsigned int i;
+	void *fdt = NULL;
+	const fdt32_t *cuint;
+	struct dt_node_info info;
+
+	if (fdt_get_address(&fdt) == 0) {
+		return -FDT_ERR_NOTFOUND;
+	}
+
+	fmc_node = dt_get_node(&info, -1, DT_FMC2_COMPAT);
+	if (fmc_node == -FDT_ERR_NOTFOUND) {
+		WARN("No FMC2 node found\n");
+		return fmc_node;
+	}
+
+	if (info.status == DT_DISABLED) {
+		return -FDT_ERR_NOTFOUND;
+	}
+
+	stm32_fmc2.reg_base = info.base;
+
+	if ((info.clock < 0) || (info.reset < 0)) {
+		return -FDT_ERR_BADVALUE;
+	}
+
+	stm32_fmc2.clock_id = (unsigned long)info.clock;
+	stm32_fmc2.reset_id = (unsigned int)info.reset;
+
+	cuint = fdt_getprop(fdt, fmc_node, "reg", NULL);
+	if (cuint == NULL) {
+		return -FDT_ERR_BADVALUE;
+	}
+
+	cuint += 2;
+
+	for (i = 0U; i < MAX_CS; i++) {
+		stm32_fmc2.cs[i].data_base = fdt32_to_cpu(*cuint);
+		stm32_fmc2.cs[i].cmd_base = fdt32_to_cpu(*(cuint + 2));
+		stm32_fmc2.cs[i].addr_base = fdt32_to_cpu(*(cuint + 4));
+		cuint += 6;
+	}
+
+	/* Pinctrl initialization */
+	if (dt_set_pinctrl_config(fmc_node) != 0) {
+		return -FDT_ERR_BADVALUE;
+	}
+
+	/* Parse flash nodes */
+	fdt_for_each_subnode(fmc_subnode, fdt, fmc_node) {
+		nchips++;
+	}
+
+	if (nchips != 1) {
+		WARN("Only one SLC NAND device supported\n");
+		return -FDT_ERR_BADVALUE;
+	}
+
+	fdt_for_each_subnode(fmc_subnode, fdt, fmc_node) {
+		/* Get chip select */
+		cuint = fdt_getprop(fdt, fmc_subnode, "reg", NULL);
+		if (cuint == NULL) {
+			WARN("Chip select not well defined\n");
+			return -FDT_ERR_BADVALUE;
+		}
+		stm32_fmc2.cs_sel = fdt32_to_cpu(*cuint);
+		VERBOSE("NAND CS %i\n", stm32_fmc2.cs_sel);
+	}
+
+	/* Enable Clock */
+	stm32mp_clk_enable(stm32_fmc2.clock_id);
+
+	/* Reset IP */
+	stm32mp_reset_assert(stm32_fmc2.reset_id);
+	stm32mp_reset_deassert(stm32_fmc2.reset_id);
+
+	/* Setup default IP registers */
+	stm32_fmc2_ctrl_init();
+
+	/* Setup default timings */
+	stm32_fmc2_nand_setup_timing();
+
+	/* Init NAND RAW framework */
+	nand_raw_ctrl_init(&ctrl_ops);
+
+	return 0;
+}
diff --git a/drivers/st/gpio/stm32_gpio.c b/drivers/st/gpio/stm32_gpio.c
index 343ad6c1d..a13c341a8 100644
--- a/drivers/st/gpio/stm32_gpio.c
+++ b/drivers/st/gpio/stm32_gpio.c
@@ -165,7 +165,7 @@ int dt_set_pinctrl_config(int node)
 	void *fdt;
 
 	if (fdt_get_address(&fdt) == 0) {
-		return -ENOENT;
+		return -FDT_ERR_NOTFOUND;
 	}
 
 	if (status == DT_DISABLED) {
diff --git a/drivers/st/io/io_mmc.c b/drivers/st/io/io_mmc.c
index a239b5f3a..44b7d1907 100644
--- a/drivers/st/io/io_mmc.c
+++ b/drivers/st/io/io_mmc.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -20,14 +20,15 @@ static int mmc_dev_open(const uintptr_t init_params, io_dev_info_t **dev_info);
 static int mmc_block_open(io_dev_info_t *dev_info, const uintptr_t spec,
 			  io_entity_t *entity);
 static int mmc_dev_init(io_dev_info_t *dev_info, const uintptr_t init_params);
-static int mmc_block_seek(io_entity_t *entity, int mode, ssize_t offset);
+static int mmc_block_seek(io_entity_t *entity, int mode,
+			  signed long long offset);
 static int mmc_block_read(io_entity_t *entity, uintptr_t buffer, size_t length,
 			  size_t *length_read);
 static int mmc_block_close(io_entity_t *entity);
 static int mmc_dev_close(io_dev_info_t *dev_info);
 static io_type_t device_type_mmc(void);
 
-static ssize_t seek_offset;
+static signed long long seek_offset;
 
 static const io_dev_connector_t mmc_dev_connector = {
 	.dev_open = mmc_dev_open
@@ -85,7 +86,8 @@ static int mmc_block_open(io_dev_info_t *dev_info, const  uintptr_t spec,
 }
 
 /* Seek to a particular file offset on the mmc device */
-static int mmc_block_seek(io_entity_t *entity, int mode, ssize_t offset)
+static int mmc_block_seek(io_entity_t *entity, int mode,
+			  signed long long offset)
 {
 	seek_offset = offset;
 	return 0;
diff --git a/drivers/st/io/io_stm32image.c b/drivers/st/io/io_stm32image.c
index dc2977d5a..413521b1e 100644
--- a/drivers/st/io/io_stm32image.c
+++ b/drivers/st/io/io_stm32image.c
@@ -242,45 +242,11 @@ static int stm32image_partition_size(io_entity_t *entity, size_t *length)
 	return 0;
 }
 
-static int check_header(boot_api_image_header_t *header, uintptr_t buffer)
-{
-	uint32_t i;
-	uint32_t img_checksum = 0;
-
-	/*
-	 * Check header/payload validity:
-	 *	- Header magic
-	 *	- Header version
-	 *	- Payload checksum
-	 */
-	if (header->magic != BOOT_API_IMAGE_HEADER_MAGIC_NB) {
-		ERROR("Header magic\n");
-		return -EINVAL;
-	}
-
-	if (header->header_version != BOOT_API_HEADER_VERSION) {
-		ERROR("Header version\n");
-		return -EINVAL;
-	}
-
-	for (i = 0; i < header->image_length; i++) {
-		img_checksum += *(uint8_t *)(buffer + i);
-	}
-
-	if (header->payload_checksum != img_checksum) {
-		ERROR("Checksum: 0x%x (awaited: 0x%x)\n", img_checksum,
-		      header->payload_checksum);
-		return -EINVAL;
-	}
-
-	return 0;
-}
-
 /* Read data from a partition */
 static int stm32image_partition_read(io_entity_t *entity, uintptr_t buffer,
 				     size_t length, size_t *length_read)
 {
-	int result = 0;
+	int result;
 	uint8_t *local_buffer = (uint8_t *)buffer;
 	boot_api_image_header_t *header =
 		(boot_api_image_header_t *)first_lba_buffer;
@@ -368,13 +334,19 @@ static int stm32image_partition_read(io_entity_t *entity, uintptr_t buffer,
 			continue;
 		}
 
-		result = check_header(header, buffer);
+		result = stm32mp_check_header(header, buffer);
 		if (result != 0) {
 			ERROR("Header check failed\n");
 			*length_read = 0;
 			header->magic = 0;
 		}
 
+		result = stm32mp_auth_image(header, buffer);
+		if (result != 0) {
+			ERROR("Authentication Failed (%i)\n", result);
+			return result;
+		}
+
 		io_close(backend_handle);
 	}
 
diff --git a/drivers/st/iwdg/stm32_iwdg.c b/drivers/st/iwdg/stm32_iwdg.c
new file mode 100644
index 000000000..ea6fbb2b9
--- /dev/null
+++ b/drivers/st/iwdg/stm32_iwdg.c
@@ -0,0 +1,150 @@
+/*
+ * Copyright (c) 2017-2019, STMicroelectronics - All Rights Reserved
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <assert.h>
+#include <errno.h>
+#include <string.h>
+
+#include <libfdt.h>
+
+#include <platform_def.h>
+
+#include <arch_helpers.h>
+#include <common/debug.h>
+#include <drivers/arm/gicv2.h>
+#include <drivers/delay_timer.h>
+#include <drivers/st/stm32_iwdg.h>
+#include <drivers/st/stm32mp_clkfunc.h>
+#include <lib/mmio.h>
+#include <lib/utils.h>
+#include <plat/common/platform.h>
+
+/* IWDG registers offsets */
+#define IWDG_KR_OFFSET		0x00U
+
+/* Registers values */
+#define IWDG_KR_RELOAD_KEY	0xAAAA
+
+struct stm32_iwdg_instance {
+	uintptr_t base;
+	unsigned long clock;
+	uint8_t flags;
+	int num_irq;
+};
+
+static struct stm32_iwdg_instance stm32_iwdg[IWDG_MAX_INSTANCE];
+
+static int stm32_iwdg_get_dt_node(struct dt_node_info *info, int offset)
+{
+	int node;
+
+	node = dt_get_node(info, offset, DT_IWDG_COMPAT);
+	if (node < 0) {
+		if (offset == -1) {
+			VERBOSE("%s: No IDWG found\n", __func__);
+		}
+		return -FDT_ERR_NOTFOUND;
+	}
+
+	return node;
+}
+
+void stm32_iwdg_refresh(void)
+{
+	uint8_t i;
+
+	for (i = 0U; i < IWDG_MAX_INSTANCE; i++) {
+		struct stm32_iwdg_instance *iwdg = &stm32_iwdg[i];
+
+		/* 0x00000000 is not a valid address for IWDG peripherals */
+		if (iwdg->base != 0U) {
+			stm32mp_clk_enable(iwdg->clock);
+
+			mmio_write_32(iwdg->base + IWDG_KR_OFFSET,
+				      IWDG_KR_RELOAD_KEY);
+
+			stm32mp_clk_disable(iwdg->clock);
+		}
+	}
+}
+
+int stm32_iwdg_init(void)
+{
+	int node = -1;
+	struct dt_node_info dt_info;
+	void *fdt;
+	uint32_t __unused count = 0;
+
+	if (fdt_get_address(&fdt) == 0) {
+		panic();
+	}
+
+	for (node = stm32_iwdg_get_dt_node(&dt_info, node);
+	     node != -FDT_ERR_NOTFOUND;
+	     node = stm32_iwdg_get_dt_node(&dt_info, node)) {
+		struct stm32_iwdg_instance *iwdg;
+		uint32_t hw_init;
+		uint32_t idx;
+
+		count++;
+
+		idx = stm32_iwdg_get_instance(dt_info.base);
+		iwdg = &stm32_iwdg[idx];
+		iwdg->base = dt_info.base;
+		iwdg->clock = (unsigned long)dt_info.clock;
+
+		/* DT can specify low power cases */
+		if (fdt_getprop(fdt, node, "stm32,enable-on-stop", NULL) ==
+		    NULL) {
+			iwdg->flags |= IWDG_DISABLE_ON_STOP;
+		}
+
+		if (fdt_getprop(fdt, node, "stm32,enable-on-standby", NULL) ==
+		    NULL) {
+			iwdg->flags |= IWDG_DISABLE_ON_STANDBY;
+		}
+
+		/* Explicit list of supported bit flags */
+		hw_init = stm32_iwdg_get_otp_config(idx);
+
+		if ((hw_init & IWDG_HW_ENABLED) != 0) {
+			if (dt_info.status == DT_DISABLED) {
+				ERROR("OTP enabled but iwdg%u DT-disabled\n",
+				      idx + 1U);
+				panic();
+			}
+			iwdg->flags |= IWDG_HW_ENABLED;
+		}
+
+		if (dt_info.status == DT_DISABLED) {
+			zeromem((void *)iwdg,
+				sizeof(struct stm32_iwdg_instance));
+			continue;
+		}
+
+		if ((hw_init & IWDG_DISABLE_ON_STOP) != 0) {
+			iwdg->flags |= IWDG_DISABLE_ON_STOP;
+		}
+
+		if ((hw_init & IWDG_DISABLE_ON_STANDBY) != 0) {
+			iwdg->flags |= IWDG_DISABLE_ON_STANDBY;
+		}
+
+		VERBOSE("IWDG%u found, %ssecure\n", idx + 1U,
+			((dt_info.status & DT_NON_SECURE) != 0) ?
+			"non-" : "");
+
+#if defined(IMAGE_BL2)
+		if (stm32_iwdg_shadow_update(idx, iwdg->flags) != BSEC_OK) {
+			return -1;
+		}
+#endif
+	}
+
+	VERBOSE("%u IWDG instance%s found\n", count, (count > 1U) ? "s" : "");
+
+	return 0;
+}
diff --git a/drivers/st/mmc/stm32_sdmmc2.c b/drivers/st/mmc/stm32_sdmmc2.c
index f453ce9a5..24e6efe98 100644
--- a/drivers/st/mmc/stm32_sdmmc2.c
+++ b/drivers/st/mmc/stm32_sdmmc2.c
@@ -71,20 +71,14 @@
 #define SDMMC_DCTRLR_DTEN		BIT(0)
 #define SDMMC_DCTRLR_DTDIR		BIT(1)
 #define SDMMC_DCTRLR_DTMODE		GENMASK(3, 2)
-#define SDMMC_DCTRLR_DBLOCKSIZE_0	BIT(4)
-#define SDMMC_DCTRLR_DBLOCKSIZE_1	BIT(5)
-#define SDMMC_DCTRLR_DBLOCKSIZE_3	BIT(7)
 #define SDMMC_DCTRLR_DBLOCKSIZE		GENMASK(7, 4)
+#define SDMMC_DCTRLR_DBLOCKSIZE_SHIFT	4
 #define SDMMC_DCTRLR_FIFORST		BIT(13)
 
 #define SDMMC_DCTRLR_CLEAR_MASK		(SDMMC_DCTRLR_DTEN | \
 					 SDMMC_DCTRLR_DTDIR | \
 					 SDMMC_DCTRLR_DTMODE | \
 					 SDMMC_DCTRLR_DBLOCKSIZE)
-#define SDMMC_DBLOCKSIZE_8		(SDMMC_DCTRLR_DBLOCKSIZE_0 | \
-					 SDMMC_DCTRLR_DBLOCKSIZE_1)
-#define SDMMC_DBLOCKSIZE_512		(SDMMC_DCTRLR_DBLOCKSIZE_0 | \
-					 SDMMC_DCTRLR_DBLOCKSIZE_3)
 
 /* SDMMC status register */
 #define SDMMC_STAR_CCRCFAIL		BIT(0)
@@ -152,10 +146,14 @@ bool plat_sdmmc2_use_dma(unsigned int instance, unsigned int memory)
 static void stm32_sdmmc2_init(void)
 {
 	uint32_t clock_div;
+	uint32_t freq = STM32MP_MMC_INIT_FREQ;
 	uintptr_t base = sdmmc2_params.reg_base;
 
-	clock_div = div_round_up(sdmmc2_params.clk_rate,
-				 STM32MP_MMC_INIT_FREQ * 2);
+	if (sdmmc2_params.max_freq != 0U) {
+		freq = MIN(sdmmc2_params.max_freq, freq);
+	}
+
+	clock_div = div_round_up(sdmmc2_params.clk_rate, freq * 2U);
 
 	mmio_write_32(base + SDMMC_CLKCR, SDMMC_CLKCR_HWFC_EN | clock_div |
 		      sdmmc2_params.negedge |
@@ -406,7 +404,7 @@ static int stm32_sdmmc2_set_ios(unsigned int clk, unsigned int width)
 {
 	uintptr_t base = sdmmc2_params.reg_base;
 	uint32_t bus_cfg = 0;
-	uint32_t clock_div, max_freq;
+	uint32_t clock_div, max_freq, freq;
 	uint32_t clk_rate = sdmmc2_params.clk_rate;
 	uint32_t max_bus_freq = sdmmc2_params.device_info->max_bus_freq;
 
@@ -438,7 +436,13 @@ static int stm32_sdmmc2_set_ios(unsigned int clk, unsigned int width)
 		}
 	}
 
-	clock_div = div_round_up(clk_rate, max_freq * 2);
+	if (sdmmc2_params.max_freq != 0U) {
+		freq = MIN(sdmmc2_params.max_freq, max_freq);
+	} else {
+		freq = max_freq;
+	}
+
+	clock_div = div_round_up(clk_rate, freq * 2U);
 
 	mmio_write_32(base + SDMMC_CLKCR,
 		      SDMMC_CLKCR_HWFC_EN | clock_div | bus_cfg |
@@ -454,11 +458,14 @@ static int stm32_sdmmc2_prepare(int lba, uintptr_t buf, size_t size)
 	int ret;
 	uintptr_t base = sdmmc2_params.reg_base;
 	uint32_t data_ctrl = SDMMC_DCTRLR_DTDIR;
+	uint32_t arg_size;
+
+	assert(size != 0U);
 
-	if (size == 8U) {
-		data_ctrl |= SDMMC_DBLOCKSIZE_8;
+	if (size > MMC_BLOCK_SIZE) {
+		arg_size = MMC_BLOCK_SIZE;
 	} else {
-		data_ctrl |= SDMMC_DBLOCKSIZE_512;
+		arg_size = size;
 	}
 
 	sdmmc2_params.use_dma = plat_sdmmc2_use_dma(base, buf);
@@ -477,12 +484,7 @@ static int stm32_sdmmc2_prepare(int lba, uintptr_t buf, size_t size)
 	zeromem(&cmd, sizeof(struct mmc_cmd));
 
 	cmd.cmd_idx = MMC_CMD(16);
-	if (size > MMC_BLOCK_SIZE) {
-		cmd.cmd_arg = MMC_BLOCK_SIZE;
-	} else {
-		cmd.cmd_arg = size;
-	}
-
+	cmd.cmd_arg = arg_size;
 	cmd.resp_type = MMC_RESPONSE_R1;
 
 	ret = stm32_sdmmc2_send_cmd(&cmd);
@@ -504,6 +506,8 @@ static int stm32_sdmmc2_prepare(int lba, uintptr_t buf, size_t size)
 		flush_dcache_range(buf, size);
 	}
 
+	data_ctrl |= __builtin_ctz(arg_size) << SDMMC_DCTRLR_DBLOCKSIZE_SHIFT;
+
 	mmio_clrsetbits_32(base + SDMMC_DCTRLR,
 			   SDMMC_DCTRLR_CLEAR_MASK,
 			   data_ctrl);
@@ -692,6 +696,11 @@ static int stm32_sdmmc2_dt_get_config(void)
 		}
 	}
 
+	cuint = fdt_getprop(fdt, sdmmc_node, "max-frequency", NULL);
+	if (cuint != NULL) {
+		sdmmc2_params.max_freq = fdt32_to_cpu(*cuint);
+	}
+
 	return 0;
 }
 
diff --git a/drivers/st/pmic/stm32mp_pmic.c b/drivers/st/pmic/stm32mp_pmic.c
index 6fe51f443..9e9dddc4d 100644
--- a/drivers/st/pmic/stm32mp_pmic.c
+++ b/drivers/st/pmic/stm32mp_pmic.c
@@ -299,6 +299,7 @@ int pmic_ddr_power_init(enum ddr_type ddr_type)
 		break;
 
 	case STM32MP_LPDDR2:
+	case STM32MP_LPDDR3:
 		/*
 		 * Set LDO3 to 1.8V
 		 * Set LDO3 to bypass mode if BUCK3 = 1.8V
diff --git a/drivers/st/spi/stm32_qspi.c b/drivers/st/spi/stm32_qspi.c
new file mode 100644
index 000000000..188d2ff80
--- /dev/null
+++ b/drivers/st/spi/stm32_qspi.c
@@ -0,0 +1,500 @@
+/*
+ * Copyright (c) 2019, STMicroelectronics - All Rights Reserved
+ *
+ * SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
+ */
+
+#include <libfdt.h>
+
+#include <platform_def.h>
+
+#include <common/debug.h>
+#include <drivers/delay_timer.h>
+#include <drivers/spi_mem.h>
+#include <drivers/st/stm32_gpio.h>
+#include <drivers/st/stm32mp_reset.h>
+#include <lib/mmio.h>
+#include <lib/utils_def.h>
+
+/* QUADSPI registers */
+#define QSPI_CR			0x00U
+#define QSPI_DCR		0x04U
+#define QSPI_SR			0x08U
+#define QSPI_FCR		0x0CU
+#define QSPI_DLR		0x10U
+#define QSPI_CCR		0x14U
+#define QSPI_AR			0x18U
+#define QSPI_ABR		0x1CU
+#define QSPI_DR			0x20U
+#define QSPI_PSMKR		0x24U
+#define QSPI_PSMAR		0x28U
+#define QSPI_PIR		0x2CU
+#define QSPI_LPTR		0x30U
+
+/* QUADSPI control register */
+#define QSPI_CR_EN		BIT(0)
+#define QSPI_CR_ABORT		BIT(1)
+#define QSPI_CR_DMAEN		BIT(2)
+#define QSPI_CR_TCEN		BIT(3)
+#define QSPI_CR_SSHIFT		BIT(4)
+#define QSPI_CR_DFM		BIT(6)
+#define QSPI_CR_FSEL		BIT(7)
+#define QSPI_CR_FTHRES_SHIFT	8U
+#define QSPI_CR_TEIE		BIT(16)
+#define QSPI_CR_TCIE		BIT(17)
+#define QSPI_CR_FTIE		BIT(18)
+#define QSPI_CR_SMIE		BIT(19)
+#define QSPI_CR_TOIE		BIT(20)
+#define QSPI_CR_APMS		BIT(22)
+#define QSPI_CR_PMM		BIT(23)
+#define QSPI_CR_PRESCALER_MASK	GENMASK_32(31, 24)
+#define QSPI_CR_PRESCALER_SHIFT	24U
+
+/* QUADSPI device configuration register */
+#define QSPI_DCR_CKMODE		BIT(0)
+#define QSPI_DCR_CSHT_MASK	GENMASK_32(10, 8)
+#define QSPI_DCR_CSHT_SHIFT	8U
+#define QSPI_DCR_FSIZE_MASK	GENMASK_32(20, 16)
+#define QSPI_DCR_FSIZE_SHIFT	16U
+
+/* QUADSPI status register */
+#define QSPI_SR_TEF		BIT(0)
+#define QSPI_SR_TCF		BIT(1)
+#define QSPI_SR_FTF		BIT(2)
+#define QSPI_SR_SMF		BIT(3)
+#define QSPI_SR_TOF		BIT(4)
+#define QSPI_SR_BUSY		BIT(5)
+
+/* QUADSPI flag clear register */
+#define QSPI_FCR_CTEF		BIT(0)
+#define QSPI_FCR_CTCF		BIT(1)
+#define QSPI_FCR_CSMF		BIT(3)
+#define QSPI_FCR_CTOF		BIT(4)
+
+/* QUADSPI communication configuration register */
+#define QSPI_CCR_DDRM		BIT(31)
+#define QSPI_CCR_DHHC		BIT(30)
+#define QSPI_CCR_SIOO		BIT(28)
+#define QSPI_CCR_FMODE_SHIFT	26U
+#define QSPI_CCR_DMODE_SHIFT	24U
+#define QSPI_CCR_DCYC_SHIFT	18U
+#define QSPI_CCR_ABSIZE_SHIFT	16U
+#define QSPI_CCR_ABMODE_SHIFT	14U
+#define QSPI_CCR_ADSIZE_SHIFT	12U
+#define QSPI_CCR_ADMODE_SHIFT	10U
+#define QSPI_CCR_IMODE_SHIFT	8U
+#define QSPI_CCR_IND_WRITE	0U
+#define QSPI_CCR_IND_READ	1U
+#define QSPI_CCR_MEM_MAP	3U
+
+#define QSPI_MAX_CHIP		2U
+
+#define QSPI_FIFO_TIMEOUT_US	30U
+#define QSPI_CMD_TIMEOUT_US	1000U
+#define QSPI_BUSY_TIMEOUT_US	100U
+#define QSPI_ABT_TIMEOUT_US	100U
+
+#define DT_QSPI_COMPAT		"st,stm32f469-qspi"
+
+#define FREQ_100MHZ		100000000U
+
+struct stm32_qspi_ctrl {
+	uintptr_t reg_base;
+	uintptr_t mm_base;
+	size_t mm_size;
+	unsigned long clock_id;
+	unsigned int reset_id;
+};
+
+static struct stm32_qspi_ctrl stm32_qspi;
+
+static uintptr_t qspi_base(void)
+{
+	return stm32_qspi.reg_base;
+}
+
+static int stm32_qspi_wait_for_not_busy(void)
+{
+	uint64_t timeout = timeout_init_us(QSPI_BUSY_TIMEOUT_US);
+
+	while ((mmio_read_32(qspi_base() + QSPI_SR) & QSPI_SR_BUSY) != 0U) {
+		if (timeout_elapsed(timeout)) {
+			ERROR("%s: busy timeout\n", __func__);
+			return -ETIMEDOUT;
+		}
+	}
+
+	return 0;
+}
+
+static int stm32_qspi_wait_cmd(const struct spi_mem_op *op)
+{
+	int ret = 0;
+	uint64_t timeout;
+
+	if (op->data.nbytes == 0U) {
+		return stm32_qspi_wait_for_not_busy();
+	}
+
+	timeout = timeout_init_us(QSPI_CMD_TIMEOUT_US);
+	while ((mmio_read_32(qspi_base() + QSPI_SR) & QSPI_SR_TCF) == 0U) {
+		if (timeout_elapsed(timeout)) {
+			ret = -ETIMEDOUT;
+			break;
+		}
+	}
+
+	if (ret == 0) {
+		if ((mmio_read_32(qspi_base() + QSPI_SR) & QSPI_SR_TEF) != 0U) {
+			ERROR("%s: transfer error\n", __func__);
+			ret = -EIO;
+		}
+	} else {
+		ERROR("%s: cmd timeout\n", __func__);
+	}
+
+	/* Clear flags */
+	mmio_write_32(qspi_base() + QSPI_FCR, QSPI_FCR_CTCF | QSPI_FCR_CTEF);
+
+	return ret;
+}
+
+static void stm32_qspi_read_fifo(uint8_t *val, uintptr_t addr)
+{
+	*val = mmio_read_8(addr);
+}
+
+static void stm32_qspi_write_fifo(uint8_t *val, uintptr_t addr)
+{
+	mmio_write_8(addr, *val);
+}
+
+static int stm32_qspi_poll(const struct spi_mem_op *op)
+{
+	void (*fifo)(uint8_t *val, uintptr_t addr);
+	uint32_t len = op->data.nbytes;
+	uint8_t *buf;
+	uint64_t timeout;
+
+	if (op->data.dir == SPI_MEM_DATA_IN) {
+		fifo = stm32_qspi_read_fifo;
+	} else {
+		fifo = stm32_qspi_write_fifo;
+	}
+
+	buf = (uint8_t *)op->data.buf;
+
+	for (len = op->data.nbytes; len != 0U; len--) {
+		timeout = timeout_init_us(QSPI_FIFO_TIMEOUT_US);
+		while ((mmio_read_32(qspi_base() + QSPI_SR) &
+			QSPI_SR_FTF) == 0U) {
+			if (timeout_elapsed(timeout)) {
+				ERROR("%s: fifo timeout\n", __func__);
+				return -ETIMEDOUT;
+			}
+		}
+
+		fifo(buf++, qspi_base() + QSPI_DR);
+	}
+
+	return 0;
+}
+
+static int stm32_qspi_mm(const struct spi_mem_op *op)
+{
+	memcpy(op->data.buf,
+	       (void *)(stm32_qspi.mm_base + (size_t)op->addr.val),
+	       op->data.nbytes);
+
+	return 0;
+}
+
+static int stm32_qspi_tx(const struct spi_mem_op *op, uint8_t mode)
+{
+	if (op->data.nbytes == 0U) {
+		return 0;
+	}
+
+	if (mode == QSPI_CCR_MEM_MAP) {
+		return stm32_qspi_mm(op);
+	}
+
+	return stm32_qspi_poll(op);
+}
+
+static unsigned int stm32_qspi_get_mode(uint8_t buswidth)
+{
+	if (buswidth == 4U) {
+		return 3U;
+	}
+
+	return buswidth;
+}
+
+static int stm32_qspi_exec_op(const struct spi_mem_op *op)
+{
+	uint64_t timeout;
+	uint32_t ccr;
+	size_t addr_max;
+	uint8_t mode = QSPI_CCR_IND_WRITE;
+	int ret;
+
+	VERBOSE("%s: cmd:%x mode:%d.%d.%d.%d addr:%llx len:%x\n",
+		__func__, op->cmd.opcode, op->cmd.buswidth, op->addr.buswidth,
+		op->dummy.buswidth, op->data.buswidth,
+		op->addr.val, op->data.nbytes);
+
+	ret = stm32_qspi_wait_for_not_busy();
+	if (ret != 0) {
+		return ret;
+	}
+
+	addr_max = op->addr.val + op->data.nbytes + 1U;
+
+	if ((op->data.dir == SPI_MEM_DATA_IN) && (op->data.nbytes != 0U)) {
+		if ((addr_max < stm32_qspi.mm_size) &&
+		    (op->addr.buswidth != 0U)) {
+			mode = QSPI_CCR_MEM_MAP;
+		} else {
+			mode = QSPI_CCR_IND_READ;
+		}
+	}
+
+	if (op->data.nbytes != 0U) {
+		mmio_write_32(qspi_base() + QSPI_DLR, op->data.nbytes - 1U);
+	}
+
+	ccr = mode << QSPI_CCR_FMODE_SHIFT;
+	ccr |= op->cmd.opcode;
+	ccr |= stm32_qspi_get_mode(op->cmd.buswidth) << QSPI_CCR_IMODE_SHIFT;
+
+	if (op->addr.nbytes != 0U) {
+		ccr |= (op->addr.nbytes - 1U) << QSPI_CCR_ADSIZE_SHIFT;
+		ccr |= stm32_qspi_get_mode(op->addr.buswidth) <<
+			QSPI_CCR_ADMODE_SHIFT;
+	}
+
+	if ((op->dummy.buswidth != 0U) && (op->dummy.nbytes != 0U)) {
+		ccr |= (op->dummy.nbytes * 8U / op->dummy.buswidth) <<
+			QSPI_CCR_DCYC_SHIFT;
+	}
+
+	if (op->data.nbytes != 0U) {
+		ccr |= stm32_qspi_get_mode(op->data.buswidth) <<
+			QSPI_CCR_DMODE_SHIFT;
+	}
+
+	mmio_write_32(qspi_base() + QSPI_CCR, ccr);
+
+	if ((op->addr.nbytes != 0U) && (mode != QSPI_CCR_MEM_MAP)) {
+		mmio_write_32(qspi_base() + QSPI_AR, op->addr.val);
+	}
+
+	ret = stm32_qspi_tx(op, mode);
+
+	/*
+	 * Abort in:
+	 * - Error case.
+	 * - Memory mapped read: prefetching must be stopped if we read the last
+	 *   byte of device (device size - fifo size). If device size is not
+	 *   known then prefetching is always stopped.
+	 */
+	if ((ret != 0) || (mode == QSPI_CCR_MEM_MAP)) {
+		goto abort;
+	}
+
+	/* Wait end of TX in indirect mode */
+	ret = stm32_qspi_wait_cmd(op);
+	if (ret != 0) {
+		goto abort;
+	}
+
+	return 0;
+
+abort:
+	mmio_setbits_32(qspi_base() + QSPI_CR, QSPI_CR_ABORT);
+
+	/* Wait clear of abort bit by hardware */
+	timeout = timeout_init_us(QSPI_ABT_TIMEOUT_US);
+	while ((mmio_read_32(qspi_base() + QSPI_CR) & QSPI_CR_ABORT) != 0U) {
+		if (timeout_elapsed(timeout)) {
+			ret = -ETIMEDOUT;
+			break;
+		}
+	}
+
+	mmio_write_32(qspi_base() + QSPI_FCR, QSPI_FCR_CTCF);
+
+	if (ret != 0) {
+		ERROR("%s: exec op error\n", __func__);
+	}
+
+	return ret;
+}
+
+static int stm32_qspi_claim_bus(unsigned int cs)
+{
+	uint32_t cr;
+
+	if (cs >= QSPI_MAX_CHIP) {
+		return -ENODEV;
+	}
+
+	/* Set chip select and enable the controller */
+	cr = QSPI_CR_EN;
+	if (cs == 1U) {
+		cr |= QSPI_CR_FSEL;
+	}
+
+	mmio_clrsetbits_32(qspi_base() + QSPI_CR, QSPI_CR_FSEL, cr);
+
+	return 0;
+}
+
+static void stm32_qspi_release_bus(void)
+{
+	mmio_clrbits_32(qspi_base() + QSPI_CR, QSPI_CR_EN);
+}
+
+static int stm32_qspi_set_speed(unsigned int hz)
+{
+	unsigned long qspi_clk = stm32mp_clk_get_rate(stm32_qspi.clock_id);
+	uint32_t prescaler = UINT8_MAX;
+	uint32_t csht;
+	int ret;
+
+	if (qspi_clk == 0U) {
+		return -EINVAL;
+	}
+
+	if (hz > 0U) {
+		prescaler = div_round_up(qspi_clk, hz) - 1U;
+		if (prescaler > UINT8_MAX) {
+			prescaler = UINT8_MAX;
+		}
+	}
+
+	csht = div_round_up((5U * qspi_clk) / (prescaler + 1U), FREQ_100MHZ);
+	csht = ((csht - 1U) << QSPI_DCR_CSHT_SHIFT) & QSPI_DCR_CSHT_MASK;
+
+	ret = stm32_qspi_wait_for_not_busy();
+	if (ret != 0) {
+		return ret;
+	}
+
+	mmio_clrsetbits_32(qspi_base() + QSPI_CR, QSPI_CR_PRESCALER_MASK,
+			   prescaler << QSPI_CR_PRESCALER_SHIFT);
+
+	mmio_clrsetbits_32(qspi_base() + QSPI_DCR, QSPI_DCR_CSHT_MASK, csht);
+
+	VERBOSE("%s: speed=%lu\n", __func__, qspi_clk / (prescaler + 1U));
+
+	return 0;
+}
+
+static int stm32_qspi_set_mode(unsigned int mode)
+{
+	int ret;
+
+	ret = stm32_qspi_wait_for_not_busy();
+	if (ret != 0) {
+		return ret;
+	}
+
+	if ((mode & SPI_CS_HIGH) != 0U) {
+		return -ENODEV;
+	}
+
+	if (((mode & SPI_CPHA) != 0U) && ((mode & SPI_CPOL) != 0U)) {
+		mmio_setbits_32(qspi_base() + QSPI_DCR, QSPI_DCR_CKMODE);
+	} else if (((mode & SPI_CPHA) == 0U) && ((mode & SPI_CPOL) == 0U)) {
+		mmio_clrbits_32(qspi_base() + QSPI_DCR, QSPI_DCR_CKMODE);
+	} else {
+		return -ENODEV;
+	}
+
+	VERBOSE("%s: mode=0x%x\n", __func__, mode);
+
+	if ((mode & SPI_RX_QUAD) != 0U) {
+		VERBOSE("rx: quad\n");
+	} else if ((mode & SPI_RX_DUAL) != 0U) {
+		VERBOSE("rx: dual\n");
+	} else {
+		VERBOSE("rx: single\n");
+	}
+
+	if ((mode & SPI_TX_QUAD) != 0U) {
+		VERBOSE("tx: quad\n");
+	} else if ((mode & SPI_TX_DUAL) != 0U) {
+		VERBOSE("tx: dual\n");
+	} else {
+		VERBOSE("tx: single\n");
+	}
+
+	return 0;
+}
+
+static const struct spi_bus_ops stm32_qspi_bus_ops = {
+	.claim_bus = stm32_qspi_claim_bus,
+	.release_bus = stm32_qspi_release_bus,
+	.set_speed = stm32_qspi_set_speed,
+	.set_mode = stm32_qspi_set_mode,
+	.exec_op = stm32_qspi_exec_op,
+};
+
+int stm32_qspi_init(void)
+{
+	size_t size;
+	int qspi_node;
+	struct dt_node_info info;
+	void *fdt = NULL;
+	int ret;
+
+	if (fdt_get_address(&fdt) == 0) {
+		return -FDT_ERR_NOTFOUND;
+	}
+
+	qspi_node = dt_get_node(&info, -1, DT_QSPI_COMPAT);
+	if (qspi_node < 0) {
+		ERROR("No QSPI ctrl found\n");
+		return -FDT_ERR_NOTFOUND;
+	}
+
+	if (info.status == DT_DISABLED) {
+		return -FDT_ERR_NOTFOUND;
+	}
+
+	ret = fdt_get_reg_props_by_name(qspi_node, "qspi",
+					&stm32_qspi.reg_base, &size);
+	if (ret != 0) {
+		return ret;
+	}
+
+	ret = fdt_get_reg_props_by_name(qspi_node, "qspi_mm",
+					&stm32_qspi.mm_base,
+					&stm32_qspi.mm_size);
+	if (ret != 0) {
+		return ret;
+	}
+
+	if (dt_set_pinctrl_config(qspi_node) != 0) {
+		return -FDT_ERR_BADVALUE;
+	}
+
+	if ((info.clock < 0) || (info.reset < 0)) {
+		return -FDT_ERR_BADVALUE;
+	}
+
+	stm32_qspi.clock_id = (unsigned long)info.clock;
+	stm32_qspi.reset_id = (unsigned int)info.reset;
+
+	stm32mp_clk_enable(stm32_qspi.clock_id);
+
+	stm32mp_reset_assert(stm32_qspi.reset_id);
+	stm32mp_reset_deassert(stm32_qspi.reset_id);
+
+	mmio_write_32(qspi_base() + QSPI_CR, QSPI_CR_SSHIFT);
+	mmio_write_32(qspi_base() + QSPI_DCR, QSPI_DCR_FSIZE_MASK);
+
+	return spi_mem_init_slave(fdt, qspi_node, &stm32_qspi_bus_ops);
+};
diff --git a/drivers/st/uart/aarch32/stm32_console.S b/drivers/st/uart/aarch32/stm32_console.S
index 39e449b29..ca3c1f618 100644
--- a/drivers/st/uart/aarch32/stm32_console.S
+++ b/drivers/st/uart/aarch32/stm32_console.S
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -138,34 +138,18 @@ func console_stm32_core_putc
 	/* Check the input parameter */
 	cmp	r1, #0
 	beq	putc_error
-	/* Prepend '\r' to '\n' */
-	cmp	r0, #0xA
-	bne	2f
-1:
-	/* Check Transmit Data Register Empty */
-txe_loop_1:
-	ldr	r2, [r1, #USART_ISR]
-	tst	r2, #USART_ISR_TXE
-	beq	txe_loop_1
-	mov	r2, #0xD
-	str	r2, [r1, #USART_TDR]
-	/* Check transmit complete flag */
-tc_loop_1:
-	ldr	r2, [r1, #USART_ISR]
-	tst	r2, #USART_ISR_TC
-	beq	tc_loop_1
-2:
+
 	/* Check Transmit Data Register Empty */
-txe_loop_2:
+txe_loop:
 	ldr	r2, [r1, #USART_ISR]
 	tst	r2, #USART_ISR_TXE
-	beq	txe_loop_2
+	beq	txe_loop
 	str	r0, [r1, #USART_TDR]
 	/* Check transmit complete flag */
-tc_loop_2:
+tc_loop:
 	ldr	r2, [r1, #USART_ISR]
 	tst	r2, #USART_ISR_TC
-	beq	tc_loop_2
+	beq	tc_loop
 	bx	lr
 putc_error:
 	mov	r0, #-1
diff --git a/drivers/staging/renesas/rcar/ddr/boot_init_dram.h b/drivers/staging/renesas/rcar/ddr/boot_init_dram.h
deleted file mode 100644
index 4b0a9ebe4..000000000
--- a/drivers/staging/renesas/rcar/ddr/boot_init_dram.h
+++ /dev/null
@@ -1,18 +0,0 @@
-/*
- * Copyright (c) 2018, Renesas Electronics Corporation. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#ifndef BOOT_INIT_DRAM_H
-#define BOOT_INIT_DRAM_H
-
-extern int32_t rcar_dram_init(void);
-
-#define INITDRAM_OK (0)
-#define INITDRAM_NG (0xffffffff)
-#define INITDRAM_ERR_I (0xffffffff)
-#define INITDRAM_ERR_O (0xfffffffe)
-#define INITDRAM_ERR_T (0xfffffff0)
-
-#endif /* BOOT_INIT_DRAM_H */
diff --git a/drivers/staging/renesas/rcar/ddr/ddr.mk b/drivers/staging/renesas/rcar/ddr/ddr.mk
deleted file mode 100644
index ed7adc339..000000000
--- a/drivers/staging/renesas/rcar/ddr/ddr.mk
+++ /dev/null
@@ -1,17 +0,0 @@
-#
-# Copyright (c) 2015-2018, Renesas Electronics Corporation. All rights reserved.
-#
-# SPDX-License-Identifier: BSD-3-Clause
-#
-
-ifeq (${RCAR_LSI},${RCAR_E3})
-    include drivers/staging/renesas/rcar/ddr/ddr_a/ddr_a.mk
-    BL2_SOURCES += drivers/staging/renesas/rcar/ddr/dram_sub_func.c
-else ifeq (${RCAR_LSI},${RCAR_D3})
-    include drivers/staging/renesas/rcar/ddr/ddr_a/ddr_a.mk
-else ifeq (${RCAR_LSI},${RCAR_V3M})
-    include drivers/staging/renesas/rcar/ddr/ddr_a/ddr_a.mk
-else
-    include drivers/staging/renesas/rcar/ddr/ddr_b/ddr_b.mk
-    BL2_SOURCES += drivers/staging/renesas/rcar/ddr/dram_sub_func.c
-endif
diff --git a/drivers/staging/renesas/rcar/ddr/ddr_a/boot_init_dram_regdef.h b/drivers/staging/renesas/rcar/ddr/ddr_a/boot_init_dram_regdef.h
deleted file mode 100644
index 397bde04e..000000000
--- a/drivers/staging/renesas/rcar/ddr/ddr_a/boot_init_dram_regdef.h
+++ /dev/null
@@ -1,291 +0,0 @@
-/*
- * Copyright (c) 2015-2019, Renesas Electronics Corporation
- * All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#ifndef BOOT_INIT_DRAM_REGDEF_H_
-#define BOOT_INIT_DRAM_REGDEF_H_
-
-/* DBSC registers */
-#define DBSC_DBSYSCONF0		0xE6790000U
-#define DBSC_DBSYSCONF1		0xE6790004U
-#define DBSC_DBPHYCONF0		0xE6790010U
-#define DBSC_DBKIND		0xE6790020U
-#define DBSC_DBMEMCONF00	0xE6790030U
-#define DBSC_DBMEMCONF01	0xE6790034U
-#define DBSC_DBMEMCONF02	0xE6790038U
-#define DBSC_DBMEMCONF03	0xE679003CU
-#define DBSC_DBMEMCONF10	0xE6790040U
-#define DBSC_DBMEMCONF11	0xE6790044U
-#define DBSC_DBMEMCONF12	0xE6790048U
-#define DBSC_DBMEMCONF13	0xE679004CU
-#define DBSC_DBMEMCONF20	0xE6790050U
-#define DBSC_DBMEMCONF21	0xE6790054U
-#define DBSC_DBMEMCONF22	0xE6790058U
-#define DBSC_DBMEMCONF23	0xE679005CU
-#define DBSC_DBMEMCONF30	0xE6790060U
-#define DBSC_DBMEMCONF31	0xE6790064U
-#define DBSC_DBMEMCONF32	0xE6790068U
-#define DBSC_DBMEMCONF33	0xE679006CU
-#define DBSC_DBSYSCNT0		0xE6790100U
-#define DBSC_DBSVCR1		0xE6790104U
-#define DBSC_DBSTATE0		0xE6790108U
-#define DBSC_DBSTATE1		0xE679010CU
-#define DBSC_DBINTEN		0xE6790180U
-#define DBSC_DBINTSTAT0		0xE6790184U
-#define DBSC_DBACEN		0xE6790200U
-#define DBSC_DBRFEN		0xE6790204U
-#define DBSC_DBCMD		0xE6790208U
-#define DBSC_DBWAIT		0xE6790210U
-#define DBSC_DBSYSCTRL0		0xE6790280U
-#define DBSC_DBTR0		0xE6790300U
-#define DBSC_DBTR1		0xE6790304U
-#define DBSC_DBTR2		0xE6790308U
-#define DBSC_DBTR3		0xE679030CU
-#define DBSC_DBTR4		0xE6790310U
-#define DBSC_DBTR5		0xE6790314U
-#define DBSC_DBTR6		0xE6790318U
-#define DBSC_DBTR7		0xE679031CU
-#define DBSC_DBTR8		0xE6790320U
-#define DBSC_DBTR9		0xE6790324U
-#define DBSC_DBTR10		0xE6790328U
-#define DBSC_DBTR11		0xE679032CU
-#define DBSC_DBTR12		0xE6790330U
-#define DBSC_DBTR13		0xE6790334U
-#define DBSC_DBTR14		0xE6790338U
-#define DBSC_DBTR15		0xE679033CU
-#define DBSC_DBTR16		0xE6790340U
-#define DBSC_DBTR17		0xE6790344U
-#define DBSC_DBTR18		0xE6790348U
-#define DBSC_DBTR19		0xE679034CU
-#define DBSC_DBTR20		0xE6790350U
-#define DBSC_DBTR21		0xE6790354U
-#define DBSC_DBTR22		0xE6790358U
-#define DBSC_DBTR23		0xE679035CU
-#define DBSC_DBTR24		0xE6790360U
-#define DBSC_DBTR25		0xE6790364U
-#define DBSC_DBBL		0xE6790400U
-#define DBSC_DBRFCNF1		0xE6790414U
-#define DBSC_DBRFCNF2		0xE6790418U
-#define DBSC_DBTSPCNF		0xE6790420U
-#define DBSC_DBCALCNF		0xE6790424U
-#define DBSC_DBRNK2		0xE6790438U
-#define DBSC_DBRNK3		0xE679043CU
-#define DBSC_DBRNK4		0xE6790440U
-#define DBSC_DBRNK5		0xE6790444U
-#define DBSC_DBPDNCNF		0xE6790450U
-#define DBSC_DBODT0		0xE6790460U
-#define DBSC_DBODT1		0xE6790464U
-#define DBSC_DBODT2		0xE6790468U
-#define DBSC_DBODT3		0xE679046CU
-#define DBSC_DBODT4		0xE6790470U
-#define DBSC_DBODT5		0xE6790474U
-#define DBSC_DBODT6		0xE6790478U
-#define DBSC_DBODT7		0xE679047CU
-#define DBSC_DBADJ0		0xE6790500U
-#define DBSC_DBDBICNT		0xE6790518U
-#define DBSC_DBDFIPMSTRCNF	0xE6790520U
-#define DBSC_DBDFIPMSTRSTAT	0xE6790524U
-#define DBSC_DBDFILPCNF		0xE6790528U
-#define DBSC_DBDFICUPDCNF	0xE679052CU
-#define DBSC_DBDFISTAT0		0xE6790600U
-#define DBSC_DBDFICNT0		0xE6790604U
-#define DBSC_DBPDCNT00		0xE6790610U
-#define DBSC_DBPDCNT01		0xE6790614U
-#define DBSC_DBPDCNT02		0xE6790618U
-#define DBSC_DBPDCNT03		0xE679061CU
-#define DBSC_DBPDLK0		0xE6790620U
-#define DBSC_DBPDRGA0		0xE6790624U
-#define DBSC_DBPDRGD0		0xE6790628U
-#define DBSC_DBPDSTAT00		0xE6790630U
-#define DBSC_DBDFISTAT1		0xE6790640U
-#define DBSC_DBDFICNT1		0xE6790644U
-#define DBSC_DBPDCNT10		0xE6790650U
-#define DBSC_DBPDCNT11		0xE6790654U
-#define DBSC_DBPDCNT12		0xE6790658U
-#define DBSC_DBPDCNT13		0xE679065CU
-#define DBSC_DBPDLK1		0xE6790660U
-#define DBSC_DBPDRGA1		0xE6790664U
-#define DBSC_DBPDRGD1		0xE6790668U
-#define DBSC_DBPDSTAT10		0xE6790670U
-#define DBSC_DBDFISTAT2		0xE6790680U
-#define DBSC_DBDFICNT2		0xE6790684U
-#define DBSC_DBPDCNT20		0xE6790690U
-#define DBSC_DBPDCNT21		0xE6790694U
-#define DBSC_DBPDCNT22		0xE6790698U
-#define DBSC_DBPDCNT23		0xE679069CU
-#define DBSC_DBPDLK2		0xE67906A0U
-#define DBSC_DBPDRGA2		0xE67906A4U
-#define DBSC_DBPDRGD2		0xE67906A8U
-#define DBSC_DBPDSTAT20		0xE67906B0U
-#define DBSC_DBDFISTAT3		0xE67906C0U
-#define DBSC_DBDFICNT3		0xE67906C4U
-#define DBSC_DBPDCNT30		0xE67906D0U
-#define DBSC_DBPDCNT31		0xE67906D4U
-#define DBSC_DBPDCNT32		0xE67906D8U
-#define DBSC_DBPDCNT33		0xE67906DCU
-#define DBSC_DBPDLK3		0xE67906E0U
-#define DBSC_DBPDRGA3		0xE67906E4U
-#define DBSC_DBPDRGD3		0xE67906E8U
-#define DBSC_DBPDSTAT30		0xE67906F0U
-#define DBSC_DBBUS0CNF0		0xE6790800U
-#define DBSC_DBBUS0CNF1		0xE6790804U
-#define DBSC_DBCAM0CNF1		0xE6790904U
-#define DBSC_DBCAM0CNF2		0xE6790908U
-#define DBSC_DBCAM0CNF3		0xE679090CU
-#define DBSC_DBCAM0CTRL0	0xE6790940U
-#define DBSC_DBCAM0STAT0	0xE6790980U
-#define DBSC_DBCAM1STAT0	0xE6790990U
-#define DBSC_DBBCAMSWAP		0xE67909F0U
-#define DBSC_DBBCAMDIS		0xE67909FCU
-#define DBSC_DBSCHCNT0		0xE6791000U
-#define DBSC_DBSCHCNT1		0xE6791004U
-#define DBSC_DBSCHSZ0		0xE6791010U
-#define DBSC_DBSCHRW0		0xE6791020U
-#define DBSC_DBSCHRW1		0xE6791024U
-#define DBSC_DBSCHQOS00		0xE6791030U
-#define DBSC_DBSCHQOS01		0xE6791034U
-#define DBSC_DBSCHQOS02		0xE6791038U
-#define DBSC_DBSCHQOS03		0xE679103CU
-#define DBSC_DBSCHQOS10		0xE6791040U
-#define DBSC_DBSCHQOS11		0xE6791044U
-#define DBSC_DBSCHQOS12		0xE6791048U
-#define DBSC_DBSCHQOS13		0xE679104CU
-#define DBSC_DBSCHQOS20		0xE6791050U
-#define DBSC_DBSCHQOS21		0xE6791054U
-#define DBSC_DBSCHQOS22		0xE6791058U
-#define DBSC_DBSCHQOS23		0xE679105CU
-#define DBSC_DBSCHQOS30		0xE6791060U
-#define DBSC_DBSCHQOS31		0xE6791064U
-#define DBSC_DBSCHQOS32		0xE6791068U
-#define DBSC_DBSCHQOS33		0xE679106CU
-#define DBSC_DBSCHQOS40		0xE6791070U
-#define DBSC_DBSCHQOS41		0xE6791074U
-#define DBSC_DBSCHQOS42		0xE6791078U
-#define DBSC_DBSCHQOS43		0xE679107CU
-#define DBSC_DBSCHQOS50		0xE6791080U
-#define DBSC_DBSCHQOS51		0xE6791084U
-#define DBSC_DBSCHQOS52		0xE6791088U
-#define DBSC_DBSCHQOS53		0xE679108CU
-#define DBSC_DBSCHQOS60		0xE6791090U
-#define DBSC_DBSCHQOS61		0xE6791094U
-#define DBSC_DBSCHQOS62		0xE6791098U
-#define DBSC_DBSCHQOS63		0xE679109CU
-#define DBSC_DBSCHQOS70		0xE67910A0U
-#define DBSC_DBSCHQOS71		0xE67910A4U
-#define DBSC_DBSCHQOS72		0xE67910A8U
-#define DBSC_DBSCHQOS73		0xE67910ACU
-#define DBSC_DBSCHQOS80		0xE67910B0U
-#define DBSC_DBSCHQOS81		0xE67910B4U
-#define DBSC_DBSCHQOS82		0xE67910B8U
-#define DBSC_DBSCHQOS83		0xE67910BCU
-#define DBSC_DBSCHQOS90		0xE67910C0U
-#define DBSC_DBSCHQOS91		0xE67910C4U
-#define DBSC_DBSCHQOS92		0xE67910C8U
-#define DBSC_DBSCHQOS93		0xE67910CCU
-#define DBSC_DBSCHQOS100	0xE67910D0U
-#define DBSC_DBSCHQOS101	0xE67910D4U
-#define DBSC_DBSCHQOS102	0xE67910D8U
-#define DBSC_DBSCHQOS103	0xE67910DCU
-#define DBSC_DBSCHQOS110	0xE67910E0U
-#define DBSC_DBSCHQOS111	0xE67910E4U
-#define DBSC_DBSCHQOS112	0xE67910E8U
-#define DBSC_DBSCHQOS113	0xE67910ECU
-#define DBSC_DBSCHQOS120	0xE67910F0U
-#define DBSC_DBSCHQOS121	0xE67910F4U
-#define DBSC_DBSCHQOS122	0xE67910F8U
-#define DBSC_DBSCHQOS123	0xE67910FCU
-#define DBSC_DBSCHQOS130	0xE6791100U
-#define DBSC_DBSCHQOS131	0xE6791104U
-#define DBSC_DBSCHQOS132	0xE6791108U
-#define DBSC_DBSCHQOS133	0xE679110CU
-#define DBSC_DBSCHQOS140	0xE6791110U
-#define DBSC_DBSCHQOS141	0xE6791114U
-#define DBSC_DBSCHQOS142	0xE6791118U
-#define DBSC_DBSCHQOS143	0xE679111CU
-#define DBSC_DBSCHQOS150	0xE6791120U
-#define DBSC_DBSCHQOS151	0xE6791124U
-#define DBSC_DBSCHQOS152	0xE6791128U
-#define DBSC_DBSCHQOS153	0xE679112CU
-#define DBSC_SCFCTST0		0xE6791700U
-#define DBSC_SCFCTST1		0xE6791708U
-#define DBSC_SCFCTST2		0xE679170CU
-#define DBSC_DBMRRDR0		0xE6791800U
-#define DBSC_DBMRRDR1		0xE6791804U
-#define DBSC_DBMRRDR2		0xE6791808U
-#define DBSC_DBMRRDR3		0xE679180CU
-#define DBSC_DBMRRDR4		0xE6791810U
-#define DBSC_DBMRRDR5		0xE6791814U
-#define DBSC_DBMRRDR6		0xE6791818U
-#define DBSC_DBMRRDR7		0xE679181CU
-#define DBSC_DBDTMP0		0xE6791820U
-#define DBSC_DBDTMP1		0xE6791824U
-#define DBSC_DBDTMP2		0xE6791828U
-#define DBSC_DBDTMP3		0xE679182CU
-#define DBSC_DBDTMP4		0xE6791830U
-#define DBSC_DBDTMP5		0xE6791834U
-#define DBSC_DBDTMP6		0xE6791838U
-#define DBSC_DBDTMP7		0xE679183CU
-#define DBSC_DBDQSOSC00		0xE6791840U
-#define DBSC_DBDQSOSC01		0xE6791844U
-#define DBSC_DBDQSOSC10		0xE6791848U
-#define DBSC_DBDQSOSC11		0xE679184CU
-#define DBSC_DBDQSOSC20		0xE6791850U
-#define DBSC_DBDQSOSC21		0xE6791854U
-#define DBSC_DBDQSOSC30		0xE6791858U
-#define DBSC_DBDQSOSC31		0xE679185CU
-#define DBSC_DBDQSOSC40		0xE6791860U
-#define DBSC_DBDQSOSC41		0xE6791864U
-#define DBSC_DBDQSOSC50		0xE6791868U
-#define DBSC_DBDQSOSC51		0xE679186CU
-#define DBSC_DBDQSOSC60		0xE6791870U
-#define DBSC_DBDQSOSC61		0xE6791874U
-#define DBSC_DBDQSOSC70		0xE6791878U
-#define DBSC_DBDQSOSC71		0xE679187CU
-#define DBSC_DBOSCTHH00		0xE6791880U
-#define DBSC_DBOSCTHH01		0xE6791884U
-#define DBSC_DBOSCTHH10		0xE6791888U
-#define DBSC_DBOSCTHH11		0xE679188CU
-#define DBSC_DBOSCTHH20		0xE6791890U
-#define DBSC_DBOSCTHH21		0xE6791894U
-#define DBSC_DBOSCTHH30		0xE6791898U
-#define DBSC_DBOSCTHH31		0xE679189CU
-#define DBSC_DBOSCTHH40		0xE67918A0U
-#define DBSC_DBOSCTHH41		0xE67918A4U
-#define DBSC_DBOSCTHH50		0xE67918A8U
-#define DBSC_DBOSCTHH51		0xE67918ACU
-#define DBSC_DBOSCTHH60		0xE67918B0U
-#define DBSC_DBOSCTHH61		0xE67918B4U
-#define DBSC_DBOSCTHH70		0xE67918B8U
-#define DBSC_DBOSCTHH71		0xE67918BCU
-#define DBSC_DBOSCTHL00		0xE67918C0U
-#define DBSC_DBOSCTHL01		0xE67918C4U
-#define DBSC_DBOSCTHL10		0xE67918C8U
-#define DBSC_DBOSCTHL11		0xE67918CCU
-#define DBSC_DBOSCTHL20		0xE67918D0U
-#define DBSC_DBOSCTHL21		0xE67918D4U
-#define DBSC_DBOSCTHL30		0xE67918D8U
-#define DBSC_DBOSCTHL31		0xE67918DCU
-#define DBSC_DBOSCTHL40		0xE67918E0U
-#define DBSC_DBOSCTHL41		0xE67918E4U
-#define DBSC_DBOSCTHL50		0xE67918E8U
-#define DBSC_DBOSCTHL51		0xE67918ECU
-#define DBSC_DBOSCTHL60		0xE67918F0U
-#define DBSC_DBOSCTHL61		0xE67918F4U
-#define DBSC_DBOSCTHL70		0xE67918F8U
-#define DBSC_DBOSCTHL71		0xE67918FCU
-#define DBSC_DBMEMSWAPCONF0	0xE6792000U
-
-/* CPG registers */
-#define CPG_SRCR4		0xE61500BCU
-#define CPG_PLLECR		0xE61500D0U
-#define CPG_CPGWPR		0xE6150900U
-#define CPG_CPGWPCR		0xE6150904U
-#define CPG_SRSTCLR4		0xE6150950U
-
-/* MODE Monitor registers */
-#define RST_MODEMR		0xE6160060U
-
-#endif /* BOOT_INIT_DRAM_REGDEF_H_*/
diff --git a/drivers/staging/renesas/rcar/ddr/ddr_a/ddr_a.mk b/drivers/staging/renesas/rcar/ddr/ddr_a/ddr_a.mk
deleted file mode 100644
index aee27a59a..000000000
--- a/drivers/staging/renesas/rcar/ddr/ddr_a/ddr_a.mk
+++ /dev/null
@@ -1,13 +0,0 @@
-#
-# Copyright (c) 2015-2018, Renesas Electronics Corporation. All rights reserved.
-#
-# SPDX-License-Identifier: BSD-3-Clause
-#
-
-ifeq (${RCAR_LSI},${RCAR_E3})
-BL2_SOURCES += drivers/staging/renesas/rcar/ddr/ddr_a/ddr_init_e3.c
-else ifeq (${RCAR_LSI},${RCAR_D3})
-BL2_SOURCES += drivers/staging/renesas/rcar/ddr/ddr_a/ddr_init_d3.c
-else
-BL2_SOURCES += drivers/staging/renesas/rcar/ddr/ddr_a/ddr_init_v3m.c
-endif
diff --git a/drivers/staging/renesas/rcar/ddr/ddr_a/ddr_init_d3.c b/drivers/staging/renesas/rcar/ddr/ddr_a/ddr_init_d3.c
deleted file mode 100644
index d03b1b965..000000000
--- a/drivers/staging/renesas/rcar/ddr/ddr_a/ddr_init_d3.c
+++ /dev/null
@@ -1,699 +0,0 @@
-/*
- * Copyright (c) 2015-2019, Renesas Electronics Corporation.
- * All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#include <stdint.h>
-#include <lib/mmio.h>
-#include <common/debug.h>
-
-#include "boot_init_dram_regdef.h"
-
-#define RCAR_DDR_VERSION	"rev.0.01"
-
-#if RCAR_LSI != RCAR_D3
-#error "Don't have DDR initialize routine."
-#endif
-
-static void init_ddr_d3_1866(void)
-{
-	uint32_t i, r2, r3, r5, r6, r7, r12;
-
-	mmio_write_32(DBSC_DBSYSCNT0, 0x00001234);
-	mmio_write_32(DBSC_DBKIND, 0x00000007);
-	mmio_write_32(DBSC_DBMEMCONF00, 0x0f030a01);
-	mmio_write_32(DBSC_DBPHYCONF0, 0x00000001);
-	mmio_write_32(DBSC_DBTR0, 0x0000000D);
-	mmio_write_32(DBSC_DBTR1, 0x00000009);
-	mmio_write_32(DBSC_DBTR2, 0x00000000);
-	mmio_write_32(DBSC_DBTR3, 0x0000000D);
-	mmio_write_32(DBSC_DBTR4, 0x000D000D);
-	mmio_write_32(DBSC_DBTR5, 0x0000002D);
-	mmio_write_32(DBSC_DBTR6, 0x00000020);
-	mmio_write_32(DBSC_DBTR7, 0x00060006);
-	mmio_write_32(DBSC_DBTR8, 0x00000021);
-	mmio_write_32(DBSC_DBTR9, 0x00000007);
-	mmio_write_32(DBSC_DBTR10, 0x0000000E);
-	mmio_write_32(DBSC_DBTR11, 0x0000000C);
-	mmio_write_32(DBSC_DBTR12, 0x00140014);
-	mmio_write_32(DBSC_DBTR13, 0x000000F2);
-	mmio_write_32(DBSC_DBTR14, 0x00170006);
-	mmio_write_32(DBSC_DBTR15, 0x00060005);
-	mmio_write_32(DBSC_DBTR16, 0x09210507);
-	mmio_write_32(DBSC_DBTR17, 0x040E0000);
-	mmio_write_32(DBSC_DBTR18, 0x00000200);
-	mmio_write_32(DBSC_DBTR19, 0x012B004B);
-	mmio_write_32(DBSC_DBTR20, 0x020000FB);
-	mmio_write_32(DBSC_DBTR21, 0x00040004);
-	mmio_write_32(DBSC_DBBL, 0x00000000);
-	mmio_write_32(DBSC_DBODT0, 0x00000001);
-	mmio_write_32(DBSC_DBADJ0, 0x00000001);
-	mmio_write_32(DBSC_DBSYSCONF1, 0x00000002);
-	mmio_write_32(DBSC_DBDFICNT0, 0x00000010);
-	mmio_write_32(DBSC_DBBCAMDIS, 0x00000001);
-	mmio_write_32(DBSC_DBSCHRW1, 0x00000046);
-	mmio_write_32(DBSC_SCFCTST0, 0x0D020D04);
-	mmio_write_32(DBSC_SCFCTST1, 0x0306040C);
-
-	mmio_write_32(DBSC_DBPDLK0, 0x0000A55A);
-	mmio_write_32(DBSC_DBCMD, 0x01000001);
-	mmio_write_32(DBSC_DBCMD, 0x08000000);
-	mmio_write_32(DBSC_DBPDRGA0, 0x00000001);
-	mmio_write_32(DBSC_DBPDRGD0, 0x80010000);
-	mmio_write_32(DBSC_DBPDRGA0, 0x00000006);
-	while (!(mmio_read_32(DBSC_DBPDRGD0) & BIT(0)))
-		;
-
-	mmio_write_32(DBSC_DBPDRGA0, 0x00000008);
-	mmio_write_32(DBSC_DBPDRGD0, 0x000B8000);
-	mmio_write_32(DBSC_DBPDRGA0, 0x00000090);
-	mmio_write_32(DBSC_DBPDRGD0, 0x04058A04);
-	mmio_write_32(DBSC_DBPDRGA0, 0x00000091);
-	mmio_write_32(DBSC_DBPDRGD0, 0x0007BB6B);
-	mmio_write_32(DBSC_DBPDRGA0, 0x00000095);
-	mmio_write_32(DBSC_DBPDRGD0, 0x0007BBAD);
-	mmio_write_32(DBSC_DBPDRGA0, 0x00000099);
-	mmio_write_32(DBSC_DBPDRGD0, 0x0007BB6B);
-	mmio_write_32(DBSC_DBPDRGA0, 0x00000090);
-	mmio_write_32(DBSC_DBPDRGD0, 0x04058A00);
-	mmio_write_32(DBSC_DBPDRGA0, 0x00000021);
-	mmio_write_32(DBSC_DBPDRGD0, 0x0024641E);
-	mmio_write_32(DBSC_DBPDRGA0, 0x00000001);
-	mmio_write_32(DBSC_DBPDRGD0, 0x00010073);
-	mmio_write_32(DBSC_DBPDRGA0, 0x00000006);
-	while (!(mmio_read_32(DBSC_DBPDRGD0) & BIT(0)))
-		;
-
-	mmio_write_32(DBSC_DBPDRGA0, 0x00000090);
-	mmio_write_32(DBSC_DBPDRGD0, 0x0C058A00);
-	mmio_write_32(DBSC_DBPDRGA0, 0x00000090);
-	mmio_write_32(DBSC_DBPDRGD0, 0x04058A00);
-	mmio_write_32(DBSC_DBPDRGA0, 0x00000006);
-	while (!(mmio_read_32(DBSC_DBPDRGD0) & BIT(0)))
-		;
-
-	mmio_write_32(DBSC_DBPDRGA0, 0x00000003);
-	mmio_write_32(DBSC_DBPDRGD0, 0x0780C700);
-	mmio_write_32(DBSC_DBPDRGA0, 0x00000007);
-	while (!(mmio_read_32(DBSC_DBPDRGD0) & BIT(30)))
-		;
-
-	mmio_write_32(DBSC_DBPDRGA0, 0x00000004);
-	mmio_write_32(DBSC_DBPDRGD0, 0x0A206F89);
-	mmio_write_32(DBSC_DBPDRGA0, 0x00000022);
-	mmio_write_32(DBSC_DBPDRGD0, 0x1000040B);
-	mmio_write_32(DBSC_DBPDRGA0, 0x00000023);
-	mmio_write_32(DBSC_DBPDRGD0, 0x35A00D77);
-	mmio_write_32(DBSC_DBPDRGA0, 0x00000024);
-	mmio_write_32(DBSC_DBPDRGD0, 0x2A8A2C28);
-	mmio_write_32(DBSC_DBPDRGA0, 0x00000025);
-	mmio_write_32(DBSC_DBPDRGD0, 0x30005E00);
-	mmio_write_32(DBSC_DBPDRGA0, 0x00000026);
-	mmio_write_32(DBSC_DBPDRGD0, 0x0014CB49);
-	mmio_write_32(DBSC_DBPDRGA0, 0x00000027);
-	mmio_write_32(DBSC_DBPDRGD0, 0x00000F14);
-	mmio_write_32(DBSC_DBPDRGA0, 0x00000028);
-	mmio_write_32(DBSC_DBPDRGD0, 0x00000046);
-	mmio_write_32(DBSC_DBPDRGA0, 0x00000029);
-	mmio_write_32(DBSC_DBPDRGD0, 0x000000A0);
-	mmio_write_32(DBSC_DBPDRGA0, 0x0000002C);
-	mmio_write_32(DBSC_DBPDRGD0, 0x81003047);
-	mmio_write_32(DBSC_DBPDRGA0, 0x00000020);
-	mmio_write_32(DBSC_DBPDRGD0, 0x00181884);
-	mmio_write_32(DBSC_DBPDRGA0, 0x0000001A);
-	mmio_write_32(DBSC_DBPDRGD0, 0x33C03C10);
-	mmio_write_32(DBSC_DBPDRGA0, 0x00000006);
-	while (!(mmio_read_32(DBSC_DBPDRGD0) & BIT(0)))
-		;
-
-	mmio_write_32(DBSC_DBPDRGA0, 0x000000A7);
-	mmio_write_32(DBSC_DBPDRGD0, 0x0D0D0D0D);
-	mmio_write_32(DBSC_DBPDRGA0, 0x000000A8);
-	mmio_write_32(DBSC_DBPDRGD0, 0x0D0D0D0D);
-	mmio_write_32(DBSC_DBPDRGA0, 0x000000A9);
-	mmio_write_32(DBSC_DBPDRGD0, 0x000D0D0D);
-	mmio_write_32(DBSC_DBPDRGA0, 0x000000C7);
-	mmio_write_32(DBSC_DBPDRGD0, 0x0D0D0D0D);
-	mmio_write_32(DBSC_DBPDRGA0, 0x000000C8);
-	mmio_write_32(DBSC_DBPDRGD0, 0x0D0D0D0D);
-	mmio_write_32(DBSC_DBPDRGA0, 0x000000C9);
-	mmio_write_32(DBSC_DBPDRGD0, 0x000D0D0D);
-
-	mmio_write_32(DBSC_DBPDRGA0, 0x0000000E);
-	r2 = (mmio_read_32(DBSC_DBPDRGD0) & 0x0000FF00) >> 0x9;
-	r3 = (r2 << 16) + (r2 << 8) + r2;
-	r6 = (r2 << 24) + (r2 << 16) + (r2 << 8) + r2;
-	mmio_write_32(DBSC_DBPDRGA0, 0x00000011);
-	mmio_write_32(DBSC_DBPDRGD0, r3);
-	mmio_write_32(DBSC_DBPDRGA0, 0x00000012);
-	mmio_write_32(DBSC_DBPDRGD0, r3);
-	mmio_write_32(DBSC_DBPDRGA0, 0x00000016);
-	mmio_write_32(DBSC_DBPDRGD0, r6);
-	mmio_write_32(DBSC_DBPDRGA0, 0x00000017);
-	mmio_write_32(DBSC_DBPDRGD0, r6);
-	mmio_write_32(DBSC_DBPDRGA0, 0x00000018);
-	mmio_write_32(DBSC_DBPDRGD0, r6);
-	mmio_write_32(DBSC_DBPDRGA0, 0x00000019);
-	mmio_write_32(DBSC_DBPDRGD0, r6);
-
-	mmio_write_32(DBSC_DBPDRGA0, 0x00000001);
-	mmio_write_32(DBSC_DBPDRGD0, 0x00010181);
-	mmio_write_32(DBSC_DBCMD, 0x08000001);
-	mmio_write_32(DBSC_DBPDRGA0, 0x00000006);
-	while (!(mmio_read_32(DBSC_DBPDRGD0) & BIT(0)))
-		;
-
-	mmio_write_32(DBSC_DBPDRGA0, 0x00000001);
-	mmio_write_32(DBSC_DBPDRGD0, 0x00010601);
-	mmio_write_32(DBSC_DBPDRGA0, 0x00000006);
-	while (!(mmio_read_32(DBSC_DBPDRGD0) & BIT(0)))
-		;
-
-	for (i = 0; i < 2; i++) {
-		mmio_write_32(DBSC_DBPDRGA0, 0xB1 + i * 0x20);
-		r5 = (mmio_read_32(DBSC_DBPDRGD0) & 0xFF00) >> 0x8;
-		mmio_write_32(DBSC_DBPDRGA0, 0xB4 + i * 0x20);
-		r6 = mmio_read_32(DBSC_DBPDRGD0) & 0xFF;
-		mmio_write_32(DBSC_DBPDRGA0, 0xB3 + i * 0x20);
-		r7 = mmio_read_32(DBSC_DBPDRGD0) & 0x7;
-
-		if (r6 > 0) {
-			mmio_write_32(DBSC_DBPDRGA0, 0xB2 + i * 0x20);
-			r2 = mmio_read_32(DBSC_DBPDRGD0) & 0xFFFFFFF8;
-
-			mmio_write_32(DBSC_DBPDRGA0, 0xB2 + i * 0x20);
-			mmio_write_32(DBSC_DBPDRGD0, r2 | ((r7 + 0x1) & 0x7));
-			mmio_write_32(DBSC_DBPDRGA0, 0xB0 + i * 0x20);
-			r2 = mmio_read_32(DBSC_DBPDRGD0) & 0xFFFFFF00;
-			mmio_write_32(DBSC_DBPDRGA0, 0xB0 + i * 0x20);
-			mmio_write_32(DBSC_DBPDRGD0, r2 | r6);
-		} else {
-			mmio_write_32(DBSC_DBPDRGA0, 0xB2 + i * 0x20);
-			r2 = mmio_read_32(DBSC_DBPDRGD0) & 0xFFFFFFF8;
-			mmio_write_32(DBSC_DBPDRGA0, 0xB2 + i * 0x20);
-			mmio_write_32(DBSC_DBPDRGD0, r2 | r7);
-
-			mmio_write_32(DBSC_DBPDRGA0, 0xB0 + i * 0x20);
-			r2 = mmio_read_32(DBSC_DBPDRGD0) & 0xFFFFFF00;
-			mmio_write_32(DBSC_DBPDRGA0, 0xB0 + i * 0x20);
-			mmio_write_32(DBSC_DBPDRGD0, r2 |
-						     ((r6 + (r5 << 1)) & 0xFF));
-		}
-	}
-
-	mmio_write_32(DBSC_DBPDRGA0, 0x00000005);
-	mmio_write_32(DBSC_DBPDRGD0, 0xC1AA00C0);
-	mmio_write_32(DBSC_DBPDRGA0, 0x000000A0);
-	mmio_write_32(DBSC_DBPDRGD0, 0x7C0002C5);
-	mmio_write_32(DBSC_DBPDRGA0, 0x000000C0);
-	mmio_write_32(DBSC_DBPDRGD0, 0x7C0002C5);
-	mmio_write_32(DBSC_DBPDRGA0, 0x00000001);
-	mmio_write_32(DBSC_DBPDRGD0, 0x00010801);
-	mmio_write_32(DBSC_DBPDRGA0, 0x00000006);
-	while (!(mmio_read_32(DBSC_DBPDRGD0) & BIT(0)))
-		;
-
-	mmio_write_32(DBSC_DBPDRGA0, 0x00000005);
-	mmio_write_32(DBSC_DBPDRGD0, 0xC1AA00D8);
-	mmio_write_32(DBSC_DBPDRGA0, 0x00000001);
-	mmio_write_32(DBSC_DBPDRGD0, 0x0001F001);
-	mmio_write_32(DBSC_DBPDRGA0, 0x00000006);
-	while (!(mmio_read_32(DBSC_DBPDRGD0) & BIT(0)))
-		;
-
-	mmio_write_32(DBSC_DBPDRGA0, 0x000000AF);
-	r2 = mmio_read_32(DBSC_DBPDRGD0);
-	mmio_write_32(DBSC_DBPDRGD0, ((r2 + 0x1) & 0xFF) | (r2 & 0xFFFFFF00));
-	mmio_write_32(DBSC_DBPDRGA0, 0x000000CF);
-	r2 = mmio_read_32(DBSC_DBPDRGD0);
-	mmio_write_32(DBSC_DBPDRGD0, ((r2 + 0x1) & 0xFF) | (r2 & 0xFFFFFF00));
-
-	mmio_write_32(DBSC_DBPDRGA0, 0x000000A0);
-	mmio_write_32(DBSC_DBPDRGD0, 0x7C000285);
-	mmio_write_32(DBSC_DBPDRGA0, 0x000000C0);
-	mmio_write_32(DBSC_DBPDRGD0, 0x7C000285);
-	mmio_write_32(DBSC_DBPDRGA0, 0x0000002C);
-	mmio_write_32(DBSC_DBPDRGD0, 0x81003087);
-	mmio_write_32(DBSC_DBPDRGA0, 0x00000001);
-	mmio_write_32(DBSC_DBPDRGD0, 0x00010401);
-	mmio_write_32(DBSC_DBPDRGA0, 0x00000006);
-	while (!(mmio_read_32(DBSC_DBPDRGD0) & BIT(0)))
-		;
-
-	for (i = 0; i < 2; i++) {
-		mmio_write_32(DBSC_DBPDRGA0, 0xB1 + i * 0x20);
-		r5 = ((mmio_read_32(DBSC_DBPDRGD0) & 0xFF00) >> 0x8);
-		mmio_write_32(DBSC_DBPDRGA0, 0xB4 + i * 0x20);
-		r6 = mmio_read_32(DBSC_DBPDRGD0) & 0xFF;
-
-		mmio_write_32(DBSC_DBPDRGA0, 0xB3 + i * 0x20);
-		r7 = mmio_read_32(DBSC_DBPDRGD0) & 0x7;
-		r12 = (r5 >> 0x2);
-
-		if (r12 < r6) {
-			mmio_write_32(DBSC_DBPDRGA0, 0xB2 + i * 0x20);
-			r2 = mmio_read_32(DBSC_DBPDRGD0) & 0xFFFFFFF8;
-
-			mmio_write_32(DBSC_DBPDRGA0, 0xB2 + i * 0x20);
-			mmio_write_32(DBSC_DBPDRGD0, r2 | ((r7 + 0x1) & 0x7));
-			mmio_write_32(DBSC_DBPDRGA0, 0xB0 + i * 0x20);
-			r2 = mmio_read_32(DBSC_DBPDRGD0) & 0xFFFFFF00;
-
-			mmio_write_32(DBSC_DBPDRGA0, 0xB0 + i * 0x20);
-			mmio_write_32(DBSC_DBPDRGD0, r2 | ((r6 - r12) & 0xFF));
-		} else {
-			mmio_write_32(DBSC_DBPDRGA0, 0xB2 + i * 0x20);
-			r2 = mmio_read_32(DBSC_DBPDRGD0) & 0xFFFFFFF8;
-			mmio_write_32(DBSC_DBPDRGA0, 0xB2 + i * 0x20);
-			mmio_write_32(DBSC_DBPDRGD0, r2 | (r7 & 0x7));
-			mmio_write_32(DBSC_DBPDRGA0, 0xB0 + i * 0x20);
-			r2 = mmio_read_32(DBSC_DBPDRGD0) & 0xFFFFFF00;
-			mmio_write_32(DBSC_DBPDRGA0, 0xB0 + i * 0x20);
-			mmio_write_32(DBSC_DBPDRGD0, r2 |
-						     ((r6 + r5 +
-						      (r5 >> 1) + r12) & 0xFF));
-		}
-	}
-
-	mmio_write_32(DBSC_DBPDRGA0, 0x000000A0);
-	mmio_write_32(DBSC_DBPDRGD0, 0x7C0002C5);
-	mmio_write_32(DBSC_DBPDRGA0, 0x000000C0);
-	mmio_write_32(DBSC_DBPDRGD0, 0x7C0002C5);
-	mmio_write_32(DBSC_DBPDRGA0, 0x00000001);
-	mmio_write_32(DBSC_DBPDRGD0, 0x00015001);
-	mmio_write_32(DBSC_DBPDRGA0, 0x00000006);
-	while (!(mmio_read_32(DBSC_DBPDRGD0) & BIT(0)))
-		;
-
-	mmio_write_32(DBSC_DBPDRGA0, 0x00000003);
-	mmio_write_32(DBSC_DBPDRGD0, 0x0380C700);
-	mmio_write_32(DBSC_DBPDRGA0, 0x00000007);
-	while (mmio_read_32(DBSC_DBPDRGD0) & BIT(30))
-		;
-	mmio_write_32(DBSC_DBPDRGA0, 0x00000021);
-	mmio_write_32(DBSC_DBPDRGD0, 0x0024643E);
-
-	mmio_write_32(DBSC_DBBUS0CNF1, 0x00000010);
-	mmio_write_32(DBSC_DBCALCNF, 0x0100401B);
-	mmio_write_32(DBSC_DBRFCNF1, 0x00080E23);
-	mmio_write_32(DBSC_DBRFCNF2, 0x00010000);
-	mmio_write_32(DBSC_DBDFICUPDCNF, 0x40100001);
-	mmio_write_32(DBSC_DBRFEN, 0x00000001);
-	mmio_write_32(DBSC_DBACEN, 0x00000001);
-	mmio_write_32(DBSC_DBPDLK0, 0x00000000);
-	mmio_write_32(DBSC_DBSYSCNT0, 0x00000000);
-
-#ifdef ddr_qos_init_setting // only for non qos_init
-	mmio_write_32(DBSC_DBSYSCNT0, 0x00001234);
-	mmio_write_32(DBSC_DBCAM0CNF1, 0x00043218);
-	mmio_write_32(DBSC_DBCAM0CNF2, 0x000000F4);
-	mmio_write_32(DBSC_DBSCHCNT0, 0x000f0037);
-	mmio_write_32(DBSC_DBSCHSZ0, 0x00000001);
-	mmio_write_32(DBSC_DBSCHRW0, 0x22421111);
-	mmio_write_32(DBSC_SCFCTST2, 0x012F1123);
-	mmio_write_32(DBSC_DBSCHQOS00, 0x00000F00);
-	mmio_write_32(DBSC_DBSCHQOS01, 0x00000B00);
-	mmio_write_32(DBSC_DBSCHQOS02, 0x00000000);
-	mmio_write_32(DBSC_DBSCHQOS03, 0x00000000);
-	mmio_write_32(DBSC_DBSCHQOS40, 0x00000300);
-	mmio_write_32(DBSC_DBSCHQOS41, 0x000002F0);
-	mmio_write_32(DBSC_DBSCHQOS42, 0x00000200);
-	mmio_write_32(DBSC_DBSCHQOS43, 0x00000100);
-	mmio_write_32(DBSC_DBSCHQOS90, 0x00000300);
-	mmio_write_32(DBSC_DBSCHQOS91, 0x000002F0);
-	mmio_write_32(DBSC_DBSCHQOS92, 0x00000200);
-	mmio_write_32(DBSC_DBSCHQOS93, 0x00000100);
-	mmio_write_32(DBSC_DBSCHQOS130, 0x00000100);
-	mmio_write_32(DBSC_DBSCHQOS131, 0x000000F0);
-	mmio_write_32(DBSC_DBSCHQOS132, 0x000000A0);
-	mmio_write_32(DBSC_DBSCHQOS133, 0x00000040);
-	mmio_write_32(DBSC_DBSCHQOS140, 0x000000C0);
-	mmio_write_32(DBSC_DBSCHQOS141, 0x000000B0);
-	mmio_write_32(DBSC_DBSCHQOS142, 0x00000080);
-	mmio_write_32(DBSC_DBSCHQOS143, 0x00000040);
-	mmio_write_32(DBSC_DBSCHQOS150, 0x00000040);
-	mmio_write_32(DBSC_DBSCHQOS151, 0x00000030);
-	mmio_write_32(DBSC_DBSCHQOS152, 0x00000020);
-	mmio_write_32(DBSC_DBSCHQOS153, 0x00000010);
-	mmio_write_32(0xE67F0018, 0x00000001);
-	mmio_write_32(DBSC_DBSYSCNT0, 0x00000000);
-#endif
-}
-
-static void init_ddr_d3_1600(void)
-{
-	uint32_t i, r2, r3, r5, r6, r7, r12;
-
-	mmio_write_32(DBSC_DBSYSCNT0, 0x00001234);
-	mmio_write_32(DBSC_DBKIND, 0x00000007);
-	mmio_write_32(DBSC_DBMEMCONF00, 0x0f030a01);
-	mmio_write_32(DBSC_DBPHYCONF0, 0x00000001);
-	mmio_write_32(DBSC_DBTR0, 0x0000000B);
-	mmio_write_32(DBSC_DBTR1, 0x00000008);
-	mmio_write_32(DBSC_DBTR2, 0x00000000);
-	mmio_write_32(DBSC_DBTR3, 0x0000000B);
-	mmio_write_32(DBSC_DBTR4, 0x000B000B);
-	mmio_write_32(DBSC_DBTR5, 0x00000027);
-	mmio_write_32(DBSC_DBTR6, 0x0000001C);
-	mmio_write_32(DBSC_DBTR7, 0x00060006);
-	mmio_write_32(DBSC_DBTR8, 0x00000020);
-	mmio_write_32(DBSC_DBTR9, 0x00000006);
-	mmio_write_32(DBSC_DBTR10, 0x0000000C);
-	mmio_write_32(DBSC_DBTR11, 0x0000000A);
-	mmio_write_32(DBSC_DBTR12, 0x00120012);
-	mmio_write_32(DBSC_DBTR13, 0x000000D0);
-	mmio_write_32(DBSC_DBTR14, 0x00140005);
-	mmio_write_32(DBSC_DBTR15, 0x00050004);
-	mmio_write_32(DBSC_DBTR16, 0x071F0305);
-	mmio_write_32(DBSC_DBTR17, 0x040C0000);
-	mmio_write_32(DBSC_DBTR18, 0x00000200);
-	mmio_write_32(DBSC_DBTR19, 0x01000040);
-	mmio_write_32(DBSC_DBTR20, 0x020000D8);
-	mmio_write_32(DBSC_DBTR21, 0x00040004);
-	mmio_write_32(DBSC_DBBL, 0x00000000);
-	mmio_write_32(DBSC_DBODT0, 0x00000001);
-	mmio_write_32(DBSC_DBADJ0, 0x00000001);
-	mmio_write_32(DBSC_DBSYSCONF1, 0x00000002);
-	mmio_write_32(DBSC_DBDFICNT0, 0x00000010);
-	mmio_write_32(DBSC_DBBCAMDIS, 0x00000001);
-	mmio_write_32(DBSC_DBSCHRW1, 0x00000046);
-	mmio_write_32(DBSC_SCFCTST0, 0x0D020C04);
-	mmio_write_32(DBSC_SCFCTST1, 0x0305040C);
-
-	mmio_write_32(DBSC_DBPDLK0, 0x0000A55A);
-	mmio_write_32(DBSC_DBCMD, 0x01000001);
-	mmio_write_32(DBSC_DBCMD, 0x08000000);
-	mmio_write_32(DBSC_DBPDRGA0, 0x00000001);
-	mmio_write_32(DBSC_DBPDRGD0, 0x80010000);
-	mmio_write_32(DBSC_DBPDRGA0, 0x00000006);
-	while (!(mmio_read_32(DBSC_DBPDRGD0) & BIT(0)))
-		;
-
-	mmio_write_32(DBSC_DBPDRGA0, 0x00000008);
-	mmio_write_32(DBSC_DBPDRGD0, 0x000B8000);
-	mmio_write_32(DBSC_DBPDRGA0, 0x00000090);
-	mmio_write_32(DBSC_DBPDRGD0, 0x04058904);
-	mmio_write_32(DBSC_DBPDRGA0, 0x00000091);
-	mmio_write_32(DBSC_DBPDRGD0, 0x0007BB6B);
-	mmio_write_32(DBSC_DBPDRGA0, 0x00000095);
-	mmio_write_32(DBSC_DBPDRGD0, 0x0007BBAD);
-	mmio_write_32(DBSC_DBPDRGA0, 0x00000099);
-	mmio_write_32(DBSC_DBPDRGD0, 0x0007BB6B);
-	mmio_write_32(DBSC_DBPDRGA0, 0x00000090);
-	mmio_write_32(DBSC_DBPDRGD0, 0x04058900);
-	mmio_write_32(DBSC_DBPDRGA0, 0x00000021);
-	mmio_write_32(DBSC_DBPDRGD0, 0x0024641E);
-	mmio_write_32(DBSC_DBPDRGA0, 0x00000001);
-	mmio_write_32(DBSC_DBPDRGD0, 0x00010073);
-	mmio_write_32(DBSC_DBPDRGA0, 0x00000006);
-	while (!(mmio_read_32(DBSC_DBPDRGD0) & BIT(0)))
-		;
-
-	mmio_write_32(DBSC_DBPDRGA0, 0x00000090);
-	mmio_write_32(DBSC_DBPDRGD0, 0x0C058900);
-	mmio_write_32(DBSC_DBPDRGA0, 0x00000090);
-	mmio_write_32(DBSC_DBPDRGD0, 0x04058900);
-	mmio_write_32(DBSC_DBPDRGA0, 0x00000006);
-	while (!(mmio_read_32(DBSC_DBPDRGD0) & BIT(0)))
-		;
-
-	mmio_write_32(DBSC_DBPDRGA0, 0x00000003);
-	mmio_write_32(DBSC_DBPDRGD0, 0x0780C700);
-	mmio_write_32(DBSC_DBPDRGA0, 0x00000007);
-	while (!(mmio_read_32(DBSC_DBPDRGD0) & BIT(30)))
-		;
-
-	mmio_write_32(DBSC_DBPDRGA0, 0x00000004);
-	mmio_write_32(DBSC_DBPDRGD0, 0x08C05FF0);
-	mmio_write_32(DBSC_DBPDRGA0, 0x00000022);
-	mmio_write_32(DBSC_DBPDRGD0, 0x1000040B);
-	mmio_write_32(DBSC_DBPDRGA0, 0x00000023);
-	mmio_write_32(DBSC_DBPDRGD0, 0x2D9C0B66);
-	mmio_write_32(DBSC_DBPDRGA0, 0x00000024);
-	mmio_write_32(DBSC_DBPDRGD0, 0x2A88C400);
-	mmio_write_32(DBSC_DBPDRGA0, 0x00000025);
-	mmio_write_32(DBSC_DBPDRGD0, 0x30005200);
-	mmio_write_32(DBSC_DBPDRGA0, 0x00000026);
-	mmio_write_32(DBSC_DBPDRGD0, 0x0014A9C9);
-	mmio_write_32(DBSC_DBPDRGA0, 0x00000027);
-	mmio_write_32(DBSC_DBPDRGD0, 0x00000D70);
-	mmio_write_32(DBSC_DBPDRGA0, 0x00000028);
-	mmio_write_32(DBSC_DBPDRGD0, 0x00000046);
-	mmio_write_32(DBSC_DBPDRGA0, 0x00000029);
-	mmio_write_32(DBSC_DBPDRGD0, 0x00000098);
-	mmio_write_32(DBSC_DBPDRGA0, 0x0000002C);
-	mmio_write_32(DBSC_DBPDRGD0, 0x81003047);
-	mmio_write_32(DBSC_DBPDRGA0, 0x00000020);
-	mmio_write_32(DBSC_DBPDRGD0, 0x00181884);
-	mmio_write_32(DBSC_DBPDRGA0, 0x0000001A);
-	mmio_write_32(DBSC_DBPDRGD0, 0x33C03C10);
-	mmio_write_32(DBSC_DBPDRGA0, 0x00000006);
-	while (!(mmio_read_32(DBSC_DBPDRGD0) & BIT(0)))
-		;
-
-	mmio_write_32(DBSC_DBPDRGA0, 0x000000A7);
-	mmio_write_32(DBSC_DBPDRGD0, 0x0D0D0D0D);
-	mmio_write_32(DBSC_DBPDRGA0, 0x000000A8);
-	mmio_write_32(DBSC_DBPDRGD0, 0x0D0D0D0D);
-	mmio_write_32(DBSC_DBPDRGA0, 0x000000A9);
-	mmio_write_32(DBSC_DBPDRGD0, 0x000D0D0D);
-	mmio_write_32(DBSC_DBPDRGA0, 0x000000C7);
-	mmio_write_32(DBSC_DBPDRGD0, 0x0D0D0D0D);
-	mmio_write_32(DBSC_DBPDRGA0, 0x000000C8);
-	mmio_write_32(DBSC_DBPDRGD0, 0x0D0D0D0D);
-	mmio_write_32(DBSC_DBPDRGA0, 0x000000C9);
-	mmio_write_32(DBSC_DBPDRGD0, 0x000D0D0D);
-
-	mmio_write_32(DBSC_DBPDRGA0, 0x0000000E);
-	r2 = (mmio_read_32(DBSC_DBPDRGD0) & 0x0000FF00) >> 0x9;
-	r3 = (r2 << 16) + (r2 << 8) + r2;
-	r6 = (r2 << 24) + (r2 << 16) + (r2 << 8) + r2;
-	mmio_write_32(DBSC_DBPDRGA0, 0x00000011);
-	mmio_write_32(DBSC_DBPDRGD0, r3);
-	mmio_write_32(DBSC_DBPDRGA0, 0x00000012);
-	mmio_write_32(DBSC_DBPDRGD0, r3);
-	mmio_write_32(DBSC_DBPDRGA0, 0x00000016);
-	mmio_write_32(DBSC_DBPDRGD0, r6);
-	mmio_write_32(DBSC_DBPDRGA0, 0x00000017);
-	mmio_write_32(DBSC_DBPDRGD0, r6);
-	mmio_write_32(DBSC_DBPDRGA0, 0x00000018);
-	mmio_write_32(DBSC_DBPDRGD0, r6);
-	mmio_write_32(DBSC_DBPDRGA0, 0x00000019);
-	mmio_write_32(DBSC_DBPDRGD0, r6);
-
-	mmio_write_32(DBSC_DBPDRGA0, 0x00000001);
-	mmio_write_32(DBSC_DBPDRGD0, 0x00010181);
-	mmio_write_32(DBSC_DBCMD, 0x08000001);
-	mmio_write_32(DBSC_DBPDRGA0, 0x00000006);
-	while (!(mmio_read_32(DBSC_DBPDRGD0) & BIT(0)))
-		;
-
-	mmio_write_32(DBSC_DBPDRGA0, 0x00000001);
-	mmio_write_32(DBSC_DBPDRGD0, 0x00010601);
-	mmio_write_32(DBSC_DBPDRGA0, 0x00000006);
-	while (!(mmio_read_32(DBSC_DBPDRGD0) & BIT(0)))
-		;
-
-	for (i = 0; i < 2; i++) {
-		mmio_write_32(DBSC_DBPDRGA0, 0xB1 + i * 0x20);
-		r5 = (mmio_read_32(DBSC_DBPDRGD0) & 0xFF00) >> 0x8;
-		mmio_write_32(DBSC_DBPDRGA0, 0xB4 + i * 0x20);
-		r6 = mmio_read_32(DBSC_DBPDRGD0) & 0xFF;
-		mmio_write_32(DBSC_DBPDRGA0, 0xB3 + i * 0x20);
-		r7 = mmio_read_32(DBSC_DBPDRGD0) & 0x7;
-		if (r6 > 0) {
-			mmio_write_32(DBSC_DBPDRGA0, 0xB2 + i * 0x20);
-			r2 = mmio_read_32(DBSC_DBPDRGD0) & 0xFFFFFFF8;
-
-			mmio_write_32(DBSC_DBPDRGA0, 0xB2 + i * 0x20);
-			mmio_write_32(DBSC_DBPDRGD0, r2 | ((r7 + 0x1) & 0x7));
-			mmio_write_32(DBSC_DBPDRGA0, 0xB0 + i * 0x20);
-			r2 = mmio_read_32(DBSC_DBPDRGD0) & 0xFFFFFF00;
-			mmio_write_32(DBSC_DBPDRGA0, 0xB0 + i * 0x20);
-			mmio_write_32(DBSC_DBPDRGD0, r2 | r6);
-		} else {
-			mmio_write_32(DBSC_DBPDRGA0, 0xB2 + i * 0x20);
-			r2 = mmio_read_32(DBSC_DBPDRGD0) & 0xFFFFFFF8;
-			mmio_write_32(DBSC_DBPDRGA0, 0xB2 + i * 0x20);
-			mmio_write_32(DBSC_DBPDRGD0, r2 | r7);
-
-			mmio_write_32(DBSC_DBPDRGA0, 0xB0 + i * 0x20);
-			r2 = mmio_read_32(DBSC_DBPDRGD0) & 0xFFFFFF00;
-			mmio_write_32(DBSC_DBPDRGA0, 0xB0 + i * 0x20);
-			mmio_write_32(DBSC_DBPDRGD0, r2 |
-						     ((r6 + (r5 << 1)) & 0xFF));
-		}
-	}
-
-	mmio_write_32(DBSC_DBPDRGA0, 0x00000005);
-	mmio_write_32(DBSC_DBPDRGD0, 0xC1AA00C0);
-	mmio_write_32(DBSC_DBPDRGA0, 0x000000A0);
-	mmio_write_32(DBSC_DBPDRGD0, 0x7C0002C5);
-	mmio_write_32(DBSC_DBPDRGA0, 0x000000C0);
-	mmio_write_32(DBSC_DBPDRGD0, 0x7C0002C5);
-	mmio_write_32(DBSC_DBPDRGA0, 0x00000001);
-	mmio_write_32(DBSC_DBPDRGD0, 0x00010801);
-	mmio_write_32(DBSC_DBPDRGA0, 0x00000006);
-	while (!(mmio_read_32(DBSC_DBPDRGD0) & BIT(0)))
-		;
-
-	mmio_write_32(DBSC_DBPDRGA0, 0x00000005);
-	mmio_write_32(DBSC_DBPDRGD0, 0xC1AA00D8);
-	mmio_write_32(DBSC_DBPDRGA0, 0x00000001);
-	mmio_write_32(DBSC_DBPDRGD0, 0x0001F001);
-	mmio_write_32(DBSC_DBPDRGA0, 0x00000006);
-	while (!(mmio_read_32(DBSC_DBPDRGD0) & BIT(0)))
-		;
-
-	mmio_write_32(DBSC_DBPDRGA0, 0x000000AF);
-	r2 = mmio_read_32(DBSC_DBPDRGD0);
-	mmio_write_32(DBSC_DBPDRGD0, ((r2 + 0x1) & 0xFF) | (r2 & 0xFFFFFF00));
-	mmio_write_32(DBSC_DBPDRGA0, 0x000000CF);
-	r2 = mmio_read_32(DBSC_DBPDRGD0);
-	mmio_write_32(DBSC_DBPDRGD0, ((r2 + 0x1) & 0xFF) | (r2 & 0xFFFFFF00));
-
-	mmio_write_32(DBSC_DBPDRGA0, 0x000000A0);
-	mmio_write_32(DBSC_DBPDRGD0, 0x7C000285);
-	mmio_write_32(DBSC_DBPDRGA0, 0x000000C0);
-	mmio_write_32(DBSC_DBPDRGD0, 0x7C000285);
-	mmio_write_32(DBSC_DBPDRGA0, 0x0000002C);
-	mmio_write_32(DBSC_DBPDRGD0, 0x81003087);
-	mmio_write_32(DBSC_DBPDRGA0, 0x00000001);
-	mmio_write_32(DBSC_DBPDRGD0, 0x00010401);
-	mmio_write_32(DBSC_DBPDRGA0, 0x00000006);
-	while (!(mmio_read_32(DBSC_DBPDRGD0) & BIT(0)))
-		;
-
-	for (i = 0; i < 2; i++) {
-		mmio_write_32(DBSC_DBPDRGA0, 0xB1 + i * 0x20);
-		r5 = (mmio_read_32(DBSC_DBPDRGD0) & 0xFF00) >> 0x8;
-		mmio_write_32(DBSC_DBPDRGA0, 0xB4 + i * 0x20);
-		r6 = mmio_read_32(DBSC_DBPDRGD0) & 0xFF;
-
-		mmio_write_32(DBSC_DBPDRGA0, 0xB3 + i * 0x20);
-		r7 = mmio_read_32(DBSC_DBPDRGD0) & 0x7;
-		r12 = (r5 >> 0x2);
-
-		if (r12 < r6) {
-			mmio_write_32(DBSC_DBPDRGA0, 0xB2 + i * 0x20);
-			r2 = mmio_read_32(DBSC_DBPDRGD0) & 0xFFFFFFF8;
-
-			mmio_write_32(DBSC_DBPDRGA0, 0xB2 + i * 0x20);
-			mmio_write_32(DBSC_DBPDRGD0, r2 | ((r7 + 0x1) & 0x7));
-			mmio_write_32(DBSC_DBPDRGA0, 0xB0 + i * 0x20);
-			r2 = mmio_read_32(DBSC_DBPDRGD0) & 0xFFFFFF00;
-
-			mmio_write_32(DBSC_DBPDRGA0, 0xB0 + i * 0x20);
-			mmio_write_32(DBSC_DBPDRGD0, r2 | ((r6 - r12) & 0xFF));
-		} else {
-			mmio_write_32(DBSC_DBPDRGA0, 0xB2 + i * 0x20);
-			r2 = mmio_read_32(DBSC_DBPDRGD0) & 0xFFFFFFF8;
-			mmio_write_32(DBSC_DBPDRGA0, 0xB2 + i * 0x20);
-			mmio_write_32(DBSC_DBPDRGD0, r2 | (r7 & 0x7));
-			mmio_write_32(DBSC_DBPDRGA0, 0xB0 + i * 0x20);
-			r2 = mmio_read_32(DBSC_DBPDRGD0) & 0xFFFFFF00;
-			mmio_write_32(DBSC_DBPDRGA0, 0xB0 + i * 0x20);
-			mmio_write_32(DBSC_DBPDRGD0, r2 |
-						     ((r6 + r5 +
-						      (r5 >> 1) + r12) & 0xFF));
-		}
-	}
-
-	mmio_write_32(DBSC_DBPDRGA0, 0x000000A0);
-	mmio_write_32(DBSC_DBPDRGD0, 0x7C0002C5);
-	mmio_write_32(DBSC_DBPDRGA0, 0x000000C0);
-	mmio_write_32(DBSC_DBPDRGD0, 0x7C0002C5);
-	mmio_write_32(DBSC_DBPDRGA0, 0x00000001);
-	mmio_write_32(DBSC_DBPDRGD0, 0x00015001);
-	mmio_write_32(DBSC_DBPDRGA0, 0x00000006);
-	while (!(mmio_read_32(DBSC_DBPDRGD0) & BIT(0)))
-		;
-
-	mmio_write_32(DBSC_DBPDRGA0, 0x00000003);
-	mmio_write_32(DBSC_DBPDRGD0, 0x0380C700);
-	mmio_write_32(DBSC_DBPDRGA0, 0x00000007);
-	while (mmio_read_32(DBSC_DBPDRGD0) & BIT(30))
-		;
-	mmio_write_32(DBSC_DBPDRGA0, 0x00000021);
-	mmio_write_32(DBSC_DBPDRGD0, 0x0024643E);
-
-	mmio_write_32(DBSC_DBBUS0CNF1, 0x00000010);
-	mmio_write_32(DBSC_DBCALCNF, 0x0100401B);
-	mmio_write_32(DBSC_DBRFCNF1, 0x00080C30);
-	mmio_write_32(DBSC_DBRFCNF2, 0x00010000);
-	mmio_write_32(DBSC_DBDFICUPDCNF, 0x40100001);
-	mmio_write_32(DBSC_DBRFEN, 0x00000001);
-	mmio_write_32(DBSC_DBACEN, 0x00000001);
-	mmio_write_32(DBSC_DBPDLK0, 0x00000000);
-	mmio_write_32(DBSC_DBSYSCNT0, 0x00000000);
-
-#ifdef ddr_qos_init_setting // only for non qos_init
-	mmio_write_32(DBSC_DBSYSCNT0, 0x00001234);
-	mmio_write_32(DBSC_DBCAM0CNF1, 0x00043218);
-	mmio_write_32(DBSC_DBCAM0CNF2, 0x000000F4);
-	mmio_write_32(DBSC_DBSCHCNT0, 0x000f0037);
-	mmio_write_32(DBSC_DBSCHSZ0, 0x00000001);
-	mmio_write_32(DBSC_DBSCHRW0, 0x22421111);
-	mmio_write_32(DBSC_SCFCTST2, 0x012F1123);
-	mmio_write_32(DBSC_DBSCHQOS00, 0x00000F00);
-	mmio_write_32(DBSC_DBSCHQOS01, 0x00000B00);
-	mmio_write_32(DBSC_DBSCHQOS02, 0x00000000);
-	mmio_write_32(DBSC_DBSCHQOS03, 0x00000000);
-	mmio_write_32(DBSC_DBSCHQOS40, 0x00000300);
-	mmio_write_32(DBSC_DBSCHQOS41, 0x000002F0);
-	mmio_write_32(DBSC_DBSCHQOS42, 0x00000200);
-	mmio_write_32(DBSC_DBSCHQOS43, 0x00000100);
-	mmio_write_32(DBSC_DBSCHQOS90, 0x00000300);
-	mmio_write_32(DBSC_DBSCHQOS91, 0x000002F0);
-	mmio_write_32(DBSC_DBSCHQOS92, 0x00000200);
-	mmio_write_32(DBSC_DBSCHQOS93, 0x00000100);
-	mmio_write_32(DBSC_DBSCHQOS130, 0x00000100);
-	mmio_write_32(DBSC_DBSCHQOS131, 0x000000F0);
-	mmio_write_32(DBSC_DBSCHQOS132, 0x000000A0);
-	mmio_write_32(DBSC_DBSCHQOS133, 0x00000040);
-	mmio_write_32(DBSC_DBSCHQOS140, 0x000000C0);
-	mmio_write_32(DBSC_DBSCHQOS141, 0x000000B0);
-	mmio_write_32(DBSC_DBSCHQOS142, 0x00000080);
-	mmio_write_32(DBSC_DBSCHQOS143, 0x00000040);
-	mmio_write_32(DBSC_DBSCHQOS150, 0x00000040);
-	mmio_write_32(DBSC_DBSCHQOS151, 0x00000030);
-	mmio_write_32(DBSC_DBSCHQOS152, 0x00000020);
-	mmio_write_32(DBSC_DBSCHQOS153, 0x00000010);
-	mmio_write_32(0xE67F0018, 0x00000001);
-	mmio_write_32(DBSC_DBSYSCNT0, 0x00000000);
-#endif
-}
-
-#define PRR			0xFFF00044U
-#define PRR_PRODUCT_MASK	0x00007F00U
-#define PRR_PRODUCT_D3		0x00005800U
-
-#define	MODEMR_MD19		BIT(19)
-
-int32_t rcar_dram_init(void)
-{
-	uint32_t reg;
-	uint32_t ddr_mbps;
-
-	reg = mmio_read_32(PRR);
-	if ((reg & PRR_PRODUCT_MASK) != PRR_PRODUCT_D3) {
-		ERROR("LSI Product ID (PRR=0x%x) DDR initialize not supported.\n",
-		      reg);
-		panic();
-	}
-
-	reg = mmio_read_32(RST_MODEMR);
-	if (reg & MODEMR_MD19) {
-		init_ddr_d3_1866();
-		ddr_mbps = 1866;
-	} else {
-		init_ddr_d3_1600();
-		ddr_mbps = 1600;
-	}
-
-	NOTICE("BL2: DDR%d\n", ddr_mbps);
-
-	return 0;
-}
diff --git a/drivers/staging/renesas/rcar/ddr/ddr_a/ddr_init_e3.c b/drivers/staging/renesas/rcar/ddr/ddr_a/ddr_init_e3.c
deleted file mode 100644
index 7aedc88d6..000000000
--- a/drivers/staging/renesas/rcar/ddr/ddr_a/ddr_init_e3.c
+++ /dev/null
@@ -1,1711 +0,0 @@
-/*
- * Copyright (c) 2015-2019, Renesas Electronics Corporation.
- * All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#include <lib/mmio.h>
-#include <stdint.h>
-
-#include <common/debug.h>
-
-#include "boot_init_dram.h"
-#include "boot_init_dram_regdef.h"
-
-#include "../dram_sub_func.h"
-
-#define RCAR_E3_DDR_VERSION    "rev.0.12"
-
-/* Average periodic refresh interval[ns]. Support 3900,7800 */
-#ifdef ddr_qos_init_setting
-#define REFRESH_RATE	3900U
-#else
-#if RCAR_REF_INT == 1
-#define REFRESH_RATE	7800U
-#else
-#define REFRESH_RATE	3900U
-#endif
-#endif
-
-/*
- *  Initialize ddr
- */
-uint32_t init_ddr(void)
-{
-	uint32_t i, r2, r5, r6, r7, r12;
-	uint32_t ddr_md;
-	uint32_t regval, j;
-	uint32_t dqsgd_0c, bdlcount_0c, bdlcount_0c_div2, bdlcount_0c_div4;
-	uint32_t bdlcount_0c_div8, bdlcount_0c_div16;
-	uint32_t gatesl_0c, rdqsd_0c, rdqsnd_0c, rbd_0c[4];
-	uint32_t pdqsr_ctl, lcdl_ctl, lcdl_judge1, lcdl_judge2;
-	uint32_t pdr_ctl;
-	uint32_t byp_ctl;
-
-	if ((mmio_read_32(0xFFF00044) & 0x000000FF) == 0x00000000) {
-		pdqsr_ctl = 1;
-		lcdl_ctl = 1;
-		pdr_ctl = 1;
-		byp_ctl = 1;
-	} else {
-		pdqsr_ctl = 0;
-		lcdl_ctl = 0;
-		pdr_ctl = 0;
-		byp_ctl = 0;
-	}
-
-	/* Judge the DDR bit rate (ddr_md : 0 = 1584Mbps, 1 = 1856Mbps) */
-	ddr_md = (mmio_read_32(RST_MODEMR) >> 19) & BIT(0);
-
-	/* 1584Mbps setting */
-	if (ddr_md == 0) {
-		mmio_write_32(CPG_CPGWPR, 0x5A5AFFFF);
-		mmio_write_32(CPG_CPGWPCR, 0xA5A50000);
-
-		mmio_write_32(CPG_SRCR4, 0x20000000);
-
-		mmio_write_32(0xE61500DC, 0xe2200000);	/* Change to 1584Mbps */
-		while (!(mmio_read_32(CPG_PLLECR) & BIT(11)))
-			;
-
-		mmio_write_32(CPG_SRSTCLR4, 0x20000000);
-
-		mmio_write_32(CPG_CPGWPCR, 0xA5A50001);
-	}
-
-	mmio_write_32(DBSC_DBSYSCNT0, 0x00001234);
-	mmio_write_32(DBSC_DBKIND, 0x00000007);
-
-#if RCAR_DRAM_DDR3L_MEMCONF == 0
-	mmio_write_32(DBSC_DBMEMCONF00, 0x0f030a02);	/* 1GB */
-#else
-	mmio_write_32(DBSC_DBMEMCONF00, 0x10030a02);	/* 2GB(default) */
-#endif
-
-#if RCAR_DRAM_DDR3L_MEMDUAL == 1
-	r2 = mmio_read_32(0xE6790614);
-	mmio_write_32(0xE6790614, r2 | 0x3); /* MCS1_N/MODT1 are activated. */
-#endif
-
-	mmio_write_32(DBSC_DBPHYCONF0, 0x1);
-
-	/* Select setting value in bps */
-	if (ddr_md == 0) {	/* 1584Mbps */
-		mmio_write_32(DBSC_DBTR0, 0xB);
-		mmio_write_32(DBSC_DBTR1, 0x8);
-	} else {		/* 1856Mbps */
-		mmio_write_32(DBSC_DBTR0, 0xD);
-		mmio_write_32(DBSC_DBTR1, 0x9);
-	}
-
-	mmio_write_32(DBSC_DBTR2, 0x00000000);
-
-	/* Select setting value in bps */
-	if (ddr_md == 0) {	/* 1584Mbps */
-		mmio_write_32(DBSC_DBTR3, 0x0000000B);
-		mmio_write_32(DBSC_DBTR4, 0x000B000B);
-		mmio_write_32(DBSC_DBTR5, 0x00000027);
-		mmio_write_32(DBSC_DBTR6, 0x0000001C);
-	} else {		/* 1856Mbps */
-		mmio_write_32(DBSC_DBTR3, 0x0000000D);
-		mmio_write_32(DBSC_DBTR4, 0x000D000D);
-		mmio_write_32(DBSC_DBTR5, 0x0000002D);
-		mmio_write_32(DBSC_DBTR6, 0x00000020);
-	}
-
-	mmio_write_32(DBSC_DBTR7, 0x00060006);
-
-	/* Select setting value in bps */
-	if (ddr_md == 0) {	/* 1584Mbps */
-		mmio_write_32(DBSC_DBTR8, 0x00000020);
-		mmio_write_32(DBSC_DBTR9, 0x00000006);
-		mmio_write_32(DBSC_DBTR10, 0x0000000C);
-		mmio_write_32(DBSC_DBTR11, 0x0000000A);
-		mmio_write_32(DBSC_DBTR12, 0x00120012);
-		mmio_write_32(DBSC_DBTR13, 0x000000CE);
-		mmio_write_32(DBSC_DBTR14, 0x00140005);
-		mmio_write_32(DBSC_DBTR15, 0x00050004);
-		mmio_write_32(DBSC_DBTR16, 0x071F0305);
-		mmio_write_32(DBSC_DBTR17, 0x040C0000);
-	} else {		/* 1856Mbps */
-		mmio_write_32(DBSC_DBTR8, 0x00000021);
-		mmio_write_32(DBSC_DBTR9, 0x00000007);
-		mmio_write_32(DBSC_DBTR10, 0x0000000E);
-		mmio_write_32(DBSC_DBTR11, 0x0000000C);
-		mmio_write_32(DBSC_DBTR12, 0x00140014);
-		mmio_write_32(DBSC_DBTR13, 0x000000F2);
-		mmio_write_32(DBSC_DBTR14, 0x00170006);
-		mmio_write_32(DBSC_DBTR15, 0x00060005);
-		mmio_write_32(DBSC_DBTR16, 0x09210507);
-		mmio_write_32(DBSC_DBTR17, 0x040E0000);
-	}
-
-	mmio_write_32(DBSC_DBTR18, 0x00000200);
-
-	/* Select setting value in bps */
-	if (ddr_md == 0) {	/* 1584Mbps */
-		mmio_write_32(DBSC_DBTR19, 0x01000040);
-		mmio_write_32(DBSC_DBTR20, 0x020000D6);
-	} else {		/* 1856Mbps */
-		mmio_write_32(DBSC_DBTR19, 0x0129004B);
-		mmio_write_32(DBSC_DBTR20, 0x020000FB);
-	}
-
-	mmio_write_32(DBSC_DBTR21, 0x00040004);
-	mmio_write_32(DBSC_DBBL, 0x00000000);
-	mmio_write_32(DBSC_DBODT0, 0x00000001);
-	mmio_write_32(DBSC_DBADJ0, 0x00000001);
-	mmio_write_32(DBSC_DBSYSCONF1, 0x00000002);
-	mmio_write_32(DBSC_DBDFICNT0, 0x00000010);
-	mmio_write_32(DBSC_DBBCAMDIS, 0x00000001);
-	mmio_write_32(DBSC_DBSCHRW1, 0x00000046);
-
-	/* Select setting value in bps */
-	if (ddr_md == 0) {	/* 1584Mbps */
-		mmio_write_32(DBSC_SCFCTST0, 0x0D050B03);
-		mmio_write_32(DBSC_SCFCTST1, 0x0306030C);
-	} else {		/* 1856Mbps */
-		mmio_write_32(DBSC_SCFCTST0, 0x0C050B03);
-		mmio_write_32(DBSC_SCFCTST1, 0x0305030C);
-	}
-
-	/*
-	 * Initial_Step0( INITBYP )
-	 */
-	mmio_write_32(DBSC_DBPDLK0, 0x0000A55A);
-	mmio_write_32(DBSC_DBCMD, 0x01840001);
-	mmio_write_32(DBSC_DBCMD, 0x08840000);
-	NOTICE("BL2: [COLD_BOOT]\n");
-	mmio_write_32(DBSC_DBPDRGA0, 0x00000001);
-	mmio_write_32(DBSC_DBPDRGD0, 0x80010000);
-	mmio_write_32(DBSC_DBPDRGA0, 0x00000006);
-	while (!(mmio_read_32(DBSC_DBPDRGD0) & BIT(0)))
-		;
-
-	/*
-	 * Initial_Step1( ZCAL,PLLINIT,DCAL,PHYRST training )
-	 */
-	mmio_write_32(DBSC_DBPDRGA0, 0x00000008);
-	mmio_write_32(DBSC_DBPDRGD0, 0x000B8000);
-	mmio_write_32(DBSC_DBPDRGA0, 0x00000090);
-
-	/* Select setting value in bps */
-	if (ddr_md == 0)	/* 1584Mbps */
-		mmio_write_32(DBSC_DBPDRGD0, 0x04058904);
-	else			/* 1856Mbps */
-		mmio_write_32(DBSC_DBPDRGD0, 0x04058A04);
-
-	mmio_write_32(DBSC_DBPDRGA0, 0x00000091);
-	mmio_write_32(DBSC_DBPDRGD0, 0x0007BB6B);
-	mmio_write_32(DBSC_DBPDRGA0, 0x00000095);
-	mmio_write_32(DBSC_DBPDRGD0, 0x0007BBAD);
-	mmio_write_32(DBSC_DBPDRGA0, 0x00000099);
-	mmio_write_32(DBSC_DBPDRGD0, 0x0007BB6B);
-	mmio_write_32(DBSC_DBPDRGA0, 0x00000090);
-
-	/* Select setting value in bps */
-	if (ddr_md == 0)	/* 1584Mbps */
-		mmio_write_32(DBSC_DBPDRGD0, 0x04058900);
-	else			/* 1856Mbps */
-		mmio_write_32(DBSC_DBPDRGD0, 0x04058A00);
-
-	mmio_write_32(DBSC_DBPDRGA0, 0x00000021);
-	mmio_write_32(DBSC_DBPDRGD0, 0x0024641E);
-	mmio_write_32(DBSC_DBPDRGA0, 0x00000001);
-	mmio_write_32(DBSC_DBPDRGD0, 0x00010073);
-	mmio_write_32(DBSC_DBPDRGA0, 0x00000006);
-	while (!(mmio_read_32(DBSC_DBPDRGD0) & BIT(0)))
-		;
-
-	/*
-	 * Initial_Step2( DRAMRST/DRAMINT training )
-	 */
-	mmio_write_32(DBSC_DBPDRGA0, 0x00000090);
-
-	/* Select setting value in bps */
-	if (ddr_md == 0)	/* 1584Mbps */
-		mmio_write_32(DBSC_DBPDRGD0, 0x0C058900);
-	else			/* 1856Mbps */
-		mmio_write_32(DBSC_DBPDRGD0, 0x0C058A00);
-
-	mmio_write_32(DBSC_DBPDRGA0, 0x00000090);
-
-	/* Select setting value in bps */
-	if (ddr_md == 0)	/* 1584Mbps */
-		mmio_write_32(DBSC_DBPDRGD0, 0x04058900);
-	else			/* 1856Mbps */
-		mmio_write_32(DBSC_DBPDRGD0, 0x04058A00);
-
-	mmio_write_32(DBSC_DBPDRGA0, 0x00000006);
-	while (!(mmio_read_32(DBSC_DBPDRGD0) & BIT(0)))
-		;
-
-	mmio_write_32(DBSC_DBPDRGA0, 0x00000003);
-	if (byp_ctl == 1)
-		mmio_write_32(DBSC_DBPDRGD0, 0x0780C720);
-	else
-		mmio_write_32(DBSC_DBPDRGD0, 0x0780C700);
-
-	mmio_write_32(DBSC_DBPDRGA0, 0x00000007);
-	while (!(mmio_read_32(DBSC_DBPDRGD0) & BIT(30)))
-		;
-
-	mmio_write_32(DBSC_DBPDRGA0, 0x00000004);
-
-	/* Select setting value in bps */
-	if (ddr_md == 0) {	/* 1584Mbps */
-		mmio_write_32(DBSC_DBPDRGD0, (REFRESH_RATE * 792 / 125) -
-					     400 + 0x08B00000);
-	} else {		/* 1856Mbps */
-		mmio_write_32(DBSC_DBPDRGD0, (REFRESH_RATE * 928 / 125) -
-					     400 + 0x0A300000);
-	}
-
-	mmio_write_32(DBSC_DBPDRGA0, 0x00000022);
-	mmio_write_32(DBSC_DBPDRGD0, 0x1000040B);
-	mmio_write_32(DBSC_DBPDRGA0, 0x00000023);
-
-	/* Select setting value in bps */
-	if (ddr_md == 0)	/* 1584Mbps */
-		mmio_write_32(DBSC_DBPDRGD0, 0x2D9C0B66);
-	else			/* 1856Mbps */
-		mmio_write_32(DBSC_DBPDRGD0, 0x35A00D77);
-
-	mmio_write_32(DBSC_DBPDRGA0, 0x00000024);
-
-	/* Select setting value in bps */
-	if (ddr_md == 0)	/* 1584Mbps */
-		mmio_write_32(DBSC_DBPDRGD0, 0x2A88B400);
-	else			/* 1856Mbps */
-		mmio_write_32(DBSC_DBPDRGD0, 0x2A8A2C28);
-
-	mmio_write_32(DBSC_DBPDRGA0, 0x00000025);
-
-	/* Select setting value in bps */
-	if (ddr_md == 0)	/* 1584Mbps */
-		mmio_write_32(DBSC_DBPDRGD0, 0x30005200);
-	else			/* 1856Mbps */
-		mmio_write_32(DBSC_DBPDRGD0, 0x30005E00);
-
-	mmio_write_32(DBSC_DBPDRGA0, 0x00000026);
-
-	/* Select setting value in bps */
-	if (ddr_md == 0)	/* 1584Mbps */
-		mmio_write_32(DBSC_DBPDRGD0, 0x0014A9C9);
-	else			/* 1856Mbps */
-		mmio_write_32(DBSC_DBPDRGD0, 0x0014CB49);
-
-	mmio_write_32(DBSC_DBPDRGA0, 0x00000027);
-
-	/* Select setting value in bps */
-	if (ddr_md == 0)	/* 1584Mbps */
-		mmio_write_32(DBSC_DBPDRGD0, 0x00000D70);
-	else			/* 1856Mbps */
-		mmio_write_32(DBSC_DBPDRGD0, 0x00000F14);
-
-	mmio_write_32(DBSC_DBPDRGA0, 0x00000028);
-	mmio_write_32(DBSC_DBPDRGD0, 0x00000046);
-	mmio_write_32(DBSC_DBPDRGA0, 0x00000029);
-
-	/* Select setting value in bps */
-	if (ddr_md == 0) {	/* 1584Mbps */
-		if (REFRESH_RATE > 3900)	/* [7]SRT=0 */
-			mmio_write_32(DBSC_DBPDRGD0, 0x18);
-		else				/* [7]SRT=1 */
-			mmio_write_32(DBSC_DBPDRGD0, 0x98);
-	} else {		/* 1856Mbps */
-		if (REFRESH_RATE > 3900)	/* [7]SRT=0 */
-			mmio_write_32(DBSC_DBPDRGD0, 0x20);
-		else				/* [7]SRT=1 */
-			mmio_write_32(DBSC_DBPDRGD0, 0xA0);
-	}
-
-	mmio_write_32(DBSC_DBPDRGA0, 0x0000002C);
-	mmio_write_32(DBSC_DBPDRGD0, 0x81003047);
-	mmio_write_32(DBSC_DBPDRGA0, 0x00000020);
-	mmio_write_32(DBSC_DBPDRGD0, 0x00181884);
-	mmio_write_32(DBSC_DBPDRGA0, 0x0000001A);
-	mmio_write_32(DBSC_DBPDRGD0, 0x33C03C10);
-	mmio_write_32(DBSC_DBPDRGA0, 0x00000006);
-	while (!(mmio_read_32(DBSC_DBPDRGD0) & BIT(0)))
-		;
-
-	mmio_write_32(DBSC_DBPDRGA0, 0x000000A7);
-	mmio_write_32(DBSC_DBPDRGD0, 0x0D0D0D0D);
-	mmio_write_32(DBSC_DBPDRGA0, 0x000000A8);
-	mmio_write_32(DBSC_DBPDRGD0, 0x0D0D0D0D);
-	mmio_write_32(DBSC_DBPDRGA0, 0x000000A9);
-	mmio_write_32(DBSC_DBPDRGD0, 0x000D0D0D);
-	mmio_write_32(DBSC_DBPDRGA0, 0x000000C7);
-	mmio_write_32(DBSC_DBPDRGD0, 0x0D0D0D0D);
-	mmio_write_32(DBSC_DBPDRGA0, 0x000000C8);
-	mmio_write_32(DBSC_DBPDRGD0, 0x0D0D0D0D);
-	mmio_write_32(DBSC_DBPDRGA0, 0x000000C9);
-	mmio_write_32(DBSC_DBPDRGD0, 0x000D0D0D);
-	mmio_write_32(DBSC_DBPDRGA0, 0x000000E7);
-	mmio_write_32(DBSC_DBPDRGD0, 0x0D0D0D0D);
-	mmio_write_32(DBSC_DBPDRGA0, 0x000000E8);
-	mmio_write_32(DBSC_DBPDRGD0, 0x0D0D0D0D);
-	mmio_write_32(DBSC_DBPDRGA0, 0x000000E9);
-	mmio_write_32(DBSC_DBPDRGD0, 0x000D0D0D);
-	mmio_write_32(DBSC_DBPDRGA0, 0x00000107);
-	mmio_write_32(DBSC_DBPDRGD0, 0x0D0D0D0D);
-	mmio_write_32(DBSC_DBPDRGA0, 0x00000108);
-	mmio_write_32(DBSC_DBPDRGD0, 0x0D0D0D0D);
-	mmio_write_32(DBSC_DBPDRGA0, 0x00000109);
-	mmio_write_32(DBSC_DBPDRGD0, 0x000D0D0D);
-
-	mmio_write_32(DBSC_DBPDRGA0, 0x00000001);
-	mmio_write_32(DBSC_DBPDRGD0, 0x00010181);
-	mmio_write_32(DBSC_DBCMD, 0x08840001);
-	mmio_write_32(DBSC_DBPDRGA0, 0x00000006);
-	while (!(mmio_read_32(DBSC_DBPDRGD0) & BIT(0)))
-		;
-
-	/*
-	 * Initial_Step3( WL/QSG training )
-	 */
-	mmio_write_32(DBSC_DBPDRGA0, 0x00000001);
-	mmio_write_32(DBSC_DBPDRGD0, 0x00010601);
-	mmio_write_32(DBSC_DBPDRGA0, 0x00000006);
-	while (!(mmio_read_32(DBSC_DBPDRGD0) & BIT(0)))
-		;
-
-	for (i = 0; i < 4; i++) {
-		mmio_write_32(DBSC_DBPDRGA0, 0xB1 + i * 0x20);
-		r5 = (mmio_read_32(DBSC_DBPDRGD0) & 0xFF00) >> 0x8;
-		mmio_write_32(DBSC_DBPDRGA0, 0xB4 + i * 0x20);
-		r6 = mmio_read_32(DBSC_DBPDRGD0) & 0xFF;
-		mmio_write_32(DBSC_DBPDRGA0, 0xB3 + i * 0x20);
-		r7 = mmio_read_32(DBSC_DBPDRGD0) & 0x7;
-
-		if (r6 > 0) {
-			mmio_write_32(DBSC_DBPDRGA0, 0xB2 + i * 0x20);
-			r2 = mmio_read_32(DBSC_DBPDRGD0) & 0xFFFFFFF8;
-			mmio_write_32(DBSC_DBPDRGA0, 0xB2 + i * 0x20);
-			mmio_write_32(DBSC_DBPDRGD0, r2 | ((r7 + 0x1) & 0x7));
-			mmio_write_32(DBSC_DBPDRGA0, 0xB0 + i * 0x20);
-			r2 = mmio_read_32(DBSC_DBPDRGD0) & 0xFFFFFF00;
-			mmio_write_32(DBSC_DBPDRGA0, 0xB0 + i * 0x20);
-			mmio_write_32(DBSC_DBPDRGD0, r2 | r6);
-		} else {
-			mmio_write_32(DBSC_DBPDRGA0, 0xB2 + i * 0x20);
-			r2 = mmio_read_32(DBSC_DBPDRGD0) & 0xFFFFFFF8;
-			mmio_write_32(DBSC_DBPDRGA0, 0xB2 + i * 0x20);
-			mmio_write_32(DBSC_DBPDRGD0, r2 | r7);
-			mmio_write_32(DBSC_DBPDRGA0, 0xB0 + i * 0x20);
-			r2 = mmio_read_32(DBSC_DBPDRGD0) & 0xFFFFFF00;
-			mmio_write_32(DBSC_DBPDRGA0, 0xB0 + i * 0x20);
-			mmio_write_32(DBSC_DBPDRGD0, r2 |
-						     ((r6 + ((r5) << 1)) &
-						     0xFF));
-		}
-	}
-
-	/*
-	 * Initial_Step4( WLADJ training )
-	 */
-	mmio_write_32(DBSC_DBPDRGA0, 0x00000005);
-	mmio_write_32(DBSC_DBPDRGD0, 0xC1AA00C0);
-
-	if (pdqsr_ctl == 0) {
-		mmio_write_32(DBSC_DBPDRGA0, 0x000000A0);
-		mmio_write_32(DBSC_DBPDRGD0, 0x7C0002C5);
-		mmio_write_32(DBSC_DBPDRGA0, 0x000000C0);
-		mmio_write_32(DBSC_DBPDRGD0, 0x7C0002C5);
-		mmio_write_32(DBSC_DBPDRGA0, 0x000000E0);
-		mmio_write_32(DBSC_DBPDRGD0, 0x7C0002C5);
-		mmio_write_32(DBSC_DBPDRGA0, 0x00000100);
-		mmio_write_32(DBSC_DBPDRGD0, 0x7C0002C5);
-	}
-
-	/* PDR always off */
-	if (pdr_ctl == 1) {
-		mmio_write_32(DBSC_DBPDRGA0, 0x000000A3);
-		mmio_write_32(DBSC_DBPDRGD0, 0x00000008);
-		mmio_write_32(DBSC_DBPDRGA0, 0x000000C3);
-		mmio_write_32(DBSC_DBPDRGD0, 0x00000008);
-		mmio_write_32(DBSC_DBPDRGA0, 0x000000E3);
-		mmio_write_32(DBSC_DBPDRGD0, 0x00000008);
-		mmio_write_32(DBSC_DBPDRGA0, 0x00000103);
-		mmio_write_32(DBSC_DBPDRGD0, 0x00000008);
-	}
-
-	mmio_write_32(DBSC_DBPDRGA0, 0x00000001);
-	mmio_write_32(DBSC_DBPDRGD0, 0x00010801);
-	mmio_write_32(DBSC_DBPDRGA0, 0x00000006);
-	while (!(mmio_read_32(DBSC_DBPDRGD0) & BIT(0)))
-		;
-
-	/*
-	 * Initial_Step5(Read Data Bit Deskew)
-	 */
-	mmio_write_32(DBSC_DBPDRGA0, 0x00000005);
-	mmio_write_32(DBSC_DBPDRGD0, 0xC1AA00D8);
-
-	mmio_write_32(DBSC_DBPDRGA0, 0x00000001);
-	mmio_write_32(DBSC_DBPDRGD0, 0x00011001);
-	mmio_write_32(DBSC_DBPDRGA0, 0x00000006);
-	while (!(mmio_read_32(DBSC_DBPDRGD0) & BIT(0)))
-		;
-
-	if (pdqsr_ctl == 1) {
-		mmio_write_32(DBSC_DBPDRGA0, 0x000000A0);
-		mmio_write_32(DBSC_DBPDRGD0, 0x7C0002C5);
-		mmio_write_32(DBSC_DBPDRGA0, 0x000000C0);
-		mmio_write_32(DBSC_DBPDRGD0, 0x7C0002C5);
-		mmio_write_32(DBSC_DBPDRGA0, 0x000000E0);
-		mmio_write_32(DBSC_DBPDRGD0, 0x7C0002C5);
-		mmio_write_32(DBSC_DBPDRGA0, 0x00000100);
-		mmio_write_32(DBSC_DBPDRGD0, 0x7C0002C5);
-	}
-
-	/* PDR dynamic */
-	if (pdr_ctl == 1) {
-		mmio_write_32(DBSC_DBPDRGA0, 0x000000A3);
-		mmio_write_32(DBSC_DBPDRGD0, 0x00000000);
-		mmio_write_32(DBSC_DBPDRGA0, 0x000000C3);
-		mmio_write_32(DBSC_DBPDRGD0, 0x00000000);
-		mmio_write_32(DBSC_DBPDRGA0, 0x000000E3);
-		mmio_write_32(DBSC_DBPDRGD0, 0x00000000);
-		mmio_write_32(DBSC_DBPDRGA0, 0x00000103);
-		mmio_write_32(DBSC_DBPDRGD0, 0x00000000);
-	}
-
-	/*
-	 * Initial_Step6(Write Data Bit Deskew)
-	 */
-	mmio_write_32(DBSC_DBPDRGA0, 0x00000001);
-	mmio_write_32(DBSC_DBPDRGD0, 0x00012001);
-	mmio_write_32(DBSC_DBPDRGA0, 0x00000006);
-	while (!(mmio_read_32(DBSC_DBPDRGD0) & BIT(0)))
-		;
-
-	/*
-	 * Initial_Step7(Read Data Eye Training)
-	 */
-	if (pdqsr_ctl == 1) {
-		mmio_write_32(DBSC_DBPDRGA0, 0x000000A0);
-		mmio_write_32(DBSC_DBPDRGD0, 0x7C000285);
-		mmio_write_32(DBSC_DBPDRGA0, 0x000000C0);
-		mmio_write_32(DBSC_DBPDRGD0, 0x7C000285);
-		mmio_write_32(DBSC_DBPDRGA0, 0x000000E0);
-		mmio_write_32(DBSC_DBPDRGD0, 0x7C000285);
-		mmio_write_32(DBSC_DBPDRGA0, 0x00000100);
-		mmio_write_32(DBSC_DBPDRGD0, 0x7C000285);
-	}
-
-	/* PDR always off */
-	if (pdr_ctl == 1) {
-		mmio_write_32(DBSC_DBPDRGA0, 0x000000A3);
-		mmio_write_32(DBSC_DBPDRGD0, 0x00000008);
-		mmio_write_32(DBSC_DBPDRGA0, 0x000000C3);
-		mmio_write_32(DBSC_DBPDRGD0, 0x00000008);
-		mmio_write_32(DBSC_DBPDRGA0, 0x000000E3);
-		mmio_write_32(DBSC_DBPDRGD0, 0x00000008);
-		mmio_write_32(DBSC_DBPDRGA0, 0x00000103);
-		mmio_write_32(DBSC_DBPDRGD0, 0x00000008);
-	}
-
-	mmio_write_32(DBSC_DBPDRGA0, 0x00000001);
-	mmio_write_32(DBSC_DBPDRGD0, 0x00014001);
-	mmio_write_32(DBSC_DBPDRGA0, 0x00000006);
-	while (!(mmio_read_32(DBSC_DBPDRGD0) & BIT(0)))
-		;
-
-	if (pdqsr_ctl == 1) {
-		mmio_write_32(DBSC_DBPDRGA0, 0x000000A0);
-		mmio_write_32(DBSC_DBPDRGD0, 0x7C0002C5);
-		mmio_write_32(DBSC_DBPDRGA0, 0x000000C0);
-		mmio_write_32(DBSC_DBPDRGD0, 0x7C0002C5);
-		mmio_write_32(DBSC_DBPDRGA0, 0x000000E0);
-		mmio_write_32(DBSC_DBPDRGD0, 0x7C0002C5);
-		mmio_write_32(DBSC_DBPDRGA0, 0x00000100);
-		mmio_write_32(DBSC_DBPDRGD0, 0x7C0002C5);
-	}
-
-	/* PDR dynamic */
-	if (pdr_ctl == 1) {
-		mmio_write_32(DBSC_DBPDRGA0, 0x000000A3);
-		mmio_write_32(DBSC_DBPDRGD0, 0x00000000);
-		mmio_write_32(DBSC_DBPDRGA0, 0x000000C3);
-		mmio_write_32(DBSC_DBPDRGD0, 0x00000000);
-		mmio_write_32(DBSC_DBPDRGA0, 0x000000E3);
-		mmio_write_32(DBSC_DBPDRGD0, 0x00000000);
-		mmio_write_32(DBSC_DBPDRGA0, 0x00000103);
-		mmio_write_32(DBSC_DBPDRGD0, 0x00000000);
-	}
-
-	/*
-	 * Initial_Step8(Write Data Eye Training)
-	 */
-	mmio_write_32(DBSC_DBPDRGA0, 0x00000001);
-	mmio_write_32(DBSC_DBPDRGD0, 0x00018001);
-	mmio_write_32(DBSC_DBPDRGA0, 0x00000006);
-	while (!(mmio_read_32(DBSC_DBPDRGD0) & BIT(0)))
-		;
-
-	/*
-	 * Initial_Step3_2( DQS Gate Training )
-	 */
-	mmio_write_32(DBSC_DBPDRGA0, 0x000000A0);
-	mmio_write_32(DBSC_DBPDRGD0, 0x7C000285);
-	mmio_write_32(DBSC_DBPDRGA0, 0x000000C0);
-	mmio_write_32(DBSC_DBPDRGD0, 0x7C000285);
-	mmio_write_32(DBSC_DBPDRGA0, 0x000000E0);
-	mmio_write_32(DBSC_DBPDRGD0, 0x7C000285);
-	mmio_write_32(DBSC_DBPDRGA0, 0x00000100);
-	mmio_write_32(DBSC_DBPDRGD0, 0x7C000285);
-	mmio_write_32(DBSC_DBPDRGA0, 0x0000002C);
-	mmio_write_32(DBSC_DBPDRGD0, 0x81003087);
-	mmio_write_32(DBSC_DBPDRGA0, 0x00000001);
-	mmio_write_32(DBSC_DBPDRGD0, 0x00010401);
-	mmio_write_32(DBSC_DBPDRGA0, 0x00000006);
-	while (!(mmio_read_32(DBSC_DBPDRGD0) & BIT(0)))
-		;
-
-	for (i = 0; i < 4; i++) {
-		mmio_write_32(DBSC_DBPDRGA0, 0xB1 + i * 0x20);
-		r5 = ((mmio_read_32(DBSC_DBPDRGD0) & 0xFF00) >> 0x8);
-		mmio_write_32(DBSC_DBPDRGA0, 0xB4 + i * 0x20);
-		r6 = mmio_read_32(DBSC_DBPDRGD0) & 0xFF;
-		mmio_write_32(DBSC_DBPDRGA0, 0xB3 + i * 0x20);
-		r7 = mmio_read_32(DBSC_DBPDRGD0) & 0x7;
-		r12 = (r5 >> 0x2);
-		if (r12 < r6) {
-			mmio_write_32(DBSC_DBPDRGA0, 0xB2 + i * 0x20);
-			r2 = mmio_read_32(DBSC_DBPDRGD0) & 0xFFFFFFF8;
-			mmio_write_32(DBSC_DBPDRGA0, 0xB2 + i * 0x20);
-			mmio_write_32(DBSC_DBPDRGD0, r2 | ((r7 + 0x1) & 0x7));
-			mmio_write_32(DBSC_DBPDRGA0, 0xB0 + i * 0x20);
-			r2 = mmio_read_32(DBSC_DBPDRGD0) & 0xFFFFFF00;
-			mmio_write_32(DBSC_DBPDRGA0, 0xB0 + i * 0x20);
-			mmio_write_32(DBSC_DBPDRGD0, r2 | ((r6 - r12) & 0xFF));
-		} else {
-			mmio_write_32(DBSC_DBPDRGA0, 0xB2 + i * 0x20);
-			r2 = mmio_read_32(DBSC_DBPDRGD0) & 0xFFFFFFF8;
-			mmio_write_32(DBSC_DBPDRGA0, 0xB2 + i * 0x20);
-			mmio_write_32(DBSC_DBPDRGD0, r2 | (r7 & 0x7));
-			mmio_write_32(DBSC_DBPDRGA0, 0xB0 + i * 0x20);
-			r2 = mmio_read_32(DBSC_DBPDRGD0) & 0xFFFFFF00;
-			mmio_write_32(DBSC_DBPDRGA0, 0xB0 + i * 0x20);
-			mmio_write_32(DBSC_DBPDRGD0, r2 | ((r6 + r5 +
-						     (r5 >> 1) + r12) & 0xFF));
-		}
-	}
-
-	/*
-	 * Initial_Step5-2_7-2( Rd bit Rd eye )
-	 */
-	if (pdqsr_ctl == 0) {
-		mmio_write_32(DBSC_DBPDRGA0, 0x000000A0);
-		mmio_write_32(DBSC_DBPDRGD0, 0x7C0002C5);
-		mmio_write_32(DBSC_DBPDRGA0, 0x000000C0);
-		mmio_write_32(DBSC_DBPDRGD0, 0x7C0002C5);
-		mmio_write_32(DBSC_DBPDRGA0, 0x000000E0);
-		mmio_write_32(DBSC_DBPDRGD0, 0x7C0002C5);
-		mmio_write_32(DBSC_DBPDRGA0, 0x00000100);
-		mmio_write_32(DBSC_DBPDRGD0, 0x7C0002C5);
-	}
-
-	/* PDR always off */
-	if (pdr_ctl == 1) {
-		mmio_write_32(DBSC_DBPDRGA0, 0x000000A3);
-		mmio_write_32(DBSC_DBPDRGD0, 0x00000008);
-		mmio_write_32(DBSC_DBPDRGA0, 0x000000C3);
-		mmio_write_32(DBSC_DBPDRGD0, 0x00000008);
-		mmio_write_32(DBSC_DBPDRGA0, 0x000000E3);
-		mmio_write_32(DBSC_DBPDRGD0, 0x00000008);
-		mmio_write_32(DBSC_DBPDRGA0, 0x00000103);
-		mmio_write_32(DBSC_DBPDRGD0, 0x00000008);
-	}
-
-	mmio_write_32(DBSC_DBPDRGA0, 0x00000001);
-	mmio_write_32(DBSC_DBPDRGD0, 0x00015001);
-	mmio_write_32(DBSC_DBPDRGA0, 0x00000006);
-	while (!(mmio_read_32(DBSC_DBPDRGD0) & BIT(0)))
-		;
-
-	if (lcdl_ctl == 1) {
-		for (i = 0; i < 4; i++) {
-			mmio_write_32(DBSC_DBPDRGA0, 0xB0 + i * 0x20);
-			dqsgd_0c = mmio_read_32(DBSC_DBPDRGD0) & 0xFF;
-			mmio_write_32(DBSC_DBPDRGA0, 0xB1 + i * 0x20);
-			bdlcount_0c = (mmio_read_32(DBSC_DBPDRGD0) & 0xFF00) >>
-					8;
-			bdlcount_0c_div2 = bdlcount_0c >> 1;
-			bdlcount_0c_div4 = bdlcount_0c >> 2;
-			bdlcount_0c_div8 = bdlcount_0c >> 3;
-			bdlcount_0c_div16 = bdlcount_0c >> 4;
-
-			if (ddr_md == 0) {	/* 1584Mbps */
-				lcdl_judge1 = bdlcount_0c_div2 +
-					      bdlcount_0c_div4 +
-					      bdlcount_0c_div8;
-				lcdl_judge2 = bdlcount_0c +
-					      bdlcount_0c_div4 +
-					      bdlcount_0c_div16;
-			} else {		/* 1856Mbps */
-				lcdl_judge1 = bdlcount_0c_div2 +
-					      bdlcount_0c_div4;
-				lcdl_judge2 = bdlcount_0c +
-					      bdlcount_0c_div4;
-			}
-
-			if (dqsgd_0c <= lcdl_judge1)
-				continue;
-
-			if (dqsgd_0c <= lcdl_judge2) {
-				mmio_write_32(DBSC_DBPDRGA0, 0xB0 + i * 0x20);
-				regval = mmio_read_32(DBSC_DBPDRGD0) &
-						0xFFFFFF00;
-				mmio_write_32(DBSC_DBPDRGD0,
-					      (dqsgd_0c - bdlcount_0c_div8) |
-					      regval);
-			} else {
-				mmio_write_32(DBSC_DBPDRGA0, 0xB0 + i * 0x20);
-				regval = mmio_read_32(DBSC_DBPDRGD0) &
-						0xFFFFFF00;
-				mmio_write_32(DBSC_DBPDRGD0, regval);
-				mmio_write_32(DBSC_DBPDRGA0, 0xB2 + i * 0x20);
-				gatesl_0c = mmio_read_32(DBSC_DBPDRGD0) & 0x7;
-				mmio_write_32(DBSC_DBPDRGA0, 0xB2 + i * 0x20);
-				regval = mmio_read_32(DBSC_DBPDRGD0) &
-						0xFFFFFFF8;
-				mmio_write_32(DBSC_DBPDRGD0, regval |
-							     (gatesl_0c + 1));
-				mmio_write_32(DBSC_DBPDRGA0, 0xAF + i * 0x20);
-				regval = (mmio_read_32(DBSC_DBPDRGD0));
-				rdqsd_0c = (regval & 0xFF00) >> 8;
-				rdqsnd_0c = (regval & 0xFF0000) >> 16;
-				mmio_write_32(DBSC_DBPDRGA0, 0xAF + i * 0x20);
-				mmio_write_32(DBSC_DBPDRGD0,
-					      (regval & 0xFF0000FF) |
-					      ((rdqsd_0c +
-						bdlcount_0c_div4) << 8) |
-					      ((rdqsnd_0c +
-						bdlcount_0c_div4) << 16));
-				mmio_write_32(DBSC_DBPDRGA0, 0xAA + i * 0x20);
-				regval = (mmio_read_32(DBSC_DBPDRGD0));
-				rbd_0c[0] = (regval) & 0x1f;
-				rbd_0c[1] = (regval >> 8) & 0x1f;
-				rbd_0c[2] = (regval >> 16) & 0x1f;
-				rbd_0c[3] = (regval >> 24) & 0x1f;
-				mmio_write_32(DBSC_DBPDRGA0, 0xAA + i * 0x20);
-				regval = mmio_read_32(DBSC_DBPDRGD0) &
-					0xE0E0E0E0;
-				for (j = 0; j < 4; j++) {
-					rbd_0c[j] = rbd_0c[j] +
-						    bdlcount_0c_div4;
-					if (rbd_0c[j] > 0x1F)
-						rbd_0c[j] = 0x1F;
-					regval = regval | (rbd_0c[j] << 8 * j);
-				}
-				mmio_write_32(DBSC_DBPDRGD0, regval);
-				mmio_write_32(DBSC_DBPDRGA0, 0xAB + i * 0x20);
-				regval = (mmio_read_32(DBSC_DBPDRGD0));
-				rbd_0c[0] = (regval) & 0x1f;
-				rbd_0c[1] = (regval >> 8) & 0x1f;
-				rbd_0c[2] = (regval >> 16) & 0x1f;
-				rbd_0c[3] = (regval >> 24) & 0x1f;
-				mmio_write_32(DBSC_DBPDRGA0, 0xAB + i * 0x20);
-				regval = mmio_read_32(DBSC_DBPDRGD0) &
-					0xE0E0E0E0;
-				for (j = 0; j < 4; j++) {
-					rbd_0c[j] = rbd_0c[j] +
-						    bdlcount_0c_div4;
-					if (rbd_0c[j] > 0x1F)
-						rbd_0c[j] = 0x1F;
-					regval = regval | (rbd_0c[j] << 8 * j);
-				}
-				mmio_write_32(DBSC_DBPDRGD0, regval);
-			}
-		}
-		mmio_write_32(DBSC_DBPDRGA0, 0x2);
-		mmio_write_32(DBSC_DBPDRGD0, 0x7D81E37);
-	}
-
-	mmio_write_32(DBSC_DBPDRGA0, 0x00000003);
-	if (byp_ctl == 1)
-		mmio_write_32(DBSC_DBPDRGD0, 0x0380C720);
-	else
-		mmio_write_32(DBSC_DBPDRGD0, 0x0380C700);
-
-	mmio_write_32(DBSC_DBPDRGA0, 0x00000007);
-	while (mmio_read_32(DBSC_DBPDRGD0) & BIT(30))
-		;
-
-	mmio_write_32(DBSC_DBPDRGA0, 0x00000021);
-	mmio_write_32(DBSC_DBPDRGD0, 0x0024643E);
-
-	mmio_write_32(DBSC_DBBUS0CNF1, 0x00000010);
-	mmio_write_32(DBSC_DBCALCNF, (64000000 / REFRESH_RATE) + 0x01000000);
-	/* Select setting value in bps */
-	if (ddr_md == 0) {	/* 1584Mbps */
-		mmio_write_32(DBSC_DBRFCNF1,
-			      (REFRESH_RATE * 99 / 125) + 0x00080000);
-	} else {		/* 1856Mbps */
-		mmio_write_32(DBSC_DBRFCNF1,
-			      (REFRESH_RATE * 116 / 125) + 0x00080000);
-	}
-
-	mmio_write_32(DBSC_DBRFCNF2, 0x00010000);
-	mmio_write_32(DBSC_DBDFICUPDCNF, 0x40100001);
-	mmio_write_32(DBSC_DBRFEN, 0x00000001);
-	mmio_write_32(DBSC_DBACEN, 0x00000001);
-
-	if (pdqsr_ctl == 1) {
-		mmio_write_32(0xE67F0018, 0x00000001);
-		regval = mmio_read_32(0x40000000);
-		mmio_write_32(DBSC_DBPDRGA0, 0x00000000);
-		mmio_write_32(DBSC_DBPDRGD0, regval);
-		mmio_write_32(DBSC_DBPDRGA0, 0x000000A0);
-		mmio_write_32(DBSC_DBPDRGD0, 0x7C0002C5);
-		mmio_write_32(DBSC_DBPDRGA0, 0x000000C0);
-		mmio_write_32(DBSC_DBPDRGD0, 0x7C0002C5);
-		mmio_write_32(DBSC_DBPDRGA0, 0x000000E0);
-		mmio_write_32(DBSC_DBPDRGD0, 0x7C0002C5);
-		mmio_write_32(DBSC_DBPDRGA0, 0x00000100);
-		mmio_write_32(DBSC_DBPDRGD0, 0x7C0002C5);
-	}
-
-	/* PDR dynamic */
-	if (pdr_ctl == 1) {
-		mmio_write_32(DBSC_DBPDRGA0, 0x000000A3);
-		mmio_write_32(DBSC_DBPDRGD0, 0x00000000);
-		mmio_write_32(DBSC_DBPDRGA0, 0x000000C3);
-		mmio_write_32(DBSC_DBPDRGD0, 0x00000000);
-		mmio_write_32(DBSC_DBPDRGA0, 0x000000E3);
-		mmio_write_32(DBSC_DBPDRGD0, 0x00000000);
-		mmio_write_32(DBSC_DBPDRGA0, 0x00000103);
-		mmio_write_32(DBSC_DBPDRGD0, 0x00000000);
-	}
-
-	/*
-	 * Initial_Step9( Initial End )
-	 */
-	mmio_write_32(DBSC_DBPDLK0, 0x00000000);
-	mmio_write_32(DBSC_DBSYSCNT0, 0x00000000);
-
-#ifdef ddr_qos_init_setting /* only for non qos_init */
-	mmio_write_32(DBSC_DBSYSCNT0, 0x00001234);
-	mmio_write_32(DBSC_DBCAM0CNF1, 0x00043218);
-	mmio_write_32(DBSC_DBCAM0CNF2, 0x000000F4);
-	mmio_write_32(DBSC_DBSCHCNT0, 0x000f0037);
-	mmio_write_32(DBSC_DBSCHSZ0, 0x00000001);
-	mmio_write_32(DBSC_DBSCHRW0, 0x22421111);
-	mmio_write_32(DBSC_SCFCTST2, 0x012F1123);
-	mmio_write_32(DBSC_DBSCHQOS00, 0x00000F00);
-	mmio_write_32(DBSC_DBSCHQOS01, 0x00000B00);
-	mmio_write_32(DBSC_DBSCHQOS02, 0x00000000);
-	mmio_write_32(DBSC_DBSCHQOS03, 0x00000000);
-	mmio_write_32(DBSC_DBSCHQOS40, 0x00000300);
-	mmio_write_32(DBSC_DBSCHQOS41, 0x000002F0);
-	mmio_write_32(DBSC_DBSCHQOS42, 0x00000200);
-	mmio_write_32(DBSC_DBSCHQOS43, 0x00000100);
-	mmio_write_32(DBSC_DBSCHQOS90, 0x00000100);
-	mmio_write_32(DBSC_DBSCHQOS91, 0x000000F0);
-	mmio_write_32(DBSC_DBSCHQOS92, 0x000000A0);
-	mmio_write_32(DBSC_DBSCHQOS93, 0x00000040);
-	mmio_write_32(DBSC_DBSCHQOS130, 0x00000100);
-	mmio_write_32(DBSC_DBSCHQOS131, 0x000000F0);
-	mmio_write_32(DBSC_DBSCHQOS132, 0x000000A0);
-	mmio_write_32(DBSC_DBSCHQOS133, 0x00000040);
-	mmio_write_32(DBSC_DBSCHQOS140, 0x000000C0);
-	mmio_write_32(DBSC_DBSCHQOS141, 0x000000B0);
-	mmio_write_32(DBSC_DBSCHQOS142, 0x00000080);
-	mmio_write_32(DBSC_DBSCHQOS143, 0x00000040);
-	mmio_write_32(DBSC_DBSCHQOS150, 0x00000040);
-	mmio_write_32(DBSC_DBSCHQOS151, 0x00000030);
-	mmio_write_32(DBSC_DBSCHQOS152, 0x00000020);
-	mmio_write_32(DBSC_DBSCHQOS153, 0x00000010);
-
-	if (pdqsr_ctl == 0)
-		mmio_write_32(0xE67F0018, 0x00000001);
-
-	mmio_write_32(DBSC_DBSYSCNT0, 0x00000000);
-#endif
-
-	return 1;
-}
-
-static uint32_t recovery_from_backup_mode(uint32_t ddr_backup)
-{
-	/*
-	 * recovery_Step0(DBSC Setting 1) / same "init_ddr"
-	 */
-	uint32_t r2, r5, r6, r7, r12, i;
-	uint32_t ddr_md;
-	uint32_t err;
-	uint32_t regval, j;
-	uint32_t dqsgd_0c, bdlcount_0c, bdlcount_0c_div2, bdlcount_0c_div4;
-	uint32_t bdlcount_0c_div8, bdlcount_0c_div16;
-	uint32_t gatesl_0c, rdqsd_0c, rdqsnd_0c, rbd_0c[4];
-	uint32_t pdqsr_ctl, lcdl_ctl, lcdl_judge1, lcdl_judge2;
-	uint32_t pdr_ctl;
-	uint32_t byp_ctl;
-
-	if ((mmio_read_32(0xFFF00044) & 0x000000FF) == 0x00000000) {
-		pdqsr_ctl = 1;
-		lcdl_ctl = 1;
-		pdr_ctl = 1;
-		byp_ctl = 1;
-	} else {
-		pdqsr_ctl = 0;
-		lcdl_ctl = 0;
-		pdr_ctl = 0;
-		byp_ctl = 0;
-	}
-
-	/* Judge the DDR bit rate (ddr_md : 0 = 1584Mbps, 1 = 1856Mbps) */
-	ddr_md = (mmio_read_32(RST_MODEMR) >> 19) & BIT(0);
-
-	/* 1584Mbps setting */
-	if (ddr_md == 0) {
-		mmio_write_32(CPG_CPGWPR, 0x5A5AFFFF);
-		mmio_write_32(CPG_CPGWPCR, 0xA5A50000);
-
-		mmio_write_32(CPG_SRCR4, 0x20000000);
-
-		mmio_write_32(0xE61500DC, 0xe2200000);	/* Change to 1584Mbps */
-		while (!(mmio_read_32(CPG_PLLECR) & BIT(11)))
-			;
-
-		mmio_write_32(CPG_SRSTCLR4, 0x20000000);
-
-		mmio_write_32(CPG_CPGWPCR, 0xA5A50001);
-	}
-
-	mmio_write_32(DBSC_DBSYSCNT0, 0x00001234);
-	mmio_write_32(DBSC_DBKIND, 0x00000007);
-
-#if RCAR_DRAM_DDR3L_MEMCONF == 0
-	mmio_write_32(DBSC_DBMEMCONF00, 0x0f030a02);
-#else
-	mmio_write_32(DBSC_DBMEMCONF00, 0x10030a02);
-#endif
-
-#if RCAR_DRAM_DDR3L_MEMDUAL == 1
-	r2 = mmio_read_32(0xE6790614);
-	mmio_write_32(0xE6790614, r2 | 0x3); /* MCS1_N/MODT1 are activated. */
-#endif
-
-	mmio_write_32(DBSC_DBPHYCONF0, 0x00000001);
-
-	/* Select setting value in bps */
-	if (ddr_md == 0) {	/* 1584Mbps */
-		mmio_write_32(DBSC_DBTR0, 0x0000000B);
-		mmio_write_32(DBSC_DBTR1, 0x00000008);
-	} else {		/* 1856Mbps */
-		mmio_write_32(DBSC_DBTR0, 0x0000000D);
-		mmio_write_32(DBSC_DBTR1, 0x00000009);
-	}
-
-	mmio_write_32(DBSC_DBTR2, 0x00000000);
-
-	/* Select setting value in bps */
-	if (ddr_md == 0) {	/* 1584Mbps */
-		mmio_write_32(DBSC_DBTR3, 0x0000000B);
-		mmio_write_32(DBSC_DBTR4, 0x000B000B);
-		mmio_write_32(DBSC_DBTR5, 0x00000027);
-		mmio_write_32(DBSC_DBTR6, 0x0000001C);
-	} else {		/* 1856Mbps */
-		mmio_write_32(DBSC_DBTR3, 0x0000000D);
-		mmio_write_32(DBSC_DBTR4, 0x000D000D);
-		mmio_write_32(DBSC_DBTR5, 0x0000002D);
-		mmio_write_32(DBSC_DBTR6, 0x00000020);
-	}
-
-	mmio_write_32(DBSC_DBTR7, 0x00060006);
-
-	/* Select setting value in bps */
-	if (ddr_md == 0) {	/* 1584Mbps */
-		mmio_write_32(DBSC_DBTR8, 0x00000020);
-		mmio_write_32(DBSC_DBTR9, 0x00000006);
-		mmio_write_32(DBSC_DBTR10, 0x0000000C);
-		mmio_write_32(DBSC_DBTR11, 0x0000000A);
-		mmio_write_32(DBSC_DBTR12, 0x00120012);
-		mmio_write_32(DBSC_DBTR13, 0x000000CE);
-		mmio_write_32(DBSC_DBTR14, 0x00140005);
-		mmio_write_32(DBSC_DBTR15, 0x00050004);
-		mmio_write_32(DBSC_DBTR16, 0x071F0305);
-		mmio_write_32(DBSC_DBTR17, 0x040C0000);
-	} else {		/* 1856Mbps */
-		mmio_write_32(DBSC_DBTR8, 0x00000021);
-		mmio_write_32(DBSC_DBTR9, 0x00000007);
-		mmio_write_32(DBSC_DBTR10, 0x0000000E);
-		mmio_write_32(DBSC_DBTR11, 0x0000000C);
-		mmio_write_32(DBSC_DBTR12, 0x00140014);
-		mmio_write_32(DBSC_DBTR13, 0x000000F2);
-		mmio_write_32(DBSC_DBTR14, 0x00170006);
-		mmio_write_32(DBSC_DBTR15, 0x00060005);
-		mmio_write_32(DBSC_DBTR16, 0x09210507);
-		mmio_write_32(DBSC_DBTR17, 0x040E0000);
-	}
-
-	mmio_write_32(DBSC_DBTR18, 0x00000200);
-
-	/* Select setting value in bps */
-	if (ddr_md == 0) {	/* 1584Mbps */
-		mmio_write_32(DBSC_DBTR19, 0x01000040);
-		mmio_write_32(DBSC_DBTR20, 0x020000D6);
-	} else {		/* 1856Mbps */
-		mmio_write_32(DBSC_DBTR19, 0x0129004B);
-		mmio_write_32(DBSC_DBTR20, 0x020000FB);
-	}
-
-	mmio_write_32(DBSC_DBTR21, 0x00040004);
-	mmio_write_32(DBSC_DBBL, 0x00000000);
-	mmio_write_32(DBSC_DBODT0, 0x00000001);
-	mmio_write_32(DBSC_DBADJ0, 0x00000001);
-	mmio_write_32(DBSC_DBSYSCONF1, 0x00000002);
-	mmio_write_32(DBSC_DBDFICNT0, 0x00000010);
-	mmio_write_32(DBSC_DBBCAMDIS, 0x00000001);
-	mmio_write_32(DBSC_DBSCHRW1, 0x00000046);
-
-	/* Select setting value in bps */
-	if (ddr_md == 0) {	/* 1584Mbps */
-		mmio_write_32(DBSC_SCFCTST0, 0x0D050B03);
-		mmio_write_32(DBSC_SCFCTST1, 0x0306030C);
-	} else {		/* 1856Mbps */
-		mmio_write_32(DBSC_SCFCTST0, 0x0C050B03);
-		mmio_write_32(DBSC_SCFCTST1, 0x0305030C);
-	}
-
-	/*
-	 * recovery_Step1(PHY setting 1)
-	 */
-	mmio_write_32(DBSC_DBPDLK0, 0x0000A55A);
-	mmio_write_32(DBSC_DBCMD, 0x01840001);
-	mmio_write_32(DBSC_DBCMD, 0x0A840000);
-	mmio_write_32(DBSC_DBPDRGA0, 0x00000008);	/* DDR_PLLCR */
-	mmio_write_32(DBSC_DBPDRGD0, 0x000B8000);
-	mmio_write_32(DBSC_DBPDRGA0, 0x00000003);	/* DDR_PGCR1 */
-	if (byp_ctl == 1)
-		mmio_write_32(DBSC_DBPDRGD0, 0x0780C720);
-	else
-		mmio_write_32(DBSC_DBPDRGD0, 0x0780C700);
-
-	mmio_write_32(DBSC_DBPDRGA0, 0x00000020);	/* DDR_DXCCR */
-	mmio_write_32(DBSC_DBPDRGD0, 0x00181884);
-	mmio_write_32(DBSC_DBPDRGA0, 0x0000001A);	/* DDR_ACIOCR0 */
-	mmio_write_32(DBSC_DBPDRGD0, 0x33C03C10);
-	mmio_write_32(DBSC_DBPDRGA0, 0x00000007);
-	while (!(mmio_read_32(DBSC_DBPDRGD0) & BIT(30)))
-		;
-
-	mmio_write_32(DBSC_DBPDRGA0, 0x00000004);
-
-	/* Select setting value in bps */
-	if (ddr_md == 0) {	/* 1584Mbps */
-		mmio_write_32(DBSC_DBPDRGD0, (REFRESH_RATE * 792 / 125) -
-					     400 + 0x08B00000);
-	} else {		/* 1856Mbps */
-		mmio_write_32(DBSC_DBPDRGD0, (REFRESH_RATE * 928 / 125) -
-					     400 + 0x0A300000);
-	}
-
-	mmio_write_32(DBSC_DBPDRGA0, 0x00000022);
-	mmio_write_32(DBSC_DBPDRGD0, 0x1000040B);
-	mmio_write_32(DBSC_DBPDRGA0, 0x00000023);
-
-	/* Select setting value in bps */
-	if (ddr_md == 0)	/* 1584Mbps */
-		mmio_write_32(DBSC_DBPDRGD0, 0x2D9C0B66);
-	else			/* 1856Mbps */
-		mmio_write_32(DBSC_DBPDRGD0, 0x35A00D77);
-
-	mmio_write_32(DBSC_DBPDRGA0, 0x00000024);
-
-	/* Select setting value in bps */
-	if (ddr_md == 0)	/* 1584Mbps */
-		mmio_write_32(DBSC_DBPDRGD0, 0x2A88B400);
-	else			/* 1856Mbps */
-		mmio_write_32(DBSC_DBPDRGD0, 0x2A8A2C28);
-
-	mmio_write_32(DBSC_DBPDRGA0, 0x00000025);
-
-	/* Select setting value in bps */
-	if (ddr_md == 0)	/* 1584Mbps */
-		mmio_write_32(DBSC_DBPDRGD0, 0x30005200);
-	else			/* 1856Mbps */
-		mmio_write_32(DBSC_DBPDRGD0, 0x30005E00);
-
-	mmio_write_32(DBSC_DBPDRGA0, 0x00000026);
-
-	/* Select setting value in bps */
-	if (ddr_md == 0)	/* 1584Mbps */
-		mmio_write_32(DBSC_DBPDRGD0, 0x0014A9C9);
-	else			/* 1856Mbps */
-		mmio_write_32(DBSC_DBPDRGD0, 0x0014CB49);
-
-	mmio_write_32(DBSC_DBPDRGA0, 0x00000027);
-
-	/* Select setting value in bps */
-	if (ddr_md == 0)	/* 1584Mbps */
-		mmio_write_32(DBSC_DBPDRGD0, 0x00000D70);
-	else			/* 1856Mbps */
-		mmio_write_32(DBSC_DBPDRGD0, 0x00000F14);
-
-	mmio_write_32(DBSC_DBPDRGA0, 0x00000028);
-	mmio_write_32(DBSC_DBPDRGD0, 0x00000046);
-	mmio_write_32(DBSC_DBPDRGA0, 0x00000029);
-
-	/* Select setting value in bps */
-	if (ddr_md == 0) {	/* 1584Mbps */
-		if (REFRESH_RATE > 3900)
-			mmio_write_32(DBSC_DBPDRGD0, 0x18);	/* [7]SRT=0 */
-		else
-			mmio_write_32(DBSC_DBPDRGD0, 0x98);	/* [7]SRT=1 */
-	} else {	/* 1856Mbps */
-		if (REFRESH_RATE > 3900)
-			mmio_write_32(DBSC_DBPDRGD0, 0x20);	/* [7]SRT=0 */
-		else
-			mmio_write_32(DBSC_DBPDRGD0, 0xA0);	/* [7]SRT=1 */
-	}
-
-	mmio_write_32(DBSC_DBPDRGA0, 0x0000002C);
-	mmio_write_32(DBSC_DBPDRGD0, 0x81003047);
-	mmio_write_32(DBSC_DBPDRGA0, 0x00000091);
-	mmio_write_32(DBSC_DBPDRGD0, 0x0007BB6B);
-	mmio_write_32(DBSC_DBPDRGA0, 0x00000095);
-	mmio_write_32(DBSC_DBPDRGD0, 0x0007BBAD);
-	mmio_write_32(DBSC_DBPDRGA0, 0x00000099);
-	mmio_write_32(DBSC_DBPDRGD0, 0x0007BB6B);
-	mmio_write_32(DBSC_DBPDRGA0, 0x00000021);	/* DDR_DSGCR */
-	mmio_write_32(DBSC_DBPDRGD0, 0x0024641E);
-	mmio_write_32(DBSC_DBPDRGA0, 0x00000006);	/* DDR_PGSR0 */
-	while (!(mmio_read_32(DBSC_DBPDRGD0) & BIT(0)))
-		;
-
-	mmio_write_32(DBSC_DBPDRGA0, 0x00000001);	/* DDR_PIR */
-	mmio_write_32(DBSC_DBPDRGD0, 0x40010000);
-
-	mmio_write_32(DBSC_DBPDRGA0, 0x00000006);	/* DDR_PGSR0 */
-	while (!(mmio_read_32(DBSC_DBPDRGD0) & BIT(0)))
-		;
-
-	mmio_write_32(DBSC_DBPDRGA0, 0x00000092);	/* DDR_ZQ0DR */
-	mmio_write_32(DBSC_DBPDRGD0, 0xC2C59AB5);
-	mmio_write_32(DBSC_DBPDRGA0, 0x00000096);	/* DDR_ZQ1DR */
-	mmio_write_32(DBSC_DBPDRGD0, 0xC4285FBF);
-	mmio_write_32(DBSC_DBPDRGA0, 0x0000009A);	/* DDR_ZQ2DR */
-	mmio_write_32(DBSC_DBPDRGD0, 0xC2C59AB5);
-	mmio_write_32(DBSC_DBPDRGA0, 0x00000090);	/* DDR_ZQCR */
-
-	/* Select setting value in bps */
-	if (ddr_md == 0)	/* 1584Mbps */
-		mmio_write_32(DBSC_DBPDRGD0, 0x0C058900);
-	else			/* 1856Mbps */
-		mmio_write_32(DBSC_DBPDRGD0, 0x0C058A00);
-
-	mmio_write_32(DBSC_DBPDRGA0, 0x00000090);	/* DDR_ZQCR */
-
-	/* Select setting value in bps */
-	if (ddr_md == 0)	/* 1584Mbps */
-		mmio_write_32(DBSC_DBPDRGD0, 0x04058900);
-	else			/* 1856Mbps */
-		mmio_write_32(DBSC_DBPDRGD0, 0x04058A00);
-
-	mmio_write_32(DBSC_DBPDRGA0, 0x00000001);	/* DDR_PIR */
-	mmio_write_32(DBSC_DBPDRGD0, 0x00050001);
-
-	mmio_write_32(DBSC_DBPDRGA0, 0x00000006);	/* DDR_PGSR0 */
-	while (!(mmio_read_32(DBSC_DBPDRGD0) & BIT(0)))
-		;
-
-	/* ddr backupmode end */
-	if (ddr_backup)
-		NOTICE("BL2: [WARM_BOOT]\n");
-	else
-		NOTICE("BL2: [COLD_BOOT]\n");
-
-	err = rcar_dram_update_boot_status(ddr_backup);
-	if (err) {
-		NOTICE("BL2: [BOOT_STATUS_UPDATE_ERROR]\n");
-		return INITDRAM_ERR_I;
-	}
-
-	mmio_write_32(DBSC_DBPDRGA0, 0x00000092);	/* DDR_ZQ0DR */
-	mmio_write_32(DBSC_DBPDRGD0, 0x02C59AB5);
-	mmio_write_32(DBSC_DBPDRGA0, 0x00000096);	/* DDR_ZQ1DR */
-	mmio_write_32(DBSC_DBPDRGD0, 0x04285FBF);
-	mmio_write_32(DBSC_DBPDRGA0, 0x0000009A);	/* DDR_ZQ2DR */
-	mmio_write_32(DBSC_DBPDRGD0, 0x02C59AB5);
-
-	mmio_write_32(DBSC_DBPDRGA0, 0x00000001);	/* DDR_PIR */
-	mmio_write_32(DBSC_DBPDRGD0, 0x08000000);
-
-	mmio_write_32(DBSC_DBPDRGA0, 0x00000001);	/* DDR_PIR */
-	mmio_write_32(DBSC_DBPDRGD0, 0x00000003);
-
-	mmio_write_32(DBSC_DBPDRGA0, 0x00000006);	/* DDR_PGSR0 */
-	while (!(mmio_read_32(DBSC_DBPDRGD0) & BIT(0)))
-		;
-
-	mmio_write_32(DBSC_DBPDRGA0, 0x00000001);	/* DDR_PIR */
-	mmio_write_32(DBSC_DBPDRGD0, 0x80010000);
-
-	mmio_write_32(DBSC_DBPDRGA0, 0x00000006);	/* DDR_PGSR0 */
-	while (!(mmio_read_32(DBSC_DBPDRGD0) & BIT(0)))
-		;
-
-	mmio_write_32(DBSC_DBPDRGA0, 0x00000001);	/* DDR_PIR */
-	mmio_write_32(DBSC_DBPDRGD0, 0x00010073);
-
-	mmio_write_32(DBSC_DBPDRGA0, 0x00000006);	/* DDR_PGSR0 */
-	while (!(mmio_read_32(DBSC_DBPDRGD0) & BIT(0)))
-		;
-
-	mmio_write_32(DBSC_DBPDRGA0, 0x00000090);	/* DDR_ZQCR */
-
-	/* Select setting value in bps */
-	if (ddr_md == 0)	/* 1584Mbps */
-		mmio_write_32(DBSC_DBPDRGD0, 0x0C058900);
-	else			/* 1856Mbps */
-		mmio_write_32(DBSC_DBPDRGD0, 0x0C058A00);
-
-	mmio_write_32(DBSC_DBPDRGA0, 0x00000090);	/* DDR_ZQCR */
-
-	/* Select setting value in bps */
-	if (ddr_md == 0)	/* 1584Mbps */
-		mmio_write_32(DBSC_DBPDRGD0, 0x04058900);
-	else			/* 1856Mbps */
-		mmio_write_32(DBSC_DBPDRGD0, 0x04058A00);
-
-	mmio_write_32(DBSC_DBPDRGA0, 0x0000000C);
-	mmio_write_32(DBSC_DBPDRGD0, 0x18000040);
-
-	/*
-	 * recovery_Step2(PHY setting 2)
-	 */
-	mmio_write_32(DBSC_DBPDRGA0, 0x00000006);
-	while (!(mmio_read_32(DBSC_DBPDRGD0) & BIT(0)))
-		;
-
-	mmio_write_32(DBSC_DBPDRGA0, 0x000000A7);
-	mmio_write_32(DBSC_DBPDRGD0, 0x0D0D0D0D);
-	mmio_write_32(DBSC_DBPDRGA0, 0x000000A8);
-	mmio_write_32(DBSC_DBPDRGD0, 0x0D0D0D0D);
-	mmio_write_32(DBSC_DBPDRGA0, 0x000000A9);
-	mmio_write_32(DBSC_DBPDRGD0, 0x000D0D0D);
-	mmio_write_32(DBSC_DBPDRGA0, 0x000000C7);
-	mmio_write_32(DBSC_DBPDRGD0, 0x0D0D0D0D);
-	mmio_write_32(DBSC_DBPDRGA0, 0x000000C8);
-	mmio_write_32(DBSC_DBPDRGD0, 0x0D0D0D0D);
-	mmio_write_32(DBSC_DBPDRGA0, 0x000000C9);
-	mmio_write_32(DBSC_DBPDRGD0, 0x000D0D0D);
-	mmio_write_32(DBSC_DBPDRGA0, 0x000000E7);
-	mmio_write_32(DBSC_DBPDRGD0, 0x0D0D0D0D);
-	mmio_write_32(DBSC_DBPDRGA0, 0x000000E8);
-	mmio_write_32(DBSC_DBPDRGD0, 0x0D0D0D0D);
-	mmio_write_32(DBSC_DBPDRGA0, 0x000000E9);
-	mmio_write_32(DBSC_DBPDRGD0, 0x000D0D0D);
-	mmio_write_32(DBSC_DBPDRGA0, 0x00000107);
-	mmio_write_32(DBSC_DBPDRGD0, 0x0D0D0D0D);
-	mmio_write_32(DBSC_DBPDRGA0, 0x00000108);
-	mmio_write_32(DBSC_DBPDRGD0, 0x0D0D0D0D);
-	mmio_write_32(DBSC_DBPDRGA0, 0x00000109);
-	mmio_write_32(DBSC_DBPDRGD0, 0x000D0D0D);
-
-	mmio_write_32(DBSC_DBCALCNF, (64000000 / REFRESH_RATE) + 0x01000000);
-	mmio_write_32(DBSC_DBBUS0CNF1, 0x00000010);
-
-	/* Select setting value in bps */
-	if (ddr_md == 0) {	/* 1584Mbps */
-		mmio_write_32(DBSC_DBRFCNF1,
-			      (REFRESH_RATE * 99 / 125) + 0x00080000);
-	} else {			/* 1856Mbps */
-		mmio_write_32(DBSC_DBRFCNF1,
-			      (REFRESH_RATE * 116 / 125) + 0x00080000);
-	}
-
-	mmio_write_32(DBSC_DBRFCNF2, 0x00010000);
-	mmio_write_32(DBSC_DBRFEN, 0x00000001);
-	mmio_write_32(DBSC_DBCMD, 0x0A840001);
-	while (mmio_read_32(DBSC_DBWAIT) & BIT(0))
-		;
-
-	mmio_write_32(DBSC_DBCMD, 0x00000000);
-
-	mmio_write_32(DBSC_DBCMD, 0x04840010);
-	while (mmio_read_32(DBSC_DBWAIT) & BIT(0))
-		;
-
-	mmio_write_32(DBSC_DBPDRGA0, 0x00000006);	/* DDR_PGSR0 */
-	while (!(mmio_read_32(DBSC_DBPDRGD0) & BIT(0)))
-		;
-
-	mmio_write_32(DBSC_DBPDRGA0, 0x00000001);	/* DDR_PIR */
-	mmio_write_32(DBSC_DBPDRGD0, 0x00010701);
-
-	mmio_write_32(DBSC_DBPDRGA0, 0x00000006);	/* DDR_PGSR0 */
-	while (!(mmio_read_32(DBSC_DBPDRGD0) & BIT(0)))
-		;
-
-	for (i = 0; i < 4; i++) {
-		mmio_write_32(DBSC_DBPDRGA0, 0xB1 + i * 0x20);
-		r5 = (mmio_read_32(DBSC_DBPDRGD0) & 0xFF00) >> 0x8;
-		mmio_write_32(DBSC_DBPDRGA0, 0xB4 + i * 0x20);
-		r6 = mmio_read_32(DBSC_DBPDRGD0) & 0xFF;
-		mmio_write_32(DBSC_DBPDRGA0, 0xB3 + i * 0x20);
-		r7 = mmio_read_32(DBSC_DBPDRGD0) & 0x7;
-
-		if (r6 > 0) {
-			mmio_write_32(DBSC_DBPDRGA0, 0xB2 + i * 0x20);
-			r2 = mmio_read_32(DBSC_DBPDRGD0) & 0xFFFFFFF8;
-			mmio_write_32(DBSC_DBPDRGA0, 0xB2 + i * 0x20);
-			mmio_write_32(DBSC_DBPDRGD0, r2 | ((r7 + 0x1) & 0x7));
-			mmio_write_32(DBSC_DBPDRGA0, 0xB0 + i * 0x20);
-			r2 = mmio_read_32(DBSC_DBPDRGD0) & 0xFFFFFF00;
-			mmio_write_32(DBSC_DBPDRGA0, 0xB0 + i * 0x20);
-			mmio_write_32(DBSC_DBPDRGD0, r2 | r6);
-		} else {
-			mmio_write_32(DBSC_DBPDRGA0, 0xB2 + i * 0x20);
-			r2 = mmio_read_32(DBSC_DBPDRGD0) & 0xFFFFFFF8;
-			mmio_write_32(DBSC_DBPDRGA0, 0xB2 + i * 0x20);
-			mmio_write_32(DBSC_DBPDRGD0, r2 | r7);
-			mmio_write_32(DBSC_DBPDRGA0, 0xB0 + i * 0x20);
-			r2 = mmio_read_32(DBSC_DBPDRGD0) & 0xFFFFFF00;
-			mmio_write_32(DBSC_DBPDRGA0, 0xB0 + i * 0x20);
-			mmio_write_32(DBSC_DBPDRGD0,
-				      r2 | ((r6 + (r5 << 1)) & 0xFF));
-		}
-	}
-
-	mmio_write_32(DBSC_DBPDRGA0, 0x00000005);
-	mmio_write_32(DBSC_DBPDRGD0, 0xC1AA00C0);
-
-	if (pdqsr_ctl == 0) {
-		mmio_write_32(DBSC_DBPDRGA0, 0x000000A0);
-		mmio_write_32(DBSC_DBPDRGD0, 0x7C0002C5);
-		mmio_write_32(DBSC_DBPDRGA0, 0x000000C0);
-		mmio_write_32(DBSC_DBPDRGD0, 0x7C0002C5);
-		mmio_write_32(DBSC_DBPDRGA0, 0x000000E0);
-		mmio_write_32(DBSC_DBPDRGD0, 0x7C0002C5);
-		mmio_write_32(DBSC_DBPDRGA0, 0x00000100);
-		mmio_write_32(DBSC_DBPDRGD0, 0x7C0002C5);
-	}
-
-	/* PDR always off */
-	if (pdr_ctl == 1) {
-		mmio_write_32(DBSC_DBPDRGA0, 0x000000A3);
-		mmio_write_32(DBSC_DBPDRGD0, 0x00000008);
-		mmio_write_32(DBSC_DBPDRGA0, 0x000000C3);
-		mmio_write_32(DBSC_DBPDRGD0, 0x00000008);
-		mmio_write_32(DBSC_DBPDRGA0, 0x000000E3);
-		mmio_write_32(DBSC_DBPDRGD0, 0x00000008);
-		mmio_write_32(DBSC_DBPDRGA0, 0x00000103);
-		mmio_write_32(DBSC_DBPDRGD0, 0x00000008);
-	}
-
-	mmio_write_32(DBSC_DBPDRGA0, 0x00000001);
-	mmio_write_32(DBSC_DBPDRGD0, 0x00010801);
-	mmio_write_32(DBSC_DBPDRGA0, 0x00000006);
-	while (!(mmio_read_32(DBSC_DBPDRGD0) & BIT(0)))
-		;
-
-	mmio_write_32(DBSC_DBPDRGA0, 0x00000005);
-	mmio_write_32(DBSC_DBPDRGD0, 0xC1AA00D8);
-
-	mmio_write_32(DBSC_DBPDRGA0, 0x00000001);
-	mmio_write_32(DBSC_DBPDRGD0, 0x00011001);
-	mmio_write_32(DBSC_DBPDRGA0, 0x00000006);
-	while (!(mmio_read_32(DBSC_DBPDRGD0) & BIT(0)))
-		;
-
-	if (pdqsr_ctl == 1) {
-		mmio_write_32(DBSC_DBPDRGA0, 0x000000A0);
-		mmio_write_32(DBSC_DBPDRGD0, 0x7C0002C5);
-		mmio_write_32(DBSC_DBPDRGA0, 0x000000C0);
-		mmio_write_32(DBSC_DBPDRGD0, 0x7C0002C5);
-		mmio_write_32(DBSC_DBPDRGA0, 0x000000E0);
-		mmio_write_32(DBSC_DBPDRGD0, 0x7C0002C5);
-		mmio_write_32(DBSC_DBPDRGA0, 0x00000100);
-		mmio_write_32(DBSC_DBPDRGD0, 0x7C0002C5);
-	}
-
-	/* PDR dynamic */
-	if (pdr_ctl == 1) {
-		mmio_write_32(DBSC_DBPDRGA0, 0x000000A3);
-		mmio_write_32(DBSC_DBPDRGD0, 0x00000000);
-		mmio_write_32(DBSC_DBPDRGA0, 0x000000C3);
-		mmio_write_32(DBSC_DBPDRGD0, 0x00000000);
-		mmio_write_32(DBSC_DBPDRGA0, 0x000000E3);
-		mmio_write_32(DBSC_DBPDRGD0, 0x00000000);
-		mmio_write_32(DBSC_DBPDRGA0, 0x00000103);
-		mmio_write_32(DBSC_DBPDRGD0, 0x00000000);
-	}
-
-	mmio_write_32(DBSC_DBPDRGA0, 0x00000001);
-	mmio_write_32(DBSC_DBPDRGD0, 0x00012001);
-	mmio_write_32(DBSC_DBPDRGA0, 0x00000006);
-	while (!(mmio_read_32(DBSC_DBPDRGD0) & BIT(0)))
-		;
-
-	if (pdqsr_ctl == 1) {
-		mmio_write_32(DBSC_DBPDRGA0, 0x000000A0);
-		mmio_write_32(DBSC_DBPDRGD0, 0x7C000285);
-		mmio_write_32(DBSC_DBPDRGA0, 0x000000C0);
-		mmio_write_32(DBSC_DBPDRGD0, 0x7C000285);
-		mmio_write_32(DBSC_DBPDRGA0, 0x000000E0);
-		mmio_write_32(DBSC_DBPDRGD0, 0x7C000285);
-		mmio_write_32(DBSC_DBPDRGA0, 0x00000100);
-		mmio_write_32(DBSC_DBPDRGD0, 0x7C000285);
-	}
-
-	/* PDR always off */
-	if (pdr_ctl == 1) {
-		mmio_write_32(DBSC_DBPDRGA0, 0x000000A3);
-		mmio_write_32(DBSC_DBPDRGD0, 0x00000008);
-		mmio_write_32(DBSC_DBPDRGA0, 0x000000C3);
-		mmio_write_32(DBSC_DBPDRGD0, 0x00000008);
-		mmio_write_32(DBSC_DBPDRGA0, 0x000000E3);
-		mmio_write_32(DBSC_DBPDRGD0, 0x00000008);
-		mmio_write_32(DBSC_DBPDRGA0, 0x00000103);
-		mmio_write_32(DBSC_DBPDRGD0, 0x00000008);
-	}
-
-	mmio_write_32(DBSC_DBPDRGA0, 0x00000001);
-	mmio_write_32(DBSC_DBPDRGD0, 0x00014001);
-	mmio_write_32(DBSC_DBPDRGA0, 0x00000006);
-	while (!(mmio_read_32(DBSC_DBPDRGD0) & BIT(0)))
-		;
-
-	if (pdqsr_ctl == 1) {
-		mmio_write_32(DBSC_DBPDRGA0, 0x000000A0);
-		mmio_write_32(DBSC_DBPDRGD0, 0x7C0002C5);
-		mmio_write_32(DBSC_DBPDRGA0, 0x000000C0);
-		mmio_write_32(DBSC_DBPDRGD0, 0x7C0002C5);
-		mmio_write_32(DBSC_DBPDRGA0, 0x000000E0);
-		mmio_write_32(DBSC_DBPDRGD0, 0x7C0002C5);
-		mmio_write_32(DBSC_DBPDRGA0, 0x00000100);
-		mmio_write_32(DBSC_DBPDRGD0, 0x7C0002C5);
-	}
-
-	/* PDR dynamic */
-	if (pdr_ctl == 1) {
-		mmio_write_32(DBSC_DBPDRGA0, 0x000000A3);
-		mmio_write_32(DBSC_DBPDRGD0, 0x00000000);
-		mmio_write_32(DBSC_DBPDRGA0, 0x000000C3);
-		mmio_write_32(DBSC_DBPDRGD0, 0x00000000);
-		mmio_write_32(DBSC_DBPDRGA0, 0x000000E3);
-		mmio_write_32(DBSC_DBPDRGD0, 0x00000000);
-		mmio_write_32(DBSC_DBPDRGA0, 0x00000103);
-		mmio_write_32(DBSC_DBPDRGD0, 0x00000000);
-	}
-
-	mmio_write_32(DBSC_DBPDRGA0, 0x00000001);
-	mmio_write_32(DBSC_DBPDRGD0, 0x00018001);
-	mmio_write_32(DBSC_DBPDRGA0, 0x00000006);
-	while (!(mmio_read_32(DBSC_DBPDRGD0) & BIT(0)))
-		;
-
-	mmio_write_32(DBSC_DBPDRGA0, 0x000000A0);
-	mmio_write_32(DBSC_DBPDRGD0, 0x7C000285);
-	mmio_write_32(DBSC_DBPDRGA0, 0x000000C0);
-	mmio_write_32(DBSC_DBPDRGD0, 0x7C000285);
-	mmio_write_32(DBSC_DBPDRGA0, 0x000000E0);
-	mmio_write_32(DBSC_DBPDRGD0, 0x7C000285);
-	mmio_write_32(DBSC_DBPDRGA0, 0x00000100);
-	mmio_write_32(DBSC_DBPDRGD0, 0x7C000285);
-	mmio_write_32(DBSC_DBPDRGA0, 0x0000002C);
-	mmio_write_32(DBSC_DBPDRGD0, 0x81003087);
-	mmio_write_32(DBSC_DBPDRGA0, 0x00000001);
-	mmio_write_32(DBSC_DBPDRGD0, 0x00010401);
-	mmio_write_32(DBSC_DBPDRGA0, 0x00000006);
-	while (!(mmio_read_32(DBSC_DBPDRGD0) & BIT(0)))
-		;
-
-	for (i = 0; i < 4; i++) {
-		mmio_write_32(DBSC_DBPDRGA0, 0xB1 + i * 0x20);
-		r5 = ((mmio_read_32(DBSC_DBPDRGD0) & 0xFF00) >> 0x8);
-		mmio_write_32(DBSC_DBPDRGA0, 0xB4 + i * 0x20);
-		r6 = mmio_read_32(DBSC_DBPDRGD0) & 0xFF;
-		mmio_write_32(DBSC_DBPDRGA0, 0xB3 + i * 0x20);
-		r7 = mmio_read_32(DBSC_DBPDRGD0) & 0x7;
-		r12 = r5 >> 0x2;
-
-		if (r12 < r6) {
-			mmio_write_32(DBSC_DBPDRGA0, 0xB2 + i * 0x20);
-			r2 = mmio_read_32(DBSC_DBPDRGD0) & 0xFFFFFFF8;
-			mmio_write_32(DBSC_DBPDRGA0, 0xB2 + i * 0x20);
-			mmio_write_32(DBSC_DBPDRGD0, r2 | ((r7 + 0x1) & 0x7));
-			mmio_write_32(DBSC_DBPDRGA0, 0xB0 + i * 0x20);
-			r2 = mmio_read_32(DBSC_DBPDRGD0) & 0xFFFFFF00;
-			mmio_write_32(DBSC_DBPDRGA0, 0xB0 + i * 0x20);
-			mmio_write_32(DBSC_DBPDRGD0, r2 | ((r6 - r12) & 0xFF));
-		} else {
-			mmio_write_32(DBSC_DBPDRGA0, 0xB2 + i * 0x20);
-			r2 = mmio_read_32(DBSC_DBPDRGD0) & 0xFFFFFFF8;
-			mmio_write_32(DBSC_DBPDRGA0, 0xB2 + i * 0x20);
-			mmio_write_32(DBSC_DBPDRGD0, r2 | (r7 & 0x7));
-			mmio_write_32(DBSC_DBPDRGA0, 0xB0 + i * 0x20);
-			r2 = mmio_read_32(DBSC_DBPDRGD0) & 0xFFFFFF00;
-			mmio_write_32(DBSC_DBPDRGA0, 0xB0 + i * 0x20);
-			mmio_write_32(DBSC_DBPDRGD0,
-				      r2 |
-				      ((r6 + r5 + (r5 >> 1) + r12) & 0xFF));
-		}
-	}
-
-	if (pdqsr_ctl == 0) {
-		mmio_write_32(DBSC_DBPDRGA0, 0x000000A0);
-		mmio_write_32(DBSC_DBPDRGD0, 0x7C0002C5);
-		mmio_write_32(DBSC_DBPDRGA0, 0x000000C0);
-		mmio_write_32(DBSC_DBPDRGD0, 0x7C0002C5);
-		mmio_write_32(DBSC_DBPDRGA0, 0x000000E0);
-		mmio_write_32(DBSC_DBPDRGD0, 0x7C0002C5);
-		mmio_write_32(DBSC_DBPDRGA0, 0x00000100);
-		mmio_write_32(DBSC_DBPDRGD0, 0x7C0002C5);
-	}
-
-	/* PDR always off */
-	if (pdr_ctl == 1) {
-		mmio_write_32(DBSC_DBPDRGA0, 0x000000A3);
-		mmio_write_32(DBSC_DBPDRGD0, 0x00000008);
-		mmio_write_32(DBSC_DBPDRGA0, 0x000000C3);
-		mmio_write_32(DBSC_DBPDRGD0, 0x00000008);
-		mmio_write_32(DBSC_DBPDRGA0, 0x000000E3);
-		mmio_write_32(DBSC_DBPDRGD0, 0x00000008);
-		mmio_write_32(DBSC_DBPDRGA0, 0x00000103);
-		mmio_write_32(DBSC_DBPDRGD0, 0x00000008);
-	}
-
-	mmio_write_32(DBSC_DBPDRGA0, 0x00000001);
-	mmio_write_32(DBSC_DBPDRGD0, 0x00015001);
-	mmio_write_32(DBSC_DBPDRGA0, 0x00000006);
-	while (!(mmio_read_32(DBSC_DBPDRGD0) & BIT(0)))
-		;
-
-	if (lcdl_ctl == 1) {
-		for (i = 0; i < 4; i++) {
-			mmio_write_32(DBSC_DBPDRGA0, 0x000000B0 + i * 0x20);
-			dqsgd_0c = mmio_read_32(DBSC_DBPDRGD0) & 0x000000FF;
-			mmio_write_32(DBSC_DBPDRGA0, 0x000000B1 + i * 0x20);
-			bdlcount_0c = (mmio_read_32(DBSC_DBPDRGD0) &
-					0x0000FF00) >> 8;
-			bdlcount_0c_div2 = (bdlcount_0c >> 1);
-			bdlcount_0c_div4 = (bdlcount_0c >> 2);
-			bdlcount_0c_div8 = (bdlcount_0c >> 3);
-			bdlcount_0c_div16 = (bdlcount_0c >> 4);
-
-			if (ddr_md == 0) {	/* 1584Mbps */
-				lcdl_judge1 = bdlcount_0c_div2 +
-					      bdlcount_0c_div4 +
-					      bdlcount_0c_div8;
-				lcdl_judge2 = bdlcount_0c +
-					      bdlcount_0c_div4 +
-					      bdlcount_0c_div16;
-			} else {	/* 1856Mbps */
-				lcdl_judge1 = bdlcount_0c_div2 +
-					      bdlcount_0c_div4;
-				lcdl_judge2 = bdlcount_0c +
-					      bdlcount_0c_div4;
-			}
-
-			if (dqsgd_0c <= lcdl_judge1)
-				continue;
-
-			if (dqsgd_0c <= lcdl_judge2) {
-				mmio_write_32(DBSC_DBPDRGA0, 0xB0 + i * 0x20);
-				regval = mmio_read_32(DBSC_DBPDRGD0) &
-						0xFFFFFF00;
-				mmio_write_32(DBSC_DBPDRGD0,
-					      (dqsgd_0c - bdlcount_0c_div8) |
-					      regval);
-			} else {
-				mmio_write_32(DBSC_DBPDRGA0, 0xB0 + i * 0x20);
-				regval = mmio_read_32(DBSC_DBPDRGD0) &
-						0xFFFFFF00;
-				mmio_write_32(DBSC_DBPDRGD0, regval);
-				mmio_write_32(DBSC_DBPDRGA0, 0xB2 + i * 0x20);
-				gatesl_0c = mmio_read_32(DBSC_DBPDRGD0) & 0x7;
-				mmio_write_32(DBSC_DBPDRGA0, 0xB2 + i * 0x20);
-				regval = mmio_read_32(DBSC_DBPDRGD0) &
-						0xFFFFFFF8;
-				mmio_write_32(DBSC_DBPDRGD0,
-					      regval | (gatesl_0c + 1));
-				mmio_write_32(DBSC_DBPDRGA0, 0xAF + i * 0x20);
-				regval = mmio_read_32(DBSC_DBPDRGD0);
-				rdqsd_0c = (regval & 0xFF00) >> 8;
-				rdqsnd_0c = (regval & 0xFF0000) >> 16;
-				mmio_write_32(DBSC_DBPDRGA0, 0xAF + i * 0x20);
-				mmio_write_32(DBSC_DBPDRGD0,
-					      (regval & 0xFF0000FF) |
-					      ((rdqsd_0c +
-						bdlcount_0c_div4) << 8) |
-					      ((rdqsnd_0c +
-						bdlcount_0c_div4) << 16));
-				mmio_write_32(DBSC_DBPDRGA0, 0xAA + i * 0x20);
-				regval = (mmio_read_32(DBSC_DBPDRGD0));
-				rbd_0c[0] = (regval) & 0x1f;
-				rbd_0c[1] = (regval >>  8) & 0x1f;
-				rbd_0c[2] = (regval >> 16) & 0x1f;
-				rbd_0c[3] = (regval >> 24) & 0x1f;
-				mmio_write_32(DBSC_DBPDRGA0, 0xAA + i * 0x20);
-				regval = mmio_read_32(DBSC_DBPDRGD0) &
-						0xE0E0E0E0;
-				for (j = 0; j < 4; j++) {
-					rbd_0c[j] = rbd_0c[j] +
-						    bdlcount_0c_div4;
-					if (rbd_0c[j] > 0x1F)
-						rbd_0c[j] = 0x1F;
-					regval = regval | (rbd_0c[j] << 8 * j);
-				}
-				mmio_write_32(DBSC_DBPDRGD0, regval);
-				mmio_write_32(DBSC_DBPDRGA0, 0xAB + i * 0x20);
-				regval = (mmio_read_32(DBSC_DBPDRGD0));
-				rbd_0c[0] = regval & 0x1f;
-				rbd_0c[1] = (regval >> 8) & 0x1f;
-				rbd_0c[2] = (regval >> 16) & 0x1f;
-				rbd_0c[3] = (regval >> 24) & 0x1f;
-				mmio_write_32(DBSC_DBPDRGA0, 0xAB + i * 0x20);
-				regval = mmio_read_32(DBSC_DBPDRGD0) &
-						0xE0E0E0E0;
-				for (j = 0; j < 4; j++) {
-					rbd_0c[j] = rbd_0c[j] +
-						    bdlcount_0c_div4;
-					if (rbd_0c[j] > 0x1F)
-						rbd_0c[j] = 0x1F;
-					regval = regval | (rbd_0c[j] << 8 * j);
-				}
-				mmio_write_32(DBSC_DBPDRGD0, regval);
-			}
-		}
-		mmio_write_32(DBSC_DBPDRGA0, 0x00000002);
-		mmio_write_32(DBSC_DBPDRGD0, 0x07D81E37);
-	}
-
-	mmio_write_32(DBSC_DBPDRGA0, 0x00000003);
-	if (byp_ctl == 1)
-		mmio_write_32(DBSC_DBPDRGD0, 0x0380C720);
-	else
-		mmio_write_32(DBSC_DBPDRGD0, 0x0380C700);
-
-	mmio_write_32(DBSC_DBPDRGA0, 0x00000007);
-	while (mmio_read_32(DBSC_DBPDRGD0) & BIT(30))
-		;
-	mmio_write_32(DBSC_DBPDRGA0, 0x00000021);
-	mmio_write_32(DBSC_DBPDRGD0, 0x0024643E);
-
-	/*
-	 * recovery_Step3(DBSC Setting 2)
-	 */
-	mmio_write_32(DBSC_DBDFICUPDCNF, 0x40100001);
-	mmio_write_32(DBSC_DBACEN, 0x00000001);
-
-	if (pdqsr_ctl == 1) {
-		mmio_write_32(0xE67F0018, 0x00000001);
-		regval = mmio_read_32(0x40000000);
-		mmio_write_32(DBSC_DBPDRGA0, 0x00000000);
-		mmio_write_32(DBSC_DBPDRGD0, regval);
-		mmio_write_32(DBSC_DBPDRGA0, 0x000000A0);
-		mmio_write_32(DBSC_DBPDRGD0, 0x7C0002C5);
-		mmio_write_32(DBSC_DBPDRGA0, 0x000000C0);
-		mmio_write_32(DBSC_DBPDRGD0, 0x7C0002C5);
-		mmio_write_32(DBSC_DBPDRGA0, 0x000000E0);
-		mmio_write_32(DBSC_DBPDRGD0, 0x7C0002C5);
-		mmio_write_32(DBSC_DBPDRGA0, 0x00000100);
-		mmio_write_32(DBSC_DBPDRGD0, 0x7C0002C5);
-	}
-
-	/* PDR dynamic */
-	if (pdr_ctl == 1) {
-		mmio_write_32(DBSC_DBPDRGA0, 0x000000A3);
-		mmio_write_32(DBSC_DBPDRGD0, 0x00000000);
-		mmio_write_32(DBSC_DBPDRGA0, 0x000000C3);
-		mmio_write_32(DBSC_DBPDRGD0, 0x00000000);
-		mmio_write_32(DBSC_DBPDRGA0, 0x000000E3);
-		mmio_write_32(DBSC_DBPDRGD0, 0x00000000);
-		mmio_write_32(DBSC_DBPDRGA0, 0x00000103);
-		mmio_write_32(DBSC_DBPDRGD0, 0x00000000);
-	}
-
-	mmio_write_32(DBSC_DBPDLK0, 0x00000000);
-	mmio_write_32(DBSC_DBSYSCNT0, 0x00000000);
-
-#ifdef ddr_qos_init_setting /* only for non qos_init */
-	mmio_write_32(DBSC_DBSYSCNT0, 0x00001234);
-	mmio_write_32(DBSC_DBCAM0CNF1, 0x00043218);
-	mmio_write_32(DBSC_DBCAM0CNF2, 0x000000F4);
-	mmio_write_32(DBSC_DBSCHCNT0, 0x000f0037);
-	mmio_write_32(DBSC_DBSCHSZ0, 0x00000001);
-	mmio_write_32(DBSC_DBSCHRW0, 0x22421111);
-	mmio_write_32(DBSC_SCFCTST2, 0x012F1123);
-	mmio_write_32(DBSC_DBSCHQOS00, 0x00000F00);
-	mmio_write_32(DBSC_DBSCHQOS01, 0x00000B00);
-	mmio_write_32(DBSC_DBSCHQOS02, 0x00000000);
-	mmio_write_32(DBSC_DBSCHQOS03, 0x00000000);
-	mmio_write_32(DBSC_DBSCHQOS40, 0x00000300);
-	mmio_write_32(DBSC_DBSCHQOS41, 0x000002F0);
-	mmio_write_32(DBSC_DBSCHQOS42, 0x00000200);
-	mmio_write_32(DBSC_DBSCHQOS43, 0x00000100);
-	mmio_write_32(DBSC_DBSCHQOS90, 0x00000100);
-	mmio_write_32(DBSC_DBSCHQOS91, 0x000000F0);
-	mmio_write_32(DBSC_DBSCHQOS92, 0x000000A0);
-	mmio_write_32(DBSC_DBSCHQOS93, 0x00000040);
-	mmio_write_32(DBSC_DBSCHQOS130, 0x00000100);
-	mmio_write_32(DBSC_DBSCHQOS131, 0x000000F0);
-	mmio_write_32(DBSC_DBSCHQOS132, 0x000000A0);
-	mmio_write_32(DBSC_DBSCHQOS133, 0x00000040);
-	mmio_write_32(DBSC_DBSCHQOS140, 0x000000C0);
-	mmio_write_32(DBSC_DBSCHQOS141, 0x000000B0);
-	mmio_write_32(DBSC_DBSCHQOS142, 0x00000080);
-	mmio_write_32(DBSC_DBSCHQOS143, 0x00000040);
-	mmio_write_32(DBSC_DBSCHQOS150, 0x00000040);
-	mmio_write_32(DBSC_DBSCHQOS151, 0x00000030);
-	mmio_write_32(DBSC_DBSCHQOS152, 0x00000020);
-	mmio_write_32(DBSC_DBSCHQOS153, 0x00000010);
-
-	if (pdqsr_ctl == 0)
-		mmio_write_32(0xE67F0018, 0x00000001);
-
-	mmio_write_32(DBSC_DBSYSCNT0, 0x00000000);
-#endif
-
-	return 1;
-
-} /* recovery_from_backup_mode */
-
-/*
- * init_ddr : MD19=0,DDR3L,1584Mbps / MD19=1,DDR3L,1856Mbps
- */
-
-/*
- * DDR Initialize entry for IPL
- */
-int32_t rcar_dram_init(void)
-{
-	uint32_t dataL;
-	uint32_t failcount;
-	uint32_t md = 0;
-	uint32_t ddr = 0;
-	uint32_t ddr_backup;
-
-	md = *((volatile uint32_t*)RST_MODEMR);
-	ddr = (md & 0x00080000) >> 19;
-	if (ddr == 0x0)
-		NOTICE("BL2: DDR1584(%s)\n", RCAR_E3_DDR_VERSION);
-	else if (ddr == 0x1)
-		NOTICE("BL2: DDR1856(%s)\n", RCAR_E3_DDR_VERSION);
-
-	rcar_dram_get_boot_status(&ddr_backup);
-
-	if (ddr_backup == DRAM_BOOT_STATUS_WARM)
-		dataL = recovery_from_backup_mode(ddr_backup);	/* WARM boot */
-	else
-		dataL = init_ddr();				/* COLD boot */
-
-	if (dataL == 1)
-		failcount = 0;
-	else
-		failcount = 1;
-
-	if (failcount == 0)
-		return INITDRAM_OK;
-	else
-		return INITDRAM_NG;
-
-}
diff --git a/drivers/staging/renesas/rcar/ddr/ddr_a/ddr_init_v3m.c b/drivers/staging/renesas/rcar/ddr/ddr_a/ddr_init_v3m.c
deleted file mode 100644
index 00e1903ce..000000000
--- a/drivers/staging/renesas/rcar/ddr/ddr_a/ddr_init_v3m.c
+++ /dev/null
@@ -1,338 +0,0 @@
-/*
- * Copyright (c) 2015-2019, Renesas Electronics Corporation
- * All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#include <lib/mmio.h>
-#include <lib/utils_def.h>
-#include <stdint.h>
-#include "boot_init_dram.h"
-#include "boot_init_dram_regdef.h"
-
-static uint32_t init_ddr_v3m_1600(void)
-{
-	uint32_t i, r2, r5, r6, r7, r12;
-
-	mmio_write_32(DBSC_DBSYSCNT0, 0x00001234);
-	mmio_write_32(DBSC_DBKIND, 0x00000007);
-#if RCAR_DRAM_DDR3L_MEMCONF == 0
-	mmio_write_32(DBSC_DBMEMCONF00, 0x0f030a02); // 1GB: Eagle
-#else
-	mmio_write_32(DBSC_DBMEMCONF00, 0x10030a02); // 2GB: V3MSK
-#endif
-	mmio_write_32(DBSC_DBPHYCONF0, 0x00000001);
-	mmio_write_32(DBSC_DBTR0, 0x0000000B);
-	mmio_write_32(DBSC_DBTR1, 0x00000008);
-	mmio_write_32(DBSC_DBTR3, 0x0000000B);
-	mmio_write_32(DBSC_DBTR4, 0x000B000B);
-	mmio_write_32(DBSC_DBTR5, 0x00000027);
-	mmio_write_32(DBSC_DBTR6, 0x0000001C);
-	mmio_write_32(DBSC_DBTR7, 0x00060006);
-	mmio_write_32(DBSC_DBTR8, 0x00000020);
-	mmio_write_32(DBSC_DBTR9, 0x00000006);
-	mmio_write_32(DBSC_DBTR10, 0x0000000C);
-	mmio_write_32(DBSC_DBTR11, 0x0000000B);
-	mmio_write_32(DBSC_DBTR12, 0x00120012);
-	mmio_write_32(DBSC_DBTR13, 0x01180118);
-	mmio_write_32(DBSC_DBTR14, 0x00140005);
-	mmio_write_32(DBSC_DBTR15, 0x00050004);
-	mmio_write_32(DBSC_DBTR16, 0x071D0305);
-	mmio_write_32(DBSC_DBTR17, 0x040C0010);
-	mmio_write_32(DBSC_DBTR18, 0x00000200);
-	mmio_write_32(DBSC_DBTR19, 0x01000040);
-	mmio_write_32(DBSC_DBTR20, 0x02000120);
-	mmio_write_32(DBSC_DBTR21, 0x00040004);
-	mmio_write_32(DBSC_DBBL, 0x00000000);
-	mmio_write_32(DBSC_DBODT0, 0x00000001);
-	mmio_write_32(DBSC_DBADJ0, 0x00000001);
-	mmio_write_32(DBSC_DBCAM0CNF1, 0x00082010);
-	mmio_write_32(DBSC_DBCAM0CNF2, 0x00002000);
-	mmio_write_32(DBSC_DBSCHCNT0, 0x080f003f);
-	mmio_write_32(DBSC_DBSCHCNT1, 0x00001010);
-	mmio_write_32(DBSC_DBSCHSZ0, 0x00000001);
-	mmio_write_32(DBSC_DBSCHRW0, 0x00000200);
-	mmio_write_32(DBSC_DBSCHRW1, 0x00000040);
-	mmio_write_32(DBSC_DBSCHQOS40, 0x00000600);
-	mmio_write_32(DBSC_DBSCHQOS41, 0x00000480);
-	mmio_write_32(DBSC_DBSCHQOS42, 0x00000300);
-	mmio_write_32(DBSC_DBSCHQOS43, 0x00000180);
-	mmio_write_32(DBSC_DBSCHQOS90, 0x00000400);
-	mmio_write_32(DBSC_DBSCHQOS91, 0x00000300);
-	mmio_write_32(DBSC_DBSCHQOS92, 0x00000200);
-	mmio_write_32(DBSC_DBSCHQOS93, 0x00000100);
-	mmio_write_32(DBSC_DBSCHQOS130, 0x00000300);
-	mmio_write_32(DBSC_DBSCHQOS131, 0x00000240);
-	mmio_write_32(DBSC_DBSCHQOS132, 0x00000180);
-	mmio_write_32(DBSC_DBSCHQOS133, 0x000000c0);
-	mmio_write_32(DBSC_DBSCHQOS140, 0x00000200);
-	mmio_write_32(DBSC_DBSCHQOS141, 0x00000180);
-	mmio_write_32(DBSC_DBSCHQOS142, 0x00000100);
-	mmio_write_32(DBSC_DBSCHQOS143, 0x00000080);
-	mmio_write_32(DBSC_DBSCHQOS150, 0x00000100);
-	mmio_write_32(DBSC_DBSCHQOS151, 0x000000c0);
-	mmio_write_32(DBSC_DBSCHQOS152, 0x00000080);
-	mmio_write_32(DBSC_DBSCHQOS153, 0x00000040);
-	mmio_write_32(DBSC_DBSYSCONF1, 0x00000002);
-	mmio_write_32(DBSC_DBCAM0CNF1, 0x00040C04);
-	mmio_write_32(DBSC_DBCAM0CNF2, 0x000001c4);
-	mmio_write_32(DBSC_DBSCHSZ0, 0x00000003);
-	mmio_write_32(DBSC_DBSCHRW1, 0x001a0080);
-	mmio_write_32(DBSC_DBDFICNT0, 0x00000010);
-
-	mmio_write_32(DBSC_DBPDLK0, 0x0000A55A);
-	mmio_write_32(DBSC_DBCMD, 0x01000001);
-	mmio_write_32(DBSC_DBCMD, 0x08000000);
-	mmio_write_32(DBSC_DBPDRGA0, 0x00000001);
-	mmio_write_32(DBSC_DBPDRGD0, 0x80010000);
-	mmio_write_32(DBSC_DBPDRGA0, 0x00000006);
-	while (!(mmio_read_32(DBSC_DBPDRGD0) & BIT(0)))
-		;
-
-	mmio_write_32(DBSC_DBPDRGA0, 0x00000008);
-	mmio_write_32(DBSC_DBPDRGD0, 0x000B8000);
-	mmio_write_32(DBSC_DBPDRGA0, 0x00000090);
-	mmio_write_32(DBSC_DBPDRGD0, 0x04058904);
-	mmio_write_32(DBSC_DBPDRGA0, 0x00000091);
-	mmio_write_32(DBSC_DBPDRGD0, 0x0007BB6D);
-	mmio_write_32(DBSC_DBPDRGA0, 0x00000095);
-	mmio_write_32(DBSC_DBPDRGD0, 0x0007BB6B);
-	mmio_write_32(DBSC_DBPDRGA0, 0x00000099);
-	mmio_write_32(DBSC_DBPDRGD0, 0x0007BB6D);
-	mmio_write_32(DBSC_DBPDRGA0, 0x00000090);
-	mmio_write_32(DBSC_DBPDRGD0, 0x04058900);
-	mmio_write_32(DBSC_DBPDRGA0, 0x00000021);
-	mmio_write_32(DBSC_DBPDRGD0, 0x0024641E);
-	mmio_write_32(DBSC_DBPDRGA0, 0x00000001);
-	mmio_write_32(DBSC_DBPDRGD0, 0x00010073);
-	mmio_write_32(DBSC_DBPDRGA0, 0x00000006);
-	while (!(mmio_read_32(DBSC_DBPDRGD0) & BIT(0)))
-		;
-
-	mmio_write_32(DBSC_DBPDRGA0, 0x00000090);
-	mmio_write_32(DBSC_DBPDRGD0, 0x0C058900);
-	mmio_write_32(DBSC_DBPDRGA0, 0x00000090);
-	mmio_write_32(DBSC_DBPDRGD0, 0x04058900);
-	mmio_write_32(DBSC_DBPDRGA0, 0x00000006);
-	while (!(mmio_read_32(DBSC_DBPDRGD0) & BIT(0)))
-		;
-
-	mmio_write_32(DBSC_DBPDRGA0, 0x00000003);
-	mmio_write_32(DBSC_DBPDRGD0, 0x0780C700);
-	mmio_write_32(DBSC_DBPDRGA0, 0x00000007);
-	while (!(mmio_read_32(DBSC_DBPDRGD0) & BIT(30)))
-		;
-
-	mmio_write_32(DBSC_DBPDRGA0, 0x00000004);
-	mmio_write_32(DBSC_DBPDRGD0, 0x08C0C170);
-	mmio_write_32(DBSC_DBPDRGA0, 0x00000022);
-	mmio_write_32(DBSC_DBPDRGD0, 0x1000040B);
-	mmio_write_32(DBSC_DBPDRGA0, 0x00000023);
-	mmio_write_32(DBSC_DBPDRGD0, 0x2D9C0B66);
-	mmio_write_32(DBSC_DBPDRGA0, 0x00000024);
-	mmio_write_32(DBSC_DBPDRGD0, 0x2A88C400);
-	mmio_write_32(DBSC_DBPDRGA0, 0x00000025);
-	mmio_write_32(DBSC_DBPDRGD0, 0x30005200);
-	mmio_write_32(DBSC_DBPDRGA0, 0x00000026);
-	mmio_write_32(DBSC_DBPDRGD0, 0x0014A9C9);
-	mmio_write_32(DBSC_DBPDRGA0, 0x00000027);
-	mmio_write_32(DBSC_DBPDRGD0, 0x00000D70);
-	mmio_write_32(DBSC_DBPDRGA0, 0x00000028);
-	mmio_write_32(DBSC_DBPDRGD0, 0x00000004);
-	mmio_write_32(DBSC_DBPDRGA0, 0x00000029);
-	mmio_write_32(DBSC_DBPDRGD0, 0x00000018);
-	mmio_write_32(DBSC_DBPDRGA0, 0x0000002C);
-	mmio_write_32(DBSC_DBPDRGD0, 0x81003047);
-	mmio_write_32(DBSC_DBPDRGA0, 0x00000020);
-	mmio_write_32(DBSC_DBPDRGD0, 0x00181884);
-	mmio_write_32(DBSC_DBPDRGA0, 0x0000001A);
-	mmio_write_32(DBSC_DBPDRGD0, 0x13C03C10);
-	mmio_write_32(DBSC_DBPDRGA0, 0x00000006);
-	while (!(mmio_read_32(DBSC_DBPDRGD0) & BIT(0)))
-		;
-
-	mmio_write_32(DBSC_DBPDRGA0, 0x000000A7);
-	mmio_write_32(DBSC_DBPDRGD0, 0x0D0D0D0D);
-	mmio_write_32(DBSC_DBPDRGA0, 0x000000A8);
-	mmio_write_32(DBSC_DBPDRGD0, 0x0D0D0D0D);
-	mmio_write_32(DBSC_DBPDRGA0, 0x000000A9);
-	mmio_write_32(DBSC_DBPDRGD0, 0x000D0D0D);
-	mmio_write_32(DBSC_DBPDRGA0, 0x000000C7);
-	mmio_write_32(DBSC_DBPDRGD0, 0x0D0D0D0D);
-	mmio_write_32(DBSC_DBPDRGA0, 0x000000C8);
-	mmio_write_32(DBSC_DBPDRGD0, 0x0D0D0D0D);
-	mmio_write_32(DBSC_DBPDRGA0, 0x000000C9);
-	mmio_write_32(DBSC_DBPDRGD0, 0x000D0D0D);
-	mmio_write_32(DBSC_DBPDRGA0, 0x000000E7);
-	mmio_write_32(DBSC_DBPDRGD0, 0x0D0D0D0D);
-	mmio_write_32(DBSC_DBPDRGA0, 0x000000E8);
-	mmio_write_32(DBSC_DBPDRGD0, 0x0D0D0D0D);
-	mmio_write_32(DBSC_DBPDRGA0, 0x000000E9);
-	mmio_write_32(DBSC_DBPDRGD0, 0x000D0D0D);
-	mmio_write_32(DBSC_DBPDRGA0, 0x00000107);
-	mmio_write_32(DBSC_DBPDRGD0, 0x0D0D0D0D);
-	mmio_write_32(DBSC_DBPDRGA0, 0x00000108);
-	mmio_write_32(DBSC_DBPDRGD0, 0x0D0D0D0D);
-	mmio_write_32(DBSC_DBPDRGA0, 0x00000109);
-	mmio_write_32(DBSC_DBPDRGD0, 0x000D0D0D);
-	mmio_write_32(DBSC_DBPDRGA0, 0x00000001);
-	mmio_write_32(DBSC_DBPDRGD0, 0x00010181);
-	mmio_write_32(DBSC_DBCMD, 0x08000001);
-	mmio_write_32(DBSC_DBPDRGA0, 0x00000006);
-	while (!(mmio_read_32(DBSC_DBPDRGD0) & BIT(0)))
-		;
-
-	mmio_write_32(DBSC_DBPDRGA0, 0x00000001);
-	mmio_write_32(DBSC_DBPDRGD0, 0x00010601);
-	mmio_write_32(DBSC_DBPDRGA0, 0x00000006);
-	while (!(mmio_read_32(DBSC_DBPDRGD0) & BIT(0)))
-		;
-
-	for (i = 0; i < 4; i++) {
-		mmio_write_32(DBSC_DBPDRGA0, 0xB1 + i * 0x20);
-		r5 = (mmio_read_32(DBSC_DBPDRGD0) & 0xFF00) >> 8;
-		mmio_write_32(DBSC_DBPDRGA0, 0xB4 + i * 0x20);
-		r6 = mmio_read_32(DBSC_DBPDRGD0) & 0xFF;
-		mmio_write_32(DBSC_DBPDRGA0, 0xB3 + i * 0x20);
-		r7 = mmio_read_32(DBSC_DBPDRGD0) & 0x7;
-
-		if (r6 > 0) {
-			mmio_write_32(DBSC_DBPDRGA0, 0xB2 + i * 0x20);
-			r2 = (mmio_read_32(DBSC_DBPDRGD0) & 0xFFFFFFF8);
-
-			mmio_write_32(DBSC_DBPDRGA0, 0xB2 + i * 0x20);
-			mmio_write_32(DBSC_DBPDRGD0, ((r7 + 1) & 0x7) | r2);
-			mmio_write_32(DBSC_DBPDRGA0, 0xB0 + i * 0x20);
-			r2 = (mmio_read_32(DBSC_DBPDRGD0) & 0xFFFFFF00);
-			mmio_write_32(DBSC_DBPDRGA0, 0xB0 + i * 0x20);
-			mmio_write_32(DBSC_DBPDRGD0, r2 | r6);
-		} else {
-			mmio_write_32(DBSC_DBPDRGA0, 0xB2 + i * 0x20);
-			r2 = (mmio_read_32(DBSC_DBPDRGD0) & 0xFFFFFFF8);
-			mmio_write_32(DBSC_DBPDRGA0, 0xB2 + i * 0x20);
-			mmio_write_32(DBSC_DBPDRGD0, r2 | r7);
-
-			mmio_write_32(DBSC_DBPDRGA0, 0xB0 + i * 0x20);
-			r2 = (mmio_read_32(DBSC_DBPDRGD0) & 0xFFFFFF00);
-			mmio_write_32(DBSC_DBPDRGA0, 0xB0 + i * 0x20);
-			mmio_write_32(DBSC_DBPDRGD0, r2 |
-						     (((r5 << 1) + r6) & 0xFF));
-		}
-	}
-
-	mmio_write_32(DBSC_DBPDRGA0, 0x00000005);
-	mmio_write_32(DBSC_DBPDRGD0, 0xC1AA00A0);
-	mmio_write_32(DBSC_DBPDRGA0, 0x000000A0);
-	mmio_write_32(DBSC_DBPDRGD0, 0x7C0002C5);
-	mmio_write_32(DBSC_DBPDRGA0, 0x000000C0);
-	mmio_write_32(DBSC_DBPDRGD0, 0x7C0002C5);
-	mmio_write_32(DBSC_DBPDRGA0, 0x000000E0);
-	mmio_write_32(DBSC_DBPDRGD0, 0x7C0002C5);
-	mmio_write_32(DBSC_DBPDRGA0, 0x00000100);
-	mmio_write_32(DBSC_DBPDRGD0, 0x7C0002C5);
-	mmio_write_32(DBSC_DBPDRGA0, 0x00000001);
-	mmio_write_32(DBSC_DBPDRGD0, 0x00010801);
-	mmio_write_32(DBSC_DBPDRGA0, 0x00000006);
-	while (!(mmio_read_32(DBSC_DBPDRGD0) & BIT(0)))
-		;
-
-	mmio_write_32(DBSC_DBPDRGA0, 0x00000005);
-	mmio_write_32(DBSC_DBPDRGD0, 0xC1AA00B8);
-	mmio_write_32(DBSC_DBPDRGA0, 0x00000001);
-	mmio_write_32(DBSC_DBPDRGD0, 0x0001F001);
-	mmio_write_32(DBSC_DBPDRGA0, 0x00000006);
-	while (!(mmio_read_32(DBSC_DBPDRGD0) & BIT(0)))
-		;
-
-	mmio_write_32(DBSC_DBPDRGA0, 0x000000A0);
-	mmio_write_32(DBSC_DBPDRGD0, 0x7C000285);
-	mmio_write_32(DBSC_DBPDRGA0, 0x000000C0);
-	mmio_write_32(DBSC_DBPDRGD0, 0x7C000285);
-	mmio_write_32(DBSC_DBPDRGA0, 0x000000E0);
-	mmio_write_32(DBSC_DBPDRGD0, 0x7C000285);
-	mmio_write_32(DBSC_DBPDRGA0, 0x00000100);
-	mmio_write_32(DBSC_DBPDRGD0, 0x7C000285);
-	mmio_write_32(DBSC_DBPDRGA0, 0x0000002C);
-	mmio_write_32(DBSC_DBPDRGD0, 0x81003087);
-	mmio_write_32(DBSC_DBPDRGA0, 0x00000001);
-	mmio_write_32(DBSC_DBPDRGD0, 0x00010401);
-	mmio_write_32(DBSC_DBPDRGA0, 0x00000006);
-	while (!(mmio_read_32(DBSC_DBPDRGD0) & BIT(0)))
-		;
-
-	for (i = 0; i < 4; i++) {
-		mmio_write_32(DBSC_DBPDRGA0, 0xB1 + i * 0x20);
-		r5 = (mmio_read_32(DBSC_DBPDRGD0) & 0xFF00) >> 8;
-		mmio_write_32(DBSC_DBPDRGA0, 0xB4 + i * 0x20);
-		r6 = (mmio_read_32(DBSC_DBPDRGD0) & 0xFF);
-
-		mmio_write_32(DBSC_DBPDRGA0, 0xB3 + i * 0x20);
-		r7 = (mmio_read_32(DBSC_DBPDRGD0) & 0x7);
-		r12 = (r5 >> 2);
-		if (r6 - r12 > 0) {
-			mmio_write_32(DBSC_DBPDRGA0, 0xB2 + i * 0x20);
-			r2 = (mmio_read_32(DBSC_DBPDRGD0) & 0xFFFFFFF8);
-
-			mmio_write_32(DBSC_DBPDRGA0, 0xB2 + i * 0x20);
-			mmio_write_32(DBSC_DBPDRGD0, ((r7 + 1) & 0x7) | r2);
-			mmio_write_32(DBSC_DBPDRGA0, 0xB0 + i * 0x20);
-			r2 = (mmio_read_32(DBSC_DBPDRGD0) & 0xFFFFFF00);
-
-			mmio_write_32(DBSC_DBPDRGA0, 0xB0 + i * 0x20);
-			mmio_write_32(DBSC_DBPDRGD0, ((r6 - r12) & 0xFF) | r2);
-		} else {
-			mmio_write_32(DBSC_DBPDRGA0, 0xB2 + i * 0x20);
-			r2 = (mmio_read_32(DBSC_DBPDRGD0) & 0xFFFFFFF8);
-			mmio_write_32(DBSC_DBPDRGA0, 0xB2 + i * 0x20);
-			mmio_write_32(DBSC_DBPDRGD0, (r7 & 0x7) | r2);
-			mmio_write_32(DBSC_DBPDRGA0, 0xB0 + i * 0x20);
-			r2 = (mmio_read_32(DBSC_DBPDRGD0) & 0xFFFFFF00);
-			mmio_write_32(DBSC_DBPDRGA0, 0xB0 + i * 0x20);
-			mmio_write_32(DBSC_DBPDRGD0, r2 |
-						     ((r6 + r5 +
-						      (r5 >> 1) + r12) & 0xFF));
-		}
-	}
-
-	mmio_write_32(DBSC_DBPDRGA0, 0x000000A0);
-	mmio_write_32(DBSC_DBPDRGD0, 0x7C0002C5);
-	mmio_write_32(DBSC_DBPDRGA0, 0x000000C0);
-	mmio_write_32(DBSC_DBPDRGD0, 0x7C0002C5);
-	mmio_write_32(DBSC_DBPDRGA0, 0x000000E0);
-	mmio_write_32(DBSC_DBPDRGD0, 0x7C0002C5);
-	mmio_write_32(DBSC_DBPDRGA0, 0x00000100);
-	mmio_write_32(DBSC_DBPDRGD0, 0x7C0002C5);
-	mmio_write_32(DBSC_DBPDRGA0, 0x00000001);
-	mmio_write_32(DBSC_DBPDRGD0, 0x00015001);
-	mmio_write_32(DBSC_DBPDRGA0, 0x00000006);
-	while (!(mmio_read_32(DBSC_DBPDRGD0) & BIT(0)))
-		;
-
-	mmio_write_32(DBSC_DBPDRGA0, 0x00000003);
-	mmio_write_32(DBSC_DBPDRGD0, 0x0380C700);
-	mmio_write_32(DBSC_DBPDRGA0, 0x00000007);
-	while (mmio_read_32(DBSC_DBPDRGD0) & BIT(30))
-		;
-	mmio_write_32(DBSC_DBPDRGA0, 0x00000021);
-	mmio_write_32(DBSC_DBPDRGD0, 0x0024643E);
-
-	mmio_write_32(DBSC_DBBUS0CNF1, 0x00000000);
-	mmio_write_32(DBSC_DBBUS0CNF0, 0x00010001);
-	mmio_write_32(DBSC_DBCALCNF, 0x0100200E);
-	mmio_write_32(DBSC_DBRFCNF1, 0x00081860);
-	mmio_write_32(DBSC_DBRFCNF2, 0x00010000);
-	mmio_write_32(DBSC_DBDFICUPDCNF, 0x40100001);
-	mmio_write_32(DBSC_DBRFEN, 0x00000001);
-	mmio_write_32(DBSC_DBACEN, 0x00000001);
-	mmio_write_32(DBSC_DBPDLK0, 0x00000000);
-	mmio_write_32(0xE67F0024, 0x00000001);
-	mmio_write_32(DBSC_DBSYSCNT0, 0x00000000);
-
-	return INITDRAM_OK;
-}
-
-int32_t rcar_dram_init(void)
-{
-	return init_ddr_v3m_1600();
-}
diff --git a/drivers/staging/renesas/rcar/ddr/ddr_b/init_dram_tbl_h3.h b/drivers/staging/renesas/rcar/ddr/ddr_b/init_dram_tbl_h3.h
deleted file mode 100644
index 6fa9ab99d..000000000
--- a/drivers/staging/renesas/rcar/ddr/ddr_b/init_dram_tbl_h3.h
+++ /dev/null
@@ -1,440 +0,0 @@
-/*
- * Copyright (c) 2015-2019, Renesas Electronics Corporation. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#define DDR_PHY_SLICE_REGSET_OFS_H3  0x0400
-#define DDR_PHY_ADR_V_REGSET_OFS_H3  0x0600
-#define DDR_PHY_ADR_I_REGSET_OFS_H3  0x0680
-#define DDR_PHY_ADR_G_REGSET_OFS_H3  0x0700
-#define DDR_PI_REGSET_OFS_H3         0x0200
-
-#define DDR_PHY_SLICE_REGSET_SIZE_H3 0x80
-#define DDR_PHY_ADR_V_REGSET_SIZE_H3 0x80
-#define DDR_PHY_ADR_I_REGSET_SIZE_H3 0x80
-#define DDR_PHY_ADR_G_REGSET_SIZE_H3 0x80
-#define DDR_PI_REGSET_SIZE_H3        0x100
-
-#define DDR_PHY_SLICE_REGSET_NUM_H3  88
-#define DDR_PHY_ADR_V_REGSET_NUM_H3  37
-#define DDR_PHY_ADR_I_REGSET_NUM_H3  37
-#define DDR_PHY_ADR_G_REGSET_NUM_H3  59
-#define DDR_PI_REGSET_NUM_H3         181
-
-static const uint32_t DDR_PHY_SLICE_REGSET_H3[DDR_PHY_SLICE_REGSET_NUM_H3] = {
-/*0400*/ 0x000004f0,
-/*0401*/ 0x00000000,
-/*0402*/ 0x00000000,
-/*0403*/ 0x00000100,
-/*0404*/ 0x01003c0c,
-/*0405*/ 0x02003c0c,
-/*0406*/ 0x00010300,
-/*0407*/ 0x04000100,
-/*0408*/ 0x00000300,
-/*0409*/ 0x000700c0,
-/*040a*/ 0x00b00201,
-/*040b*/ 0x00000020,
-/*040c*/ 0x00000000,
-/*040d*/ 0x00000000,
-/*040e*/ 0x00000000,
-/*040f*/ 0x00000000,
-/*0410*/ 0x00000000,
-/*0411*/ 0x00000000,
-/*0412*/ 0x00000000,
-/*0413*/ 0x09000000,
-/*0414*/ 0x04080000,
-/*0415*/ 0x04080400,
-/*0416*/ 0x00000000,
-/*0417*/ 0x32103210,
-/*0418*/ 0x00800708,
-/*0419*/ 0x000f000c,
-/*041a*/ 0x00000100,
-/*041b*/ 0x55aa55aa,
-/*041c*/ 0x33cc33cc,
-/*041d*/ 0x0ff00ff0,
-/*041e*/ 0x0f0ff0f0,
-/*041f*/ 0x00008e38,
-/*0420*/ 0x76543210,
-/*0421*/ 0x00000001,
-/*0422*/ 0x00000000,
-/*0423*/ 0x00000000,
-/*0424*/ 0x00000000,
-/*0425*/ 0x00000000,
-/*0426*/ 0x00000000,
-/*0427*/ 0x00000000,
-/*0428*/ 0x00000000,
-/*0429*/ 0x00000000,
-/*042a*/ 0x00000000,
-/*042b*/ 0x00000000,
-/*042c*/ 0x00000000,
-/*042d*/ 0x00000000,
-/*042e*/ 0x00000000,
-/*042f*/ 0x00000000,
-/*0430*/ 0x00000000,
-/*0431*/ 0x00000000,
-/*0432*/ 0x00000000,
-/*0433*/ 0x00200000,
-/*0434*/ 0x08200820,
-/*0435*/ 0x08200820,
-/*0436*/ 0x08200820,
-/*0437*/ 0x08200820,
-/*0438*/ 0x08200820,
-/*0439*/ 0x00000820,
-/*043a*/ 0x03000300,
-/*043b*/ 0x03000300,
-/*043c*/ 0x03000300,
-/*043d*/ 0x03000300,
-/*043e*/ 0x00000300,
-/*043f*/ 0x00000000,
-/*0440*/ 0x00000000,
-/*0441*/ 0x00000000,
-/*0442*/ 0x00000000,
-/*0443*/ 0x00a000a0,
-/*0444*/ 0x00a000a0,
-/*0445*/ 0x00a000a0,
-/*0446*/ 0x00a000a0,
-/*0447*/ 0x00a000a0,
-/*0448*/ 0x00a000a0,
-/*0449*/ 0x00a000a0,
-/*044a*/ 0x00a000a0,
-/*044b*/ 0x00a000a0,
-/*044c*/ 0x01040109,
-/*044d*/ 0x00000200,
-/*044e*/ 0x01000000,
-/*044f*/ 0x00000200,
-/*0450*/ 0x4041a141,
-/*0451*/ 0xc00141a0,
-/*0452*/ 0x0e0100c0,
-/*0453*/ 0x0010000c,
-/*0454*/ 0x0c064208,
-/*0455*/ 0x000f0c18,
-/*0456*/ 0x00e00140,
-/*0457*/ 0x00000c20
-};
-
-static const uint32_t DDR_PHY_ADR_V_REGSET_H3[DDR_PHY_ADR_V_REGSET_NUM_H3] = {
-/*0600*/ 0x00000000,
-/*0601*/ 0x00000000,
-/*0602*/ 0x00000000,
-/*0603*/ 0x00000000,
-/*0604*/ 0x00000000,
-/*0605*/ 0x00000000,
-/*0606*/ 0x00000002,
-/*0607*/ 0x00000000,
-/*0608*/ 0x00000000,
-/*0609*/ 0x00000000,
-/*060a*/ 0x00400320,
-/*060b*/ 0x00000040,
-/*060c*/ 0x00dcba98,
-/*060d*/ 0x00000000,
-/*060e*/ 0x00dcba98,
-/*060f*/ 0x01000000,
-/*0610*/ 0x00020003,
-/*0611*/ 0x00000000,
-/*0612*/ 0x00000000,
-/*0613*/ 0x00000000,
-/*0614*/ 0x00002a01,
-/*0615*/ 0x00000015,
-/*0616*/ 0x00000015,
-/*0617*/ 0x0000002a,
-/*0618*/ 0x00000033,
-/*0619*/ 0x0000000c,
-/*061a*/ 0x0000000c,
-/*061b*/ 0x00000033,
-/*061c*/ 0x00418820,
-/*061d*/ 0x003f0000,
-/*061e*/ 0x0000003f,
-/*061f*/ 0x0002006e,
-/*0620*/ 0x02000200,
-/*0621*/ 0x02000200,
-/*0622*/ 0x00000200,
-/*0623*/ 0x42080010,
-/*0624*/ 0x00000003
-};
-
-static const uint32_t DDR_PHY_ADR_I_REGSET_H3[DDR_PHY_ADR_I_REGSET_NUM_H3] = {
-/*0680*/ 0x04040404,
-/*0681*/ 0x00000404,
-/*0682*/ 0x00000000,
-/*0683*/ 0x00000000,
-/*0684*/ 0x00000000,
-/*0685*/ 0x00000000,
-/*0686*/ 0x00000002,
-/*0687*/ 0x00000000,
-/*0688*/ 0x00000000,
-/*0689*/ 0x00000000,
-/*068a*/ 0x00400320,
-/*068b*/ 0x00000040,
-/*068c*/ 0x00000000,
-/*068d*/ 0x00000000,
-/*068e*/ 0x00000000,
-/*068f*/ 0x01000000,
-/*0690*/ 0x00020003,
-/*0691*/ 0x00000000,
-/*0692*/ 0x00000000,
-/*0693*/ 0x00000000,
-/*0694*/ 0x00002a01,
-/*0695*/ 0x00000015,
-/*0696*/ 0x00000015,
-/*0697*/ 0x0000002a,
-/*0698*/ 0x00000033,
-/*0699*/ 0x0000000c,
-/*069a*/ 0x0000000c,
-/*069b*/ 0x00000033,
-/*069c*/ 0x00000000,
-/*069d*/ 0x00000000,
-/*069e*/ 0x00000000,
-/*069f*/ 0x0002006e,
-/*06a0*/ 0x02000200,
-/*06a1*/ 0x02000200,
-/*06a2*/ 0x00000200,
-/*06a3*/ 0x42080010,
-/*06a4*/ 0x00000003
-};
-
-static const uint32_t DDR_PHY_ADR_G_REGSET_H3[DDR_PHY_ADR_G_REGSET_NUM_H3] = {
-/*0700*/ 0x00000001,
-/*0701*/ 0x00000000,
-/*0702*/ 0x00000005,
-/*0703*/ 0x04000f00,
-/*0704*/ 0x00020080,
-/*0705*/ 0x00020055,
-/*0706*/ 0x00000000,
-/*0707*/ 0x00000000,
-/*0708*/ 0x00000000,
-/*0709*/ 0x00000050,
-/*070a*/ 0x00000000,
-/*070b*/ 0x01010100,
-/*070c*/ 0x00000200,
-/*070d*/ 0x00001102,
-/*070e*/ 0x00000000,
-/*070f*/ 0x000f1f00,
-/*0710*/ 0x0f1f0f1f,
-/*0711*/ 0x0f1f0f1f,
-/*0712*/ 0x00020003,
-/*0713*/ 0x02000200,
-/*0714*/ 0x00000200,
-/*0715*/ 0x00001102,
-/*0716*/ 0x00000064,
-/*0717*/ 0x00000000,
-/*0718*/ 0x00000000,
-/*0719*/ 0x00000502,
-/*071a*/ 0x027f6e00,
-/*071b*/ 0x007f007f,
-/*071c*/ 0x00007f3c,
-/*071d*/ 0x00047f6e,
-/*071e*/ 0x0003154f,
-/*071f*/ 0x0001154f,
-/*0720*/ 0x0001154f,
-/*0721*/ 0x0001154f,
-/*0722*/ 0x0001154f,
-/*0723*/ 0x00003fee,
-/*0724*/ 0x0001154f,
-/*0725*/ 0x00003fee,
-/*0726*/ 0x0001154f,
-/*0727*/ 0x00007f3c,
-/*0728*/ 0x0001154f,
-/*0729*/ 0x00000000,
-/*072a*/ 0x00000000,
-/*072b*/ 0x00000000,
-/*072c*/ 0x65000000,
-/*072d*/ 0x00000000,
-/*072e*/ 0x00000000,
-/*072f*/ 0x00000201,
-/*0730*/ 0x00000000,
-/*0731*/ 0x00000000,
-/*0732*/ 0x00000000,
-/*0733*/ 0x00000000,
-/*0734*/ 0x00000000,
-/*0735*/ 0x00000000,
-/*0736*/ 0x00000000,
-/*0737*/ 0x00000000,
-/*0738*/ 0x00000000,
-/*0739*/ 0x00000000,
-/*073a*/ 0x00000000
-};
-
-static const uint32_t DDR_PI_REGSET_H3[DDR_PI_REGSET_NUM_H3] = {
-/*0200*/ 0x00000b00,
-/*0201*/ 0x00000100,
-/*0202*/ 0x00000000,
-/*0203*/ 0x0000ffff,
-/*0204*/ 0x00000000,
-/*0205*/ 0x0000ffff,
-/*0206*/ 0x00000000,
-/*0207*/ 0x304cffff,
-/*0208*/ 0x00000200,
-/*0209*/ 0x00000200,
-/*020a*/ 0x00000200,
-/*020b*/ 0x00000200,
-/*020c*/ 0x0000304c,
-/*020d*/ 0x00000200,
-/*020e*/ 0x00000200,
-/*020f*/ 0x00000200,
-/*0210*/ 0x00000200,
-/*0211*/ 0x0000304c,
-/*0212*/ 0x00000200,
-/*0213*/ 0x00000200,
-/*0214*/ 0x00000200,
-/*0215*/ 0x00000200,
-/*0216*/ 0x00010000,
-/*0217*/ 0x00000003,
-/*0218*/ 0x01000001,
-/*0219*/ 0x00000000,
-/*021a*/ 0x00000000,
-/*021b*/ 0x00000000,
-/*021c*/ 0x00000000,
-/*021d*/ 0x00000000,
-/*021e*/ 0x00000000,
-/*021f*/ 0x00000000,
-/*0220*/ 0x00000000,
-/*0221*/ 0x00000000,
-/*0222*/ 0x00000000,
-/*0223*/ 0x00000000,
-/*0224*/ 0x00000000,
-/*0225*/ 0x00000000,
-/*0226*/ 0x00000000,
-/*0227*/ 0x00000000,
-/*0228*/ 0x00000000,
-/*0229*/ 0x0f000101,
-/*022a*/ 0x08492d25,
-/*022b*/ 0x500e0c04,
-/*022c*/ 0x0002500e,
-/*022d*/ 0x00460003,
-/*022e*/ 0x182600cf,
-/*022f*/ 0x182600cf,
-/*0230*/ 0x00000005,
-/*0231*/ 0x00000000,
-/*0232*/ 0x00000000,
-/*0233*/ 0x00000000,
-/*0234*/ 0x00000000,
-/*0235*/ 0x00000000,
-/*0236*/ 0x00000000,
-/*0237*/ 0x00000000,
-/*0238*/ 0x01000000,
-/*0239*/ 0x00040404,
-/*023a*/ 0x01280a00,
-/*023b*/ 0x00000000,
-/*023c*/ 0x000f0000,
-/*023d*/ 0x00001803,
-/*023e*/ 0x00000000,
-/*023f*/ 0x00000000,
-/*0240*/ 0x00060002,
-/*0241*/ 0x00010001,
-/*0242*/ 0x01000101,
-/*0243*/ 0x04020201,
-/*0244*/ 0x00080804,
-/*0245*/ 0x00000000,
-/*0246*/ 0x08030000,
-/*0247*/ 0x15150408,
-/*0248*/ 0x00000000,
-/*0249*/ 0x00000000,
-/*024a*/ 0x00000000,
-/*024b*/ 0x001e0f0f,
-/*024c*/ 0x00000000,
-/*024d*/ 0x01000300,
-/*024e*/ 0x00000000,
-/*024f*/ 0x00000000,
-/*0250*/ 0x01000000,
-/*0251*/ 0x00010101,
-/*0252*/ 0x000e0e0e,
-/*0253*/ 0x000c0c0c,
-/*0254*/ 0x02060601,
-/*0255*/ 0x00000000,
-/*0256*/ 0x00000003,
-/*0257*/ 0x00181703,
-/*0258*/ 0x00280006,
-/*0259*/ 0x00280016,
-/*025a*/ 0x00000016,
-/*025b*/ 0x00000000,
-/*025c*/ 0x00000000,
-/*025d*/ 0x00000000,
-/*025e*/ 0x140a0000,
-/*025f*/ 0x0005010a,
-/*0260*/ 0x03018d03,
-/*0261*/ 0x000a018d,
-/*0262*/ 0x00060100,
-/*0263*/ 0x01000006,
-/*0264*/ 0x018e018e,
-/*0265*/ 0x018e0100,
-/*0266*/ 0x1111018e,
-/*0267*/ 0x10010204,
-/*0268*/ 0x09090650,
-/*0269*/ 0x20110202,
-/*026a*/ 0x00201000,
-/*026b*/ 0x00201000,
-/*026c*/ 0x04041000,
-/*026d*/ 0x18020100,
-/*026e*/ 0x00010118,
-/*026f*/ 0x004b004a,
-/*0270*/ 0x050f0000,
-/*0271*/ 0x0c01021e,
-/*0272*/ 0x34000000,
-/*0273*/ 0x00000000,
-/*0274*/ 0x00000000,
-/*0275*/ 0x00000000,
-/*0276*/ 0x312ed400,
-/*0277*/ 0xd4111132,
-/*0278*/ 0x1132312e,
-/*0279*/ 0x312ed411,
-/*027a*/ 0x00111132,
-/*027b*/ 0x32312ed4,
-/*027c*/ 0x2ed41111,
-/*027d*/ 0x11113231,
-/*027e*/ 0x32312ed4,
-/*027f*/ 0xd4001111,
-/*0280*/ 0x1132312e,
-/*0281*/ 0x312ed411,
-/*0282*/ 0xd4111132,
-/*0283*/ 0x1132312e,
-/*0284*/ 0x2ed40011,
-/*0285*/ 0x11113231,
-/*0286*/ 0x32312ed4,
-/*0287*/ 0x2ed41111,
-/*0288*/ 0x11113231,
-/*0289*/ 0x00020000,
-/*028a*/ 0x018d018d,
-/*028b*/ 0x0c08018d,
-/*028c*/ 0x1f121d22,
-/*028d*/ 0x4301b344,
-/*028e*/ 0x10172006,
-/*028f*/ 0x121d220c,
-/*0290*/ 0x01b3441f,
-/*0291*/ 0x17200643,
-/*0292*/ 0x1d220c10,
-/*0293*/ 0x00001f12,
-/*0294*/ 0x4301b344,
-/*0295*/ 0x10172006,
-/*0296*/ 0x00020002,
-/*0297*/ 0x00020002,
-/*0298*/ 0x00020002,
-/*0299*/ 0x00020002,
-/*029a*/ 0x00020002,
-/*029b*/ 0x00000000,
-/*029c*/ 0x00000000,
-/*029d*/ 0x00000000,
-/*029e*/ 0x00000000,
-/*029f*/ 0x00000000,
-/*02a0*/ 0x00000000,
-/*02a1*/ 0x00000000,
-/*02a2*/ 0x00000000,
-/*02a3*/ 0x00000000,
-/*02a4*/ 0x00000000,
-/*02a5*/ 0x00000000,
-/*02a6*/ 0x00000000,
-/*02a7*/ 0x01000400,
-/*02a8*/ 0x00304c00,
-/*02a9*/ 0x0001e2f8,
-/*02aa*/ 0x0000304c,
-/*02ab*/ 0x0001e2f8,
-/*02ac*/ 0x0000304c,
-/*02ad*/ 0x0001e2f8,
-/*02ae*/ 0x08000000,
-/*02af*/ 0x00000100,
-/*02b0*/ 0x00000000,
-/*02b1*/ 0x00000000,
-/*02b2*/ 0x00000000,
-/*02b3*/ 0x00000000,
-/*02b4*/ 0x00000002
-};
diff --git a/drivers/staging/renesas/rcar/ddr/ddr_b/init_dram_tbl_h3ver2.h b/drivers/staging/renesas/rcar/ddr/ddr_b/init_dram_tbl_h3ver2.h
deleted file mode 100644
index 6e4c30eb8..000000000
--- a/drivers/staging/renesas/rcar/ddr/ddr_b/init_dram_tbl_h3ver2.h
+++ /dev/null
@@ -1,537 +0,0 @@
-/*
- * Copyright (c) 2015-2019, Renesas Electronics Corporation. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#define DDR_PHY_SLICE_REGSET_OFS_H3VER2  0x0400
-#define DDR_PHY_ADR_V_REGSET_OFS_H3VER2  0x0600
-#define DDR_PHY_ADR_I_REGSET_OFS_H3VER2  0x0640
-#define DDR_PHY_ADR_G_REGSET_OFS_H3VER2  0x0680
-#define DDR_PI_REGSET_OFS_H3VER2         0x0200
-
-#define DDR_PHY_SLICE_REGSET_SIZE_H3VER2 0x80
-#define DDR_PHY_ADR_V_REGSET_SIZE_H3VER2 0x40
-#define DDR_PHY_ADR_I_REGSET_SIZE_H3VER2 0x40
-#define DDR_PHY_ADR_G_REGSET_SIZE_H3VER2 0x80
-#define DDR_PI_REGSET_SIZE_H3VER2        0x100
-
-#define DDR_PHY_SLICE_REGSET_NUM_H3VER2  97
-#define DDR_PHY_ADR_V_REGSET_NUM_H3VER2  37
-#define DDR_PHY_ADR_I_REGSET_NUM_H3VER2  37
-#define DDR_PHY_ADR_G_REGSET_NUM_H3VER2  79
-#define DDR_PI_REGSET_NUM_H3VER2         245
-
-static const uint32_t
-    DDR_PHY_SLICE_REGSET_H3VER2[DDR_PHY_SLICE_REGSET_NUM_H3VER2] = {
-/*0400*/ 0x76543210,
-/*0401*/ 0x0004f008,
-/*0402*/ 0x00020133,
-/*0403*/ 0x00000000,
-/*0404*/ 0x00000000,
-/*0405*/ 0x00010000,
-/*0406*/ 0x016e6e0e,
-/*0407*/ 0x026e6e0e,
-/*0408*/ 0x00010300,
-/*0409*/ 0x04000100,
-/*040a*/ 0x01000000,
-/*040b*/ 0x00000000,
-/*040c*/ 0x00000000,
-/*040d*/ 0x00000100,
-/*040e*/ 0x001700c0,
-/*040f*/ 0x020100b0,
-/*0410*/ 0x00030020,
-/*0411*/ 0x00000000,
-/*0412*/ 0x00000000,
-/*0413*/ 0x00000000,
-/*0414*/ 0x00000000,
-/*0415*/ 0x00000000,
-/*0416*/ 0x00000000,
-/*0417*/ 0x00000000,
-/*0418*/ 0x09000000,
-/*0419*/ 0x04080000,
-/*041a*/ 0x04080400,
-/*041b*/ 0x08000000,
-/*041c*/ 0x0c008007,
-/*041d*/ 0x00000f00,
-/*041e*/ 0x00000100,
-/*041f*/ 0x55aa55aa,
-/*0420*/ 0x33cc33cc,
-/*0421*/ 0x0ff00ff0,
-/*0422*/ 0x0f0ff0f0,
-/*0423*/ 0x00018e38,
-/*0424*/ 0x00000000,
-/*0425*/ 0x00000000,
-/*0426*/ 0x00000000,
-/*0427*/ 0x00000000,
-/*0428*/ 0x00000000,
-/*0429*/ 0x00000000,
-/*042a*/ 0x00000000,
-/*042b*/ 0x00000000,
-/*042c*/ 0x00000000,
-/*042d*/ 0x00000000,
-/*042e*/ 0x00000000,
-/*042f*/ 0x00000000,
-/*0430*/ 0x00000000,
-/*0431*/ 0x00000000,
-/*0432*/ 0x00000000,
-/*0433*/ 0x00000000,
-/*0434*/ 0x00000000,
-/*0435*/ 0x00000000,
-/*0436*/ 0x00000000,
-/*0437*/ 0x00000000,
-/*0438*/ 0x00000104,
-/*0439*/ 0x00082020,
-/*043a*/ 0x08200820,
-/*043b*/ 0x08200820,
-/*043c*/ 0x08200820,
-/*043d*/ 0x08200820,
-/*043e*/ 0x08200820,
-/*043f*/ 0x00000000,
-/*0440*/ 0x00000000,
-/*0441*/ 0x03000300,
-/*0442*/ 0x03000300,
-/*0443*/ 0x03000300,
-/*0444*/ 0x03000300,
-/*0445*/ 0x00000300,
-/*0446*/ 0x00000000,
-/*0447*/ 0x00000000,
-/*0448*/ 0x00000000,
-/*0449*/ 0x00000000,
-/*044a*/ 0x00000000,
-/*044b*/ 0x00a000a0,
-/*044c*/ 0x00a000a0,
-/*044d*/ 0x00a000a0,
-/*044e*/ 0x00a000a0,
-/*044f*/ 0x00a000a0,
-/*0450*/ 0x00a000a0,
-/*0451*/ 0x00a000a0,
-/*0452*/ 0x00a000a0,
-/*0453*/ 0x00a000a0,
-/*0454*/ 0x01040109,
-/*0455*/ 0x00000200,
-/*0456*/ 0x01000000,
-/*0457*/ 0x00000200,
-/*0458*/ 0x00000004,
-/*0459*/ 0x4041a141,
-/*045a*/ 0xc00141a0,
-/*045b*/ 0x0e0000c0,
-/*045c*/ 0x0010000c,
-/*045d*/ 0x063e4208,
-/*045e*/ 0x0f0c180c,
-/*045f*/ 0x00e00140,
-/*0460*/ 0x00000c20
-};
-
-static const uint32_t
-    DDR_PHY_ADR_V_REGSET_H3VER2[DDR_PHY_ADR_V_REGSET_NUM_H3VER2] = {
-/*0600*/ 0x00000000,
-/*0601*/ 0x00000000,
-/*0602*/ 0x00000000,
-/*0603*/ 0x00000000,
-/*0604*/ 0x00000000,
-/*0605*/ 0x00000000,
-/*0606*/ 0x00000000,
-/*0607*/ 0x00010000,
-/*0608*/ 0x00000200,
-/*0609*/ 0x00000000,
-/*060a*/ 0x00000000,
-/*060b*/ 0x00000000,
-/*060c*/ 0x00400320,
-/*060d*/ 0x00000040,
-/*060e*/ 0x00dcba98,
-/*060f*/ 0x03000000,
-/*0610*/ 0x00000200,
-/*0611*/ 0x00000000,
-/*0612*/ 0x00000000,
-/*0613*/ 0x00000000,
-/*0614*/ 0x0000002a,
-/*0615*/ 0x00000015,
-/*0616*/ 0x00000015,
-/*0617*/ 0x0000002a,
-/*0618*/ 0x00000033,
-/*0619*/ 0x0000000c,
-/*061a*/ 0x0000000c,
-/*061b*/ 0x00000033,
-/*061c*/ 0x00418820,
-/*061d*/ 0x003f0000,
-/*061e*/ 0x0000003f,
-/*061f*/ 0x0002c06e,
-/*0620*/ 0x02c002c0,
-/*0621*/ 0x02c002c0,
-/*0622*/ 0x000002c0,
-/*0623*/ 0x42080010,
-/*0624*/ 0x0000033e
-};
-
-static const uint32_t
-    DDR_PHY_ADR_I_REGSET_H3VER2[DDR_PHY_ADR_I_REGSET_NUM_H3VER2] = {
-/*0640*/ 0x00000000,
-/*0641*/ 0x00000000,
-/*0642*/ 0x00000000,
-/*0643*/ 0x00000000,
-/*0644*/ 0x00000000,
-/*0645*/ 0x00000000,
-/*0646*/ 0x00000000,
-/*0647*/ 0x00000000,
-/*0648*/ 0x00000000,
-/*0649*/ 0x00000000,
-/*064a*/ 0x00000000,
-/*064b*/ 0x00000000,
-/*064c*/ 0x00000000,
-/*064d*/ 0x00000000,
-/*064e*/ 0x00000000,
-/*064f*/ 0x00000000,
-/*0650*/ 0x00000000,
-/*0651*/ 0x00000000,
-/*0652*/ 0x00000000,
-/*0653*/ 0x00000000,
-/*0654*/ 0x00000000,
-/*0655*/ 0x00000000,
-/*0656*/ 0x00000000,
-/*0657*/ 0x00000000,
-/*0658*/ 0x00000000,
-/*0659*/ 0x00000000,
-/*065a*/ 0x00000000,
-/*065b*/ 0x00000000,
-/*065c*/ 0x00000000,
-/*065d*/ 0x00000000,
-/*065e*/ 0x00000000,
-/*065f*/ 0x00000000,
-/*0660*/ 0x00000000,
-/*0661*/ 0x00000000,
-/*0662*/ 0x00000000,
-/*0663*/ 0x00000000,
-/*0664*/ 0x00000000
-};
-
-static const uint32_t
-    DDR_PHY_ADR_G_REGSET_H3VER2[DDR_PHY_ADR_G_REGSET_NUM_H3VER2] = {
-/*0680*/ 0x00000000,
-/*0681*/ 0x00000100,
-/*0682*/ 0x00000000,
-/*0683*/ 0x00050000,
-/*0684*/ 0x0f000000,
-/*0685*/ 0x00800400,
-/*0686*/ 0x00020032,
-/*0687*/ 0x00020055,
-/*0688*/ 0x00000000,
-/*0689*/ 0x00000000,
-/*068a*/ 0x00000000,
-/*068b*/ 0x00000050,
-/*068c*/ 0x00000000,
-/*068d*/ 0x01010100,
-/*068e*/ 0x01000200,
-/*068f*/ 0x00000000,
-/*0690*/ 0x00010100,
-/*0691*/ 0x00000000,
-/*0692*/ 0x00000000,
-/*0693*/ 0x00000000,
-/*0694*/ 0x00000000,
-/*0695*/ 0x00005064,
-/*0696*/ 0x01421142,
-/*0697*/ 0x00000142,
-/*0698*/ 0x00000000,
-/*0699*/ 0x000f1100,
-/*069a*/ 0x0f110f11,
-/*069b*/ 0x09000f11,
-/*069c*/ 0x00000003,
-/*069d*/ 0x0002c000,
-/*069e*/ 0x02c002c0,
-/*069f*/ 0x000002c0,
-/*06a0*/ 0x03421342,
-/*06a1*/ 0x00000342,
-/*06a2*/ 0x00000000,
-/*06a3*/ 0x00000000,
-/*06a4*/ 0x05020000,
-/*06a5*/ 0x14000000,
-/*06a6*/ 0x027f6e00,
-/*06a7*/ 0x047f027f,
-/*06a8*/ 0x00027f6e,
-/*06a9*/ 0x00047f6e,
-/*06aa*/ 0x0003554f,
-/*06ab*/ 0x0001554f,
-/*06ac*/ 0x0001554f,
-/*06ad*/ 0x0001554f,
-/*06ae*/ 0x0001554f,
-/*06af*/ 0x00003fee,
-/*06b0*/ 0x0001554f,
-/*06b1*/ 0x00003fee,
-/*06b2*/ 0x0001554f,
-/*06b3*/ 0x00027f6e,
-/*06b4*/ 0x0001554f,
-/*06b5*/ 0x00004011,
-/*06b6*/ 0x00004410,
-/*06b7*/ 0x00000000,
-/*06b8*/ 0x00000000,
-/*06b9*/ 0x00000000,
-/*06ba*/ 0x00000065,
-/*06bb*/ 0x00000000,
-/*06bc*/ 0x00020201,
-/*06bd*/ 0x00000000,
-/*06be*/ 0x03000000,
-/*06bf*/ 0x00000008,
-/*06c0*/ 0x00000000,
-/*06c1*/ 0x00000000,
-/*06c2*/ 0x00000000,
-/*06c3*/ 0x00000000,
-/*06c4*/ 0x00000001,
-/*06c5*/ 0x00000000,
-/*06c6*/ 0x00000000,
-/*06c7*/ 0x00000000,
-/*06c8*/ 0x000000e4,
-/*06c9*/ 0x00010198,
-/*06ca*/ 0x00000000,
-/*06cb*/ 0x00000000,
-/*06cc*/ 0x07010000,
-/*06cd*/ 0x00000104,
-/*06ce*/ 0x00000000
-};
-
-static const uint32_t DDR_PI_REGSET_H3VER2[DDR_PI_REGSET_NUM_H3VER2] = {
-/*0200*/ 0x00000b00,
-/*0201*/ 0x00000100,
-/*0202*/ 0x00640000,
-/*0203*/ 0x00000000,
-/*0204*/ 0x0000ffff,
-/*0205*/ 0x00000000,
-/*0206*/ 0x0000ffff,
-/*0207*/ 0x00000000,
-/*0208*/ 0x0000ffff,
-/*0209*/ 0x0000304c,
-/*020a*/ 0x00000200,
-/*020b*/ 0x00000200,
-/*020c*/ 0x00000200,
-/*020d*/ 0x00000200,
-/*020e*/ 0x0000304c,
-/*020f*/ 0x00000200,
-/*0210*/ 0x00000200,
-/*0211*/ 0x00000200,
-/*0212*/ 0x00000200,
-/*0213*/ 0x0000304c,
-/*0214*/ 0x00000200,
-/*0215*/ 0x00000200,
-/*0216*/ 0x00000200,
-/*0217*/ 0x00000200,
-/*0218*/ 0x00010000,
-/*0219*/ 0x00000003,
-/*021a*/ 0x01000001,
-/*021b*/ 0x00000000,
-/*021c*/ 0x00000000,
-/*021d*/ 0x00000000,
-/*021e*/ 0x00000000,
-/*021f*/ 0x00000000,
-/*0220*/ 0x00000000,
-/*0221*/ 0x00000000,
-/*0222*/ 0x00000000,
-/*0223*/ 0x00000000,
-/*0224*/ 0x00000000,
-/*0225*/ 0x00000000,
-/*0226*/ 0x00000000,
-/*0227*/ 0x00000000,
-/*0228*/ 0x00000000,
-/*0229*/ 0x00000000,
-/*022a*/ 0x00000000,
-/*022b*/ 0x0f000101,
-/*022c*/ 0x08492d25,
-/*022d*/ 0x500e0c04,
-/*022e*/ 0x0002500e,
-/*022f*/ 0x00000301,
-/*0230*/ 0x00000046,
-/*0231*/ 0x000000cf,
-/*0232*/ 0x00001826,
-/*0233*/ 0x000000cf,
-/*0234*/ 0x00001826,
-/*0235*/ 0x00000005,
-/*0236*/ 0x00000000,
-/*0237*/ 0x00000000,
-/*0238*/ 0x00000000,
-/*0239*/ 0x00000000,
-/*023a*/ 0x00000000,
-/*023b*/ 0x00000000,
-/*023c*/ 0x00000000,
-/*023d*/ 0x00000000,
-/*023e*/ 0x04010000,
-/*023f*/ 0x00000404,
-/*0240*/ 0x0101280a,
-/*0241*/ 0x00000000,
-/*0242*/ 0x00000000,
-/*0243*/ 0x0003000f,
-/*0244*/ 0x00000018,
-/*0245*/ 0x00000000,
-/*0246*/ 0x00000000,
-/*0247*/ 0x00060002,
-/*0248*/ 0x00010001,
-/*0249*/ 0x01000101,
-/*024a*/ 0x04020201,
-/*024b*/ 0x00080804,
-/*024c*/ 0x00000000,
-/*024d*/ 0x08030000,
-/*024e*/ 0x15150408,
-/*024f*/ 0x00000000,
-/*0250*/ 0x00000000,
-/*0251*/ 0x00000000,
-/*0252*/ 0x0f0f0000,
-/*0253*/ 0x0000001e,
-/*0254*/ 0x00000000,
-/*0255*/ 0x01000300,
-/*0256*/ 0x00000100,
-/*0257*/ 0x00000000,
-/*0258*/ 0x00000000,
-/*0259*/ 0x01000000,
-/*025a*/ 0x00000101,
-/*025b*/ 0x55555a5a,
-/*025c*/ 0x55555a5a,
-/*025d*/ 0x55555a5a,
-/*025e*/ 0x55555a5a,
-/*025f*/ 0x0e0e0001,
-/*0260*/ 0x0c0c000e,
-/*0261*/ 0x0601000c,
-/*0262*/ 0x17170106,
-/*0263*/ 0x00020202,
-/*0264*/ 0x03000000,
-/*0265*/ 0x00000000,
-/*0266*/ 0x00181703,
-/*0267*/ 0x00280006,
-/*0268*/ 0x00280016,
-/*0269*/ 0x00000016,
-/*026a*/ 0x00000000,
-/*026b*/ 0x00000000,
-/*026c*/ 0x00000000,
-/*026d*/ 0x0a000000,
-/*026e*/ 0x00010a14,
-/*026f*/ 0x00030005,
-/*0270*/ 0x0003018d,
-/*0271*/ 0x000a018d,
-/*0272*/ 0x00060100,
-/*0273*/ 0x01000006,
-/*0274*/ 0x018e018e,
-/*0275*/ 0x018e0100,
-/*0276*/ 0x1111018e,
-/*0277*/ 0x10010204,
-/*0278*/ 0x09090650,
-/*0279*/ 0xff110202,
-/*027a*/ 0x00ff1000,
-/*027b*/ 0x00ff1000,
-/*027c*/ 0x04041000,
-/*027d*/ 0x18020100,
-/*027e*/ 0x01010018,
-/*027f*/ 0x004a004a,
-/*0280*/ 0x004b004a,
-/*0281*/ 0x050f0000,
-/*0282*/ 0x0c01021e,
-/*0283*/ 0x34000000,
-/*0284*/ 0x00000000,
-/*0285*/ 0x00000000,
-/*0286*/ 0x00000000,
-/*0287*/ 0x00000000,
-/*0288*/ 0x36312ed4,
-/*0289*/ 0x2ed41111,
-/*028a*/ 0x11113631,
-/*028b*/ 0x36312ed4,
-/*028c*/ 0xd4001111,
-/*028d*/ 0x1136312e,
-/*028e*/ 0x312ed411,
-/*028f*/ 0xd4111136,
-/*0290*/ 0x1136312e,
-/*0291*/ 0x2ed40011,
-/*0292*/ 0x11113631,
-/*0293*/ 0x36312ed4,
-/*0294*/ 0x2ed41111,
-/*0295*/ 0x11113631,
-/*0296*/ 0x312ed400,
-/*0297*/ 0xd4111136,
-/*0298*/ 0x1136312e,
-/*0299*/ 0x312ed411,
-/*029a*/ 0x00111136,
-/*029b*/ 0x018d0200,
-/*029c*/ 0x018d018d,
-/*029d*/ 0x1d220c08,
-/*029e*/ 0x00001f12,
-/*029f*/ 0x4301b344,
-/*02a0*/ 0x10172006,
-/*02a1*/ 0x121d220c,
-/*02a2*/ 0x01b3441f,
-/*02a3*/ 0x17200643,
-/*02a4*/ 0x1d220c10,
-/*02a5*/ 0x00001f12,
-/*02a6*/ 0x4301b344,
-/*02a7*/ 0x10172006,
-/*02a8*/ 0x00020002,
-/*02a9*/ 0x00020002,
-/*02aa*/ 0x00020002,
-/*02ab*/ 0x00020002,
-/*02ac*/ 0x00020002,
-/*02ad*/ 0x00000000,
-/*02ae*/ 0x00000000,
-/*02af*/ 0x00000000,
-/*02b0*/ 0x00000000,
-/*02b1*/ 0x00000000,
-/*02b2*/ 0x00000000,
-/*02b3*/ 0x00000000,
-/*02b4*/ 0x00000000,
-/*02b5*/ 0x00000000,
-/*02b6*/ 0x00000000,
-/*02b7*/ 0x00000000,
-/*02b8*/ 0x00000000,
-/*02b9*/ 0x00000400,
-/*02ba*/ 0x05040302,
-/*02bb*/ 0x01000f0e,
-/*02bc*/ 0x07060504,
-/*02bd*/ 0x03020100,
-/*02be*/ 0x02010000,
-/*02bf*/ 0x00000103,
-/*02c0*/ 0x0000304c,
-/*02c1*/ 0x0001e2f8,
-/*02c2*/ 0x0000304c,
-/*02c3*/ 0x0001e2f8,
-/*02c4*/ 0x0000304c,
-/*02c5*/ 0x0001e2f8,
-/*02c6*/ 0x08000000,
-/*02c7*/ 0x00000100,
-/*02c8*/ 0x00000000,
-/*02c9*/ 0x00000000,
-/*02ca*/ 0x00000000,
-/*02cb*/ 0x00000000,
-/*02cc*/ 0x00010000,
-/*02cd*/ 0x00000000,
-/*02ce*/ 0x00000000,
-/*02cf*/ 0x00000000,
-/*02d0*/ 0x00000000,
-/*02d1*/ 0x00000000,
-/*02d2*/ 0x00000000,
-/*02d3*/ 0x00000000,
-/*02d4*/ 0x00000000,
-/*02d5*/ 0x00000000,
-/*02d6*/ 0x00000000,
-/*02d7*/ 0x00000000,
-/*02d8*/ 0x00000000,
-/*02d9*/ 0x00000000,
-/*02da*/ 0x00000000,
-/*02db*/ 0x00000000,
-/*02dc*/ 0x00000000,
-/*02dd*/ 0x00000000,
-/*02de*/ 0x00000000,
-/*02df*/ 0x00000000,
-/*02e0*/ 0x00000000,
-/*02e1*/ 0x00000000,
-/*02e2*/ 0x00000000,
-/*02e3*/ 0x00000000,
-/*02e4*/ 0x00000000,
-/*02e5*/ 0x00000000,
-/*02e6*/ 0x00000000,
-/*02e7*/ 0x00000000,
-/*02e8*/ 0x00000000,
-/*02e9*/ 0x00000000,
-/*02ea*/ 0x00000000,
-/*02eb*/ 0x00000000,
-/*02ec*/ 0x00000000,
-/*02ed*/ 0x00000000,
-/*02ee*/ 0x00000002,
-/*02ef*/ 0x00000000,
-/*02f0*/ 0x00000000,
-/*02f1*/ 0x00000000,
-/*02f2*/ 0x00000000,
-/*02f3*/ 0x00000000,
-/*02f4*/ 0x00000000
-};
diff --git a/drivers/staging/renesas/rcar/ddr/ddr_b/init_dram_tbl_m3.h b/drivers/staging/renesas/rcar/ddr/ddr_b/init_dram_tbl_m3.h
deleted file mode 100644
index 3c62107ed..000000000
--- a/drivers/staging/renesas/rcar/ddr/ddr_b/init_dram_tbl_m3.h
+++ /dev/null
@@ -1,467 +0,0 @@
-/*
- * Copyright (c) 2015-2019, Renesas Electronics Corporation. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#define DDR_PHY_SLICE_REGSET_OFS_M3  0x0800
-#define DDR_PHY_ADR_V_REGSET_OFS_M3  0x0a00
-#define DDR_PHY_ADR_I_REGSET_OFS_M3  0x0a80
-#define DDR_PHY_ADR_G_REGSET_OFS_M3  0x0b80
-#define DDR_PI_REGSET_OFS_M3         0x0200
-
-#define DDR_PHY_SLICE_REGSET_SIZE_M3 0x80
-#define DDR_PHY_ADR_V_REGSET_SIZE_M3 0x80
-#define DDR_PHY_ADR_I_REGSET_SIZE_M3 0x80
-#define DDR_PHY_ADR_G_REGSET_SIZE_M3 0x80
-#define DDR_PI_REGSET_SIZE_M3        0x100
-
-#define DDR_PHY_SLICE_REGSET_NUM_M3  89
-#define DDR_PHY_ADR_V_REGSET_NUM_M3  37
-#define DDR_PHY_ADR_I_REGSET_NUM_M3  37
-#define DDR_PHY_ADR_G_REGSET_NUM_M3  64
-#define DDR_PI_REGSET_NUM_M3         202
-
-static const uint32_t DDR_PHY_SLICE_REGSET_M3[DDR_PHY_SLICE_REGSET_NUM_M3] = {
-/*0800*/ 0x76543210,
-/*0801*/ 0x0004f008,
-/*0802*/ 0x00000000,
-/*0803*/ 0x00000000,
-/*0804*/ 0x00010000,
-/*0805*/ 0x036e6e0e,
-/*0806*/ 0x026e6e0e,
-/*0807*/ 0x00010300,
-/*0808*/ 0x04000100,
-/*0809*/ 0x00000300,
-/*080a*/ 0x001700c0,
-/*080b*/ 0x00b00201,
-/*080c*/ 0x00030020,
-/*080d*/ 0x00000000,
-/*080e*/ 0x00000000,
-/*080f*/ 0x00000000,
-/*0810*/ 0x00000000,
-/*0811*/ 0x00000000,
-/*0812*/ 0x00000000,
-/*0813*/ 0x00000000,
-/*0814*/ 0x09000000,
-/*0815*/ 0x04080000,
-/*0816*/ 0x04080400,
-/*0817*/ 0x00000000,
-/*0818*/ 0x32103210,
-/*0819*/ 0x00800708,
-/*081a*/ 0x000f000c,
-/*081b*/ 0x00000100,
-/*081c*/ 0x55aa55aa,
-/*081d*/ 0x33cc33cc,
-/*081e*/ 0x0ff00ff0,
-/*081f*/ 0x0f0ff0f0,
-/*0820*/ 0x00018e38,
-/*0821*/ 0x00000000,
-/*0822*/ 0x00000000,
-/*0823*/ 0x00000000,
-/*0824*/ 0x00000000,
-/*0825*/ 0x00000000,
-/*0826*/ 0x00000000,
-/*0827*/ 0x00000000,
-/*0828*/ 0x00000000,
-/*0829*/ 0x00000000,
-/*082a*/ 0x00000000,
-/*082b*/ 0x00000000,
-/*082c*/ 0x00000000,
-/*082d*/ 0x00000000,
-/*082e*/ 0x00000000,
-/*082f*/ 0x00000000,
-/*0830*/ 0x00000000,
-/*0831*/ 0x00000000,
-/*0832*/ 0x00000000,
-/*0833*/ 0x00200000,
-/*0834*/ 0x08200820,
-/*0835*/ 0x08200820,
-/*0836*/ 0x08200820,
-/*0837*/ 0x08200820,
-/*0838*/ 0x08200820,
-/*0839*/ 0x00000820,
-/*083a*/ 0x03000300,
-/*083b*/ 0x03000300,
-/*083c*/ 0x03000300,
-/*083d*/ 0x03000300,
-/*083e*/ 0x00000300,
-/*083f*/ 0x00000000,
-/*0840*/ 0x00000000,
-/*0841*/ 0x00000000,
-/*0842*/ 0x00000000,
-/*0843*/ 0x00a00000,
-/*0844*/ 0x00a000a0,
-/*0845*/ 0x00a000a0,
-/*0846*/ 0x00a000a0,
-/*0847*/ 0x00a000a0,
-/*0848*/ 0x00a000a0,
-/*0849*/ 0x00a000a0,
-/*084a*/ 0x00a000a0,
-/*084b*/ 0x00a000a0,
-/*084c*/ 0x010900a0,
-/*084d*/ 0x02000104,
-/*084e*/ 0x00000000,
-/*084f*/ 0x00010000,
-/*0850*/ 0x00000200,
-/*0851*/ 0x4041a141,
-/*0852*/ 0xc00141a0,
-/*0853*/ 0x0e0100c0,
-/*0854*/ 0x0010000c,
-/*0855*/ 0x0c064208,
-/*0856*/ 0x000f0c18,
-/*0857*/ 0x00e00140,
-/*0858*/ 0x00000c20
-};
-
-static const uint32_t DDR_PHY_ADR_V_REGSET_M3[DDR_PHY_ADR_V_REGSET_NUM_M3] = {
-/*0a00*/ 0x00000000,
-/*0a01*/ 0x00000000,
-/*0a02*/ 0x00000000,
-/*0a03*/ 0x00000000,
-/*0a04*/ 0x00000000,
-/*0a05*/ 0x00000000,
-/*0a06*/ 0x00000002,
-/*0a07*/ 0x00000000,
-/*0a08*/ 0x00000000,
-/*0a09*/ 0x00000000,
-/*0a0a*/ 0x00400320,
-/*0a0b*/ 0x00000040,
-/*0a0c*/ 0x00dcba98,
-/*0a0d*/ 0x00000000,
-/*0a0e*/ 0x00dcba98,
-/*0a0f*/ 0x01000000,
-/*0a10*/ 0x00020003,
-/*0a11*/ 0x00000000,
-/*0a12*/ 0x00000000,
-/*0a13*/ 0x00000000,
-/*0a14*/ 0x0000002a,
-/*0a15*/ 0x00000015,
-/*0a16*/ 0x00000015,
-/*0a17*/ 0x0000002a,
-/*0a18*/ 0x00000033,
-/*0a19*/ 0x0000000c,
-/*0a1a*/ 0x0000000c,
-/*0a1b*/ 0x00000033,
-/*0a1c*/ 0x0a418820,
-/*0a1d*/ 0x003f0000,
-/*0a1e*/ 0x0000003f,
-/*0a1f*/ 0x0002c06e,
-/*0a20*/ 0x02c002c0,
-/*0a21*/ 0x02c002c0,
-/*0a22*/ 0x000002c0,
-/*0a23*/ 0x42080010,
-/*0a24*/ 0x00000003
-};
-
-static const uint32_t DDR_PHY_ADR_I_REGSET_M3[DDR_PHY_ADR_I_REGSET_NUM_M3] = {
-/*0a80*/ 0x04040404,
-/*0a81*/ 0x00000404,
-/*0a82*/ 0x00000000,
-/*0a83*/ 0x00000000,
-/*0a84*/ 0x00000000,
-/*0a85*/ 0x00000000,
-/*0a86*/ 0x00000002,
-/*0a87*/ 0x00000000,
-/*0a88*/ 0x00000000,
-/*0a89*/ 0x00000000,
-/*0a8a*/ 0x00400320,
-/*0a8b*/ 0x00000040,
-/*0a8c*/ 0x00000000,
-/*0a8d*/ 0x00000000,
-/*0a8e*/ 0x00000000,
-/*0a8f*/ 0x01000000,
-/*0a90*/ 0x00020003,
-/*0a91*/ 0x00000000,
-/*0a92*/ 0x00000000,
-/*0a93*/ 0x00000000,
-/*0a94*/ 0x0000002a,
-/*0a95*/ 0x00000015,
-/*0a96*/ 0x00000015,
-/*0a97*/ 0x0000002a,
-/*0a98*/ 0x00000033,
-/*0a99*/ 0x0000000c,
-/*0a9a*/ 0x0000000c,
-/*0a9b*/ 0x00000033,
-/*0a9c*/ 0x00000000,
-/*0a9d*/ 0x00000000,
-/*0a9e*/ 0x00000000,
-/*0a9f*/ 0x0002c06e,
-/*0aa0*/ 0x02c002c0,
-/*0aa1*/ 0x02c002c0,
-/*0aa2*/ 0x000002c0,
-/*0aa3*/ 0x42080010,
-/*0aa4*/ 0x00000003
-};
-
-static const uint32_t DDR_PHY_ADR_G_REGSET_M3[DDR_PHY_ADR_G_REGSET_NUM_M3] = {
-/*0b80*/ 0x00000001,
-/*0b81*/ 0x00000000,
-/*0b82*/ 0x00000005,
-/*0b83*/ 0x04000f00,
-/*0b84*/ 0x00020080,
-/*0b85*/ 0x00020055,
-/*0b86*/ 0x00000000,
-/*0b87*/ 0x00000000,
-/*0b88*/ 0x00000000,
-/*0b89*/ 0x00000050,
-/*0b8a*/ 0x00000000,
-/*0b8b*/ 0x01010100,
-/*0b8c*/ 0x00000600,
-/*0b8d*/ 0x50640000,
-/*0b8e*/ 0x01421142,
-/*0b8f*/ 0x00000142,
-/*0b90*/ 0x00000000,
-/*0b91*/ 0x000f1600,
-/*0b92*/ 0x0f160f16,
-/*0b93*/ 0x0f160f16,
-/*0b94*/ 0x00000003,
-/*0b95*/ 0x0002c000,
-/*0b96*/ 0x02c002c0,
-/*0b97*/ 0x000002c0,
-/*0b98*/ 0x03421342,
-/*0b99*/ 0x00000342,
-/*0b9a*/ 0x00000000,
-/*0b9b*/ 0x00000000,
-/*0b9c*/ 0x05020000,
-/*0b9d*/ 0x00000000,
-/*0b9e*/ 0x00027f6e,
-/*0b9f*/ 0x047f027f,
-/*0ba0*/ 0x00027f6e,
-/*0ba1*/ 0x00047f6e,
-/*0ba2*/ 0x0003554f,
-/*0ba3*/ 0x0001554f,
-/*0ba4*/ 0x0001554f,
-/*0ba5*/ 0x0001554f,
-/*0ba6*/ 0x0001554f,
-/*0ba7*/ 0x00003fee,
-/*0ba8*/ 0x0001554f,
-/*0ba9*/ 0x00003fee,
-/*0baa*/ 0x0001554f,
-/*0bab*/ 0x00027f6e,
-/*0bac*/ 0x0001554f,
-/*0bad*/ 0x00000000,
-/*0bae*/ 0x00000000,
-/*0baf*/ 0x00000000,
-/*0bb0*/ 0x65000000,
-/*0bb1*/ 0x00000000,
-/*0bb2*/ 0x00000000,
-/*0bb3*/ 0x00000201,
-/*0bb4*/ 0x00000000,
-/*0bb5*/ 0x00000000,
-/*0bb6*/ 0x00000000,
-/*0bb7*/ 0x00000000,
-/*0bb8*/ 0x00000000,
-/*0bb9*/ 0x00000000,
-/*0bba*/ 0x00000000,
-/*0bbb*/ 0x00000000,
-/*0bbc*/ 0x06e40000,
-/*0bbd*/ 0x00000000,
-/*0bbe*/ 0x00000000,
-/*0bbf*/ 0x00010000
-};
-
-static const uint32_t DDR_PI_REGSET_M3[DDR_PI_REGSET_NUM_M3] = {
-/*0200*/ 0x00000b00,
-/*0201*/ 0x00000100,
-/*0202*/ 0x00000000,
-/*0203*/ 0x0000ffff,
-/*0204*/ 0x00000000,
-/*0205*/ 0x0000ffff,
-/*0206*/ 0x00000000,
-/*0207*/ 0x304cffff,
-/*0208*/ 0x00000200,
-/*0209*/ 0x00000200,
-/*020a*/ 0x00000200,
-/*020b*/ 0x00000200,
-/*020c*/ 0x0000304c,
-/*020d*/ 0x00000200,
-/*020e*/ 0x00000200,
-/*020f*/ 0x00000200,
-/*0210*/ 0x00000200,
-/*0211*/ 0x0000304c,
-/*0212*/ 0x00000200,
-/*0213*/ 0x00000200,
-/*0214*/ 0x00000200,
-/*0215*/ 0x00000200,
-/*0216*/ 0x00010000,
-/*0217*/ 0x00000003,
-/*0218*/ 0x01000001,
-/*0219*/ 0x00000000,
-/*021a*/ 0x00000000,
-/*021b*/ 0x00000000,
-/*021c*/ 0x00000000,
-/*021d*/ 0x00000000,
-/*021e*/ 0x00000000,
-/*021f*/ 0x00000000,
-/*0220*/ 0x00000000,
-/*0221*/ 0x00000000,
-/*0222*/ 0x00000000,
-/*0223*/ 0x00000000,
-/*0224*/ 0x00000000,
-/*0225*/ 0x00000000,
-/*0226*/ 0x00000000,
-/*0227*/ 0x00000000,
-/*0228*/ 0x00000000,
-/*0229*/ 0x0f000101,
-/*022a*/ 0x08492d25,
-/*022b*/ 0x0e0c0004,
-/*022c*/ 0x000e5000,
-/*022d*/ 0x00000250,
-/*022e*/ 0x00460003,
-/*022f*/ 0x182600cf,
-/*0230*/ 0x182600cf,
-/*0231*/ 0x00000005,
-/*0232*/ 0x00000000,
-/*0233*/ 0x00000000,
-/*0234*/ 0x00000000,
-/*0235*/ 0x00000000,
-/*0236*/ 0x00000000,
-/*0237*/ 0x00000000,
-/*0238*/ 0x00000000,
-/*0239*/ 0x01000000,
-/*023a*/ 0x00040404,
-/*023b*/ 0x01280a00,
-/*023c*/ 0x00000000,
-/*023d*/ 0x000f0000,
-/*023e*/ 0x00001803,
-/*023f*/ 0x00000000,
-/*0240*/ 0x00000000,
-/*0241*/ 0x00060002,
-/*0242*/ 0x00010001,
-/*0243*/ 0x01000101,
-/*0244*/ 0x04020201,
-/*0245*/ 0x00080804,
-/*0246*/ 0x00000000,
-/*0247*/ 0x08030000,
-/*0248*/ 0x15150408,
-/*0249*/ 0x00000000,
-/*024a*/ 0x00000000,
-/*024b*/ 0x00000000,
-/*024c*/ 0x000f0f00,
-/*024d*/ 0x0000001e,
-/*024e*/ 0x00000000,
-/*024f*/ 0x01000300,
-/*0250*/ 0x00000000,
-/*0251*/ 0x00000000,
-/*0252*/ 0x01000000,
-/*0253*/ 0x00010101,
-/*0254*/ 0x000e0e0e,
-/*0255*/ 0x000c0c0c,
-/*0256*/ 0x02060601,
-/*0257*/ 0x00000000,
-/*0258*/ 0x00000003,
-/*0259*/ 0x00181703,
-/*025a*/ 0x00280006,
-/*025b*/ 0x00280016,
-/*025c*/ 0x00000016,
-/*025d*/ 0x00000000,
-/*025e*/ 0x00000000,
-/*025f*/ 0x00000000,
-/*0260*/ 0x140a0000,
-/*0261*/ 0x0005010a,
-/*0262*/ 0x03018d03,
-/*0263*/ 0x000a018d,
-/*0264*/ 0x00060100,
-/*0265*/ 0x01000006,
-/*0266*/ 0x018e018e,
-/*0267*/ 0x018e0100,
-/*0268*/ 0x1111018e,
-/*0269*/ 0x10010204,
-/*026a*/ 0x09090650,
-/*026b*/ 0x20110202,
-/*026c*/ 0x00201000,
-/*026d*/ 0x00201000,
-/*026e*/ 0x04041000,
-/*026f*/ 0x18020100,
-/*0270*/ 0x00010118,
-/*0271*/ 0x004b004a,
-/*0272*/ 0x050f0000,
-/*0273*/ 0x0c01021e,
-/*0274*/ 0x34000000,
-/*0275*/ 0x00000000,
-/*0276*/ 0x00000000,
-/*0277*/ 0x00000000,
-/*0278*/ 0x0000d400,
-/*0279*/ 0x0031002e,
-/*027a*/ 0x00111136,
-/*027b*/ 0x002e00d4,
-/*027c*/ 0x11360031,
-/*027d*/ 0x0000d411,
-/*027e*/ 0x0031002e,
-/*027f*/ 0x00111136,
-/*0280*/ 0x002e00d4,
-/*0281*/ 0x11360031,
-/*0282*/ 0x0000d411,
-/*0283*/ 0x0031002e,
-/*0284*/ 0x00111136,
-/*0285*/ 0x002e00d4,
-/*0286*/ 0x11360031,
-/*0287*/ 0x00d40011,
-/*0288*/ 0x0031002e,
-/*0289*/ 0x00111136,
-/*028a*/ 0x002e00d4,
-/*028b*/ 0x11360031,
-/*028c*/ 0x0000d411,
-/*028d*/ 0x0031002e,
-/*028e*/ 0x00111136,
-/*028f*/ 0x002e00d4,
-/*0290*/ 0x11360031,
-/*0291*/ 0x0000d411,
-/*0292*/ 0x0031002e,
-/*0293*/ 0x00111136,
-/*0294*/ 0x002e00d4,
-/*0295*/ 0x11360031,
-/*0296*/ 0x02000011,
-/*0297*/ 0x018d018d,
-/*0298*/ 0x0c08018d,
-/*0299*/ 0x1f121d22,
-/*029a*/ 0x4301b344,
-/*029b*/ 0x10172006,
-/*029c*/ 0x1d220c10,
-/*029d*/ 0x00001f12,
-/*029e*/ 0x4301b344,
-/*029f*/ 0x10172006,
-/*02a0*/ 0x1d220c10,
-/*02a1*/ 0x00001f12,
-/*02a2*/ 0x4301b344,
-/*02a3*/ 0x10172006,
-/*02a4*/ 0x02000210,
-/*02a5*/ 0x02000200,
-/*02a6*/ 0x02000200,
-/*02a7*/ 0x02000200,
-/*02a8*/ 0x02000200,
-/*02a9*/ 0x00000000,
-/*02aa*/ 0x00000000,
-/*02ab*/ 0x00000000,
-/*02ac*/ 0x00000000,
-/*02ad*/ 0x00000000,
-/*02ae*/ 0x00000000,
-/*02af*/ 0x00000000,
-/*02b0*/ 0x00000000,
-/*02b1*/ 0x00000000,
-/*02b2*/ 0x00000000,
-/*02b3*/ 0x00000000,
-/*02b4*/ 0x00000000,
-/*02b5*/ 0x00000400,
-/*02b6*/ 0x15141312,
-/*02b7*/ 0x11100f0e,
-/*02b8*/ 0x080b0c0d,
-/*02b9*/ 0x05040a09,
-/*02ba*/ 0x01000706,
-/*02bb*/ 0x00000302,
-/*02bc*/ 0x01030201,
-/*02bd*/ 0x00304c00,
-/*02be*/ 0x0001e2f8,
-/*02bf*/ 0x0000304c,
-/*02c0*/ 0x0001e2f8,
-/*02c1*/ 0x0000304c,
-/*02c2*/ 0x0001e2f8,
-/*02c3*/ 0x08000000,
-/*02c4*/ 0x00000100,
-/*02c5*/ 0x00000000,
-/*02c6*/ 0x00000000,
-/*02c7*/ 0x00000000,
-/*02c8*/ 0x00000000,
-/*02c9*/ 0x00000002
-};
diff --git a/drivers/staging/renesas/rcar/ddr/ddr_b/init_dram_tbl_m3n.h b/drivers/staging/renesas/rcar/ddr/ddr_b/init_dram_tbl_m3n.h
deleted file mode 100644
index 42c335196..000000000
--- a/drivers/staging/renesas/rcar/ddr/ddr_b/init_dram_tbl_m3n.h
+++ /dev/null
@@ -1,586 +0,0 @@
-/*
- * Copyright (c) 2015-2019, Renesas Electronics Corporation. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#define DDR_PHY_SLICE_REGSET_OFS_M3N  0x0800
-#define DDR_PHY_ADR_V_REGSET_OFS_M3N  0x0a00
-#define DDR_PHY_ADR_I_REGSET_OFS_M3N  0x0a80
-#define DDR_PHY_ADR_G_REGSET_OFS_M3N  0x0b80
-#define DDR_PI_REGSET_OFS_M3N         0x0200
-
-#define DDR_PHY_SLICE_REGSET_SIZE_M3N 0x80
-#define DDR_PHY_ADR_V_REGSET_SIZE_M3N 0x80
-#define DDR_PHY_ADR_I_REGSET_SIZE_M3N 0x80
-#define DDR_PHY_ADR_G_REGSET_SIZE_M3N 0x80
-#define DDR_PI_REGSET_SIZE_M3N        0x100
-
-#define DDR_PHY_SLICE_REGSET_NUM_M3N  101
-#define DDR_PHY_ADR_V_REGSET_NUM_M3N  37
-#define DDR_PHY_ADR_I_REGSET_NUM_M3N  37
-#define DDR_PHY_ADR_G_REGSET_NUM_M3N  87
-#define DDR_PI_REGSET_NUM_M3N         286
-
-static const uint32_t DDR_PHY_SLICE_REGSET_M3N[DDR_PHY_SLICE_REGSET_NUM_M3N] = {
-/*0800*/ 0x76543210,
-/*0801*/ 0x0004f008,
-/*0802*/ 0x00020200,
-/*0803*/ 0x00000000,
-/*0804*/ 0x00000000,
-/*0805*/ 0x00010000,
-/*0806*/ 0x036e6e0e,
-/*0807*/ 0x026e6e0e,
-/*0808*/ 0x00000103,
-/*0809*/ 0x00040001,
-/*080a*/ 0x00000103,
-/*080b*/ 0x00000001,
-/*080c*/ 0x00000000,
-/*080d*/ 0x00000000,
-/*080e*/ 0x00000100,
-/*080f*/ 0x001800c0,
-/*0810*/ 0x020100b0,
-/*0811*/ 0x00030020,
-/*0812*/ 0x00000000,
-/*0813*/ 0x00000000,
-/*0814*/ 0x0000aaaa,
-/*0815*/ 0x00005555,
-/*0816*/ 0x0000b5b5,
-/*0817*/ 0x00004a4a,
-/*0818*/ 0x00000000,
-/*0819*/ 0x09000000,
-/*081a*/ 0x04080000,
-/*081b*/ 0x08040000,
-/*081c*/ 0x00000004,
-/*081d*/ 0x00800710,
-/*081e*/ 0x000f000c,
-/*081f*/ 0x00000100,
-/*0820*/ 0x55aa55aa,
-/*0821*/ 0x33cc33cc,
-/*0822*/ 0x0ff00ff0,
-/*0823*/ 0x0f0ff0f0,
-/*0824*/ 0x00018e38,
-/*0825*/ 0x00000000,
-/*0826*/ 0x00000000,
-/*0827*/ 0x00000000,
-/*0828*/ 0x00000000,
-/*0829*/ 0x00000000,
-/*082a*/ 0x00000000,
-/*082b*/ 0x00000000,
-/*082c*/ 0x00000000,
-/*082d*/ 0x00000000,
-/*082e*/ 0x00000000,
-/*082f*/ 0x00000000,
-/*0830*/ 0x00000000,
-/*0831*/ 0x00000000,
-/*0832*/ 0x00000000,
-/*0833*/ 0x00000000,
-/*0834*/ 0x00000000,
-/*0835*/ 0x00000000,
-/*0836*/ 0x00000000,
-/*0837*/ 0x00000000,
-/*0838*/ 0x00000000,
-/*0839*/ 0x00000000,
-/*083a*/ 0x00000104,
-/*083b*/ 0x00082020,
-/*083c*/ 0x08200820,
-/*083d*/ 0x08200820,
-/*083e*/ 0x08200820,
-/*083f*/ 0x08200820,
-/*0840*/ 0x08200820,
-/*0841*/ 0x00000000,
-/*0842*/ 0x00000000,
-/*0843*/ 0x03000300,
-/*0844*/ 0x03000300,
-/*0845*/ 0x03000300,
-/*0846*/ 0x03000300,
-/*0847*/ 0x00000300,
-/*0848*/ 0x00000000,
-/*0849*/ 0x00000000,
-/*084a*/ 0x00000000,
-/*084b*/ 0x00000000,
-/*084c*/ 0x00000000,
-/*084d*/ 0x00a000a0,
-/*084e*/ 0x00a000a0,
-/*084f*/ 0x00a000a0,
-/*0850*/ 0x00a000a0,
-/*0851*/ 0x00a000a0,
-/*0852*/ 0x00a000a0,
-/*0853*/ 0x00a000a0,
-/*0854*/ 0x00a000a0,
-/*0855*/ 0x00a000a0,
-/*0856*/ 0x01040119,
-/*0857*/ 0x00000200,
-/*0858*/ 0x01000000,
-/*0859*/ 0x00000200,
-/*085a*/ 0x00000004,
-/*085b*/ 0x4041a141,
-/*085c*/ 0x0141c0a0,
-/*085d*/ 0x0000c0c0,
-/*085e*/ 0x0e0c000e,
-/*085f*/ 0x10001000,
-/*0860*/ 0x0c073e42,
-/*0861*/ 0x000f0c28,
-/*0862*/ 0x00e00140,
-/*0863*/ 0x000c0020,
-/*0864*/ 0x00000203
-};
-
-static const uint32_t DDR_PHY_ADR_V_REGSET_M3N[DDR_PHY_ADR_V_REGSET_NUM_M3N] = {
-/*0a00*/ 0x00000000,
-/*0a01*/ 0x00000000,
-/*0a02*/ 0x00000000,
-/*0a03*/ 0x00000000,
-/*0a04*/ 0x00000000,
-/*0a05*/ 0x00000000,
-/*0a06*/ 0x00000000,
-/*0a07*/ 0x01000000,
-/*0a08*/ 0x00020000,
-/*0a09*/ 0x00000000,
-/*0a0a*/ 0x00000000,
-/*0a0b*/ 0x00000000,
-/*0a0c*/ 0x00400000,
-/*0a0d*/ 0x00000080,
-/*0a0e*/ 0x00dcba98,
-/*0a0f*/ 0x03000000,
-/*0a10*/ 0x00000200,
-/*0a11*/ 0x00000000,
-/*0a12*/ 0x00000000,
-/*0a13*/ 0x00000000,
-/*0a14*/ 0x0000002a,
-/*0a15*/ 0x00000015,
-/*0a16*/ 0x00000015,
-/*0a17*/ 0x0000002a,
-/*0a18*/ 0x00000033,
-/*0a19*/ 0x0000000c,
-/*0a1a*/ 0x0000000c,
-/*0a1b*/ 0x00000033,
-/*0a1c*/ 0x0a418820,
-/*0a1d*/ 0x003f0000,
-/*0a1e*/ 0x0000013f,
-/*0a1f*/ 0x0002c06e,
-/*0a20*/ 0x02c002c0,
-/*0a21*/ 0x02c002c0,
-/*0a22*/ 0x000002c0,
-/*0a23*/ 0x42080010,
-/*0a24*/ 0x0000033e
-};
-
-static const uint32_t DDR_PHY_ADR_I_REGSET_M3N[DDR_PHY_ADR_I_REGSET_NUM_M3N] = {
-/*0a80*/ 0x00000000,
-/*0a81*/ 0x00000000,
-/*0a82*/ 0x00000000,
-/*0a83*/ 0x00000000,
-/*0a84*/ 0x00000000,
-/*0a85*/ 0x00000000,
-/*0a86*/ 0x00000000,
-/*0a87*/ 0x01000000,
-/*0a88*/ 0x00020000,
-/*0a89*/ 0x00000000,
-/*0a8a*/ 0x00000000,
-/*0a8b*/ 0x00000000,
-/*0a8c*/ 0x00400000,
-/*0a8d*/ 0x00000080,
-/*0a8e*/ 0x00000000,
-/*0a8f*/ 0x03000000,
-/*0a90*/ 0x00000200,
-/*0a91*/ 0x00000000,
-/*0a92*/ 0x00000000,
-/*0a93*/ 0x00000000,
-/*0a94*/ 0x0000002a,
-/*0a95*/ 0x00000015,
-/*0a96*/ 0x00000015,
-/*0a97*/ 0x0000002a,
-/*0a98*/ 0x00000033,
-/*0a99*/ 0x0000000c,
-/*0a9a*/ 0x0000000c,
-/*0a9b*/ 0x00000033,
-/*0a9c*/ 0x00000000,
-/*0a9d*/ 0x00000000,
-/*0a9e*/ 0x00000000,
-/*0a9f*/ 0x0002c06e,
-/*0aa0*/ 0x02c002c0,
-/*0aa1*/ 0x02c002c0,
-/*0aa2*/ 0x000002c0,
-/*0aa3*/ 0x42080010,
-/*0aa4*/ 0x0000033e
-};
-
-static const uint32_t DDR_PHY_ADR_G_REGSET_M3N[DDR_PHY_ADR_G_REGSET_NUM_M3N] = {
-/*0b80*/ 0x00000000,
-/*0b81*/ 0x00000100,
-/*0b82*/ 0x00000000,
-/*0b83*/ 0x00050000,
-/*0b84*/ 0x00000000,
-/*0b85*/ 0x0004000f,
-/*0b86*/ 0x00280080,
-/*0b87*/ 0x02005502,
-/*0b88*/ 0x00000000,
-/*0b89*/ 0x00000000,
-/*0b8a*/ 0x00000000,
-/*0b8b*/ 0x00000050,
-/*0b8c*/ 0x00000000,
-/*0b8d*/ 0x01010100,
-/*0b8e*/ 0x00010000,
-/*0b8f*/ 0x00000000,
-/*0b90*/ 0x00000101,
-/*0b91*/ 0x00000000,
-/*0b92*/ 0x00000000,
-/*0b93*/ 0x00000000,
-/*0b94*/ 0x00000000,
-/*0b95*/ 0x00005064,
-/*0b96*/ 0x01421142,
-/*0b97*/ 0x00000142,
-/*0b98*/ 0x00000000,
-/*0b99*/ 0x000f1600,
-/*0b9a*/ 0x0f160f16,
-/*0b9b*/ 0x0f160f16,
-/*0b9c*/ 0x00000003,
-/*0b9d*/ 0x0002c000,
-/*0b9e*/ 0x02c002c0,
-/*0b9f*/ 0x000002c0,
-/*0ba0*/ 0x08040201,
-/*0ba1*/ 0x03421342,
-/*0ba2*/ 0x00000342,
-/*0ba3*/ 0x00000000,
-/*0ba4*/ 0x00000000,
-/*0ba5*/ 0x05030000,
-/*0ba6*/ 0x00010700,
-/*0ba7*/ 0x00000014,
-/*0ba8*/ 0x00027f6e,
-/*0ba9*/ 0x047f027f,
-/*0baa*/ 0x00027f6e,
-/*0bab*/ 0x00047f6e,
-/*0bac*/ 0x0003554f,
-/*0bad*/ 0x0001554f,
-/*0bae*/ 0x0001554f,
-/*0baf*/ 0x0001554f,
-/*0bb0*/ 0x0001554f,
-/*0bb1*/ 0x00003fee,
-/*0bb2*/ 0x0001554f,
-/*0bb3*/ 0x00003fee,
-/*0bb4*/ 0x0001554f,
-/*0bb5*/ 0x00027f6e,
-/*0bb6*/ 0x0001554f,
-/*0bb7*/ 0x00004011,
-/*0bb8*/ 0x00004410,
-/*0bb9*/ 0x00000000,
-/*0bba*/ 0x00000000,
-/*0bbb*/ 0x00000000,
-/*0bbc*/ 0x00000265,
-/*0bbd*/ 0x00000000,
-/*0bbe*/ 0x00040401,
-/*0bbf*/ 0x00000000,
-/*0bc0*/ 0x03000000,
-/*0bc1*/ 0x00000020,
-/*0bc2*/ 0x00000000,
-/*0bc3*/ 0x00000000,
-/*0bc4*/ 0x04102006,
-/*0bc5*/ 0x00041020,
-/*0bc6*/ 0x01c98c98,
-/*0bc7*/ 0x00400000,
-/*0bc8*/ 0x00000000,
-/*0bc9*/ 0x0001ffff,
-/*0bca*/ 0x00000000,
-/*0bcb*/ 0x00000000,
-/*0bcc*/ 0x00000001,
-/*0bcd*/ 0x00000000,
-/*0bce*/ 0x00000000,
-/*0bcf*/ 0x00000000,
-/*0bd0*/ 0x76543210,
-/*0bd1*/ 0x06010198,
-/*0bd2*/ 0x00000000,
-/*0bd3*/ 0x00000000,
-/*0bd4*/ 0x04070000,
-/*0bd5*/ 0x00000001,
-/*0bd6*/ 0x00000f00
-};
-
-static const uint32_t DDR_PI_REGSET_M3N[DDR_PI_REGSET_NUM_M3N] = {
-/*0200*/ 0x00000b00,
-/*0201*/ 0x00000101,
-/*0202*/ 0x01640000,
-/*0203*/ 0x00000014,
-/*0204*/ 0x00000014,
-/*0205*/ 0x00000014,
-/*0206*/ 0x00000014,
-/*0207*/ 0x00000000,
-/*0208*/ 0x00000000,
-/*0209*/ 0x0000ffff,
-/*020a*/ 0x00000000,
-/*020b*/ 0x0000ffff,
-/*020c*/ 0x00000000,
-/*020d*/ 0x0000ffff,
-/*020e*/ 0x0000304c,
-/*020f*/ 0x00000200,
-/*0210*/ 0x00000200,
-/*0211*/ 0x00000200,
-/*0212*/ 0x00000200,
-/*0213*/ 0x0000304c,
-/*0214*/ 0x00000200,
-/*0215*/ 0x00000200,
-/*0216*/ 0x00000200,
-/*0217*/ 0x00000200,
-/*0218*/ 0x0000304c,
-/*0219*/ 0x00000200,
-/*021a*/ 0x00000200,
-/*021b*/ 0x00000200,
-/*021c*/ 0x00000200,
-/*021d*/ 0x00010000,
-/*021e*/ 0x00000003,
-/*021f*/ 0x01000001,
-/*0220*/ 0x00000000,
-/*0221*/ 0x00000000,
-/*0222*/ 0x00000000,
-/*0223*/ 0x00000000,
-/*0224*/ 0x00000000,
-/*0225*/ 0x00000000,
-/*0226*/ 0x00000000,
-/*0227*/ 0x00000000,
-/*0228*/ 0x00000000,
-/*0229*/ 0x00000000,
-/*022a*/ 0x00000000,
-/*022b*/ 0x00000000,
-/*022c*/ 0x00000000,
-/*022d*/ 0x00000000,
-/*022e*/ 0x00000000,
-/*022f*/ 0x00000000,
-/*0230*/ 0x0f000101,
-/*0231*/ 0x084d3129,
-/*0232*/ 0x0e0c0004,
-/*0233*/ 0x000e5000,
-/*0234*/ 0x01000250,
-/*0235*/ 0x00000003,
-/*0236*/ 0x00000046,
-/*0237*/ 0x000000cf,
-/*0238*/ 0x00001826,
-/*0239*/ 0x000000cf,
-/*023a*/ 0x00001826,
-/*023b*/ 0x00000000,
-/*023c*/ 0x00000000,
-/*023d*/ 0x00000000,
-/*023e*/ 0x00000000,
-/*023f*/ 0x00000000,
-/*0240*/ 0x00000000,
-/*0241*/ 0x00000000,
-/*0242*/ 0x00000000,
-/*0243*/ 0x00000000,
-/*0244*/ 0x00000000,
-/*0245*/ 0x01000000,
-/*0246*/ 0x00040404,
-/*0247*/ 0x01280a00,
-/*0248*/ 0x00000001,
-/*0249*/ 0x00000000,
-/*024a*/ 0x03000f00,
-/*024b*/ 0x00200020,
-/*024c*/ 0x00000020,
-/*024d*/ 0x00000000,
-/*024e*/ 0x00000000,
-/*024f*/ 0x00010002,
-/*0250*/ 0x01010001,
-/*0251*/ 0x02010100,
-/*0252*/ 0x08040402,
-/*0253*/ 0x00000008,
-/*0254*/ 0x00000000,
-/*0255*/ 0x04080803,
-/*0256*/ 0x00001515,
-/*0257*/ 0x00000000,
-/*0258*/ 0x000000aa,
-/*0259*/ 0x00000055,
-/*025a*/ 0x000000b5,
-/*025b*/ 0x0000004a,
-/*025c*/ 0x00000056,
-/*025d*/ 0x000000a9,
-/*025e*/ 0x000000a9,
-/*025f*/ 0x000000b5,
-/*0260*/ 0x00000000,
-/*0261*/ 0x00000000,
-/*0262*/ 0x0f000000,
-/*0263*/ 0x00001e0f,
-/*0264*/ 0x000007d0,
-/*0265*/ 0x01000300,
-/*0266*/ 0x00000100,
-/*0267*/ 0x00000000,
-/*0268*/ 0x00000000,
-/*0269*/ 0x01000000,
-/*026a*/ 0x00010101,
-/*026b*/ 0x000e0e0e,
-/*026c*/ 0x000c0c0c,
-/*026d*/ 0x01060601,
-/*026e*/ 0x04041717,
-/*026f*/ 0x00000004,
-/*0270*/ 0x00000300,
-/*0271*/ 0x17030000,
-/*0272*/ 0x00060018,
-/*0273*/ 0x00160028,
-/*0274*/ 0x00160028,
-/*0275*/ 0x00000000,
-/*0276*/ 0x00000000,
-/*0277*/ 0x00000000,
-/*0278*/ 0x0a000000,
-/*0279*/ 0x00010a14,
-/*027a*/ 0x00030005,
-/*027b*/ 0x0003018d,
-/*027c*/ 0x000a018d,
-/*027d*/ 0x00060100,
-/*027e*/ 0x01000006,
-/*027f*/ 0x018e018e,
-/*0280*/ 0x018e0100,
-/*0281*/ 0x1e1a018e,
-/*0282*/ 0x1e1a1e1a,
-/*0283*/ 0x01010204,
-/*0284*/ 0x06501001,
-/*0285*/ 0x090d0a07,
-/*0286*/ 0x090d0a07,
-/*0287*/ 0x0811180f,
-/*0288*/ 0x00ff1102,
-/*0289*/ 0x00ff1000,
-/*028a*/ 0x00ff1000,
-/*028b*/ 0x04041000,
-/*028c*/ 0x18020100,
-/*028d*/ 0x01010018,
-/*028e*/ 0x005f005f,
-/*028f*/ 0x005f005f,
-/*0290*/ 0x050f0000,
-/*0291*/ 0x051e051e,
-/*0292*/ 0x0c01021e,
-/*0293*/ 0x00000c0c,
-/*0294*/ 0x00003400,
-/*0295*/ 0x00000000,
-/*0296*/ 0x00000000,
-/*0297*/ 0x00000000,
-/*0298*/ 0x00000000,
-/*0299*/ 0x002e00d4,
-/*029a*/ 0x11360031,
-/*029b*/ 0x00d41611,
-/*029c*/ 0x0031002e,
-/*029d*/ 0x16111136,
-/*029e*/ 0x002e00d4,
-/*029f*/ 0x11360031,
-/*02a0*/ 0x00001611,
-/*02a1*/ 0x002e00d4,
-/*02a2*/ 0x11360031,
-/*02a3*/ 0x00d41611,
-/*02a4*/ 0x0031002e,
-/*02a5*/ 0x16111136,
-/*02a6*/ 0x002e00d4,
-/*02a7*/ 0x11360031,
-/*02a8*/ 0x00001611,
-/*02a9*/ 0x002e00d4,
-/*02aa*/ 0x11360031,
-/*02ab*/ 0x00d41611,
-/*02ac*/ 0x0031002e,
-/*02ad*/ 0x16111136,
-/*02ae*/ 0x002e00d4,
-/*02af*/ 0x11360031,
-/*02b0*/ 0x00001611,
-/*02b1*/ 0x002e00d4,
-/*02b2*/ 0x11360031,
-/*02b3*/ 0x00d41611,
-/*02b4*/ 0x0031002e,
-/*02b5*/ 0x16111136,
-/*02b6*/ 0x002e00d4,
-/*02b7*/ 0x11360031,
-/*02b8*/ 0x00001611,
-/*02b9*/ 0x00018d00,
-/*02ba*/ 0x018d018d,
-/*02bb*/ 0x1d220c08,
-/*02bc*/ 0x00001f12,
-/*02bd*/ 0x4301b344,
-/*02be*/ 0x17032006,
-/*02bf*/ 0x220c1010,
-/*02c0*/ 0x001f121d,
-/*02c1*/ 0x4301b344,
-/*02c2*/ 0x17062006,
-/*02c3*/ 0x220c1010,
-/*02c4*/ 0x001f121d,
-/*02c5*/ 0x4301b344,
-/*02c6*/ 0x17182006,
-/*02c7*/ 0x00021010,
-/*02c8*/ 0x00020002,
-/*02c9*/ 0x00020002,
-/*02ca*/ 0x00020002,
-/*02cb*/ 0x00020002,
-/*02cc*/ 0x00000002,
-/*02cd*/ 0x00000000,
-/*02ce*/ 0x00000000,
-/*02cf*/ 0x00000000,
-/*02d0*/ 0x00000000,
-/*02d1*/ 0x00000000,
-/*02d2*/ 0x00000000,
-/*02d3*/ 0x00000000,
-/*02d4*/ 0x00000000,
-/*02d5*/ 0x00000000,
-/*02d6*/ 0x00000000,
-/*02d7*/ 0x00000000,
-/*02d8*/ 0x00000000,
-/*02d9*/ 0x00000400,
-/*02da*/ 0x15141312,
-/*02db*/ 0x11100f0e,
-/*02dc*/ 0x080b0c0d,
-/*02dd*/ 0x05040a09,
-/*02de*/ 0x01000706,
-/*02df*/ 0x00000302,
-/*02e0*/ 0x01030201,
-/*02e1*/ 0x00304c08,
-/*02e2*/ 0x0001e2f8,
-/*02e3*/ 0x0000304c,
-/*02e4*/ 0x0001e2f8,
-/*02e5*/ 0x0000304c,
-/*02e6*/ 0x0001e2f8,
-/*02e7*/ 0x08000000,
-/*02e8*/ 0x00000100,
-/*02e9*/ 0x00000000,
-/*02ea*/ 0x00000000,
-/*02eb*/ 0x00000000,
-/*02ec*/ 0x00000000,
-/*02ed*/ 0x00010000,
-/*02ee*/ 0x00000000,
-/*02ef*/ 0x00000000,
-/*02f0*/ 0x00000000,
-/*02f1*/ 0x00000000,
-/*02f2*/ 0x00000000,
-/*02f3*/ 0x00000000,
-/*02f4*/ 0x00000000,
-/*02f5*/ 0x00000000,
-/*02f6*/ 0x00000000,
-/*02f7*/ 0x00000000,
-/*02f8*/ 0x00000000,
-/*02f9*/ 0x00000000,
-/*02fa*/ 0x00000000,
-/*02fb*/ 0x00000000,
-/*02fc*/ 0x00000000,
-/*02fd*/ 0x00000000,
-/*02fe*/ 0x00000000,
-/*02ff*/ 0x00000000,
-/*0300*/ 0x00000000,
-/*0301*/ 0x00000000,
-/*0302*/ 0x00000000,
-/*0303*/ 0x00000000,
-/*0304*/ 0x00000000,
-/*0305*/ 0x00000000,
-/*0306*/ 0x00000000,
-/*0307*/ 0x00000000,
-/*0308*/ 0x00000000,
-/*0309*/ 0x00000000,
-/*030a*/ 0x00000000,
-/*030b*/ 0x00000000,
-/*030c*/ 0x00000000,
-/*030d*/ 0x00000000,
-/*030e*/ 0x00000000,
-/*030f*/ 0x00050002,
-/*0310*/ 0x015c0057,
-/*0311*/ 0x01000100,
-/*0312*/ 0x01020001,
-/*0313*/ 0x00010300,
-/*0314*/ 0x05000104,
-/*0315*/ 0x01060001,
-/*0316*/ 0x00010700,
-/*0317*/ 0x00000000,
-/*0318*/ 0x00000000,
-/*0319*/ 0x00000001,
-/*031a*/ 0x00000000,
-/*031b*/ 0x00000000,
-/*031c*/ 0x00000000,
-/*031d*/ 0x20080101
-};
diff --git a/drivers/staging/renesas/rcar/ddr/dram_sub_func.h b/drivers/staging/renesas/rcar/ddr/dram_sub_func.h
deleted file mode 100644
index 7e88f4222..000000000
--- a/drivers/staging/renesas/rcar/ddr/dram_sub_func.h
+++ /dev/null
@@ -1,17 +0,0 @@
-/*
- * Copyright (c) 2015-2017, Renesas Electronics Corporation. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#ifndef DRAM_SUB_FUNC_H
-#define DRAM_SUB_FUNC_H
-
-#define DRAM_UPDATE_STATUS_ERR	(-1)
-#define DRAM_BOOT_STATUS_COLD	(0)
-#define DRAM_BOOT_STATUS_WARM	(1)
-
-int32_t rcar_dram_update_boot_status(uint32_t status);
-void rcar_dram_get_boot_status(uint32_t * status);
-
-#endif /* DRAM_SUB_FUNC_H */
diff --git a/drivers/ti/uart/aarch32/16550_console.S b/drivers/ti/uart/aarch32/16550_console.S
index 692188412..5cd9b30cd 100644
--- a/drivers/ti/uart/aarch32/16550_console.S
+++ b/drivers/ti/uart/aarch32/16550_console.S
@@ -89,16 +89,19 @@ endfunc console_16550_core_init
 	.globl console_16550_register
 
 	/* -------------------------------------------------------
-	 * int console_stm32_register(uintptr_t baseaddr,
+	 * int console_16550_register(uintptr_t baseaddr,
 	 *     uint32_t clock, uint32_t baud,
-	 *     struct console_stm32 *console);
-	 * Function to initialize and register a new STM32
+	 *     console_16550_t *console);
+	 * Function to initialize and register a new 16550
 	 * console. Storage passed in for the console struct
 	 * *must* be persistent (i.e. not from the stack).
+	 * If r1 (UART clock) is 0, initialisation will be
+         * skipped, relying on previous code to have done
+         * this already. r2 is ignored then as well.
 	 * In: r0 - UART register base address
 	 *     r1 - UART clock in Hz
-	 *     r2 - Baud rate
-	 *     r3 - pointer to empty console_stm32 struct
+	 *     r2 - Baud rate (ignored if r1 is 0)
+	 *     r3 - pointer to empty console_16550_t struct
 	 * Out: return 1 on success, 0 on error
 	 * Clobber list : r0, r1, r2
 	 * -------------------------------------------------------
@@ -110,10 +113,15 @@ func console_16550_register
 	beq	register_fail
 	str	r0, [r4, #CONSOLE_T_16550_BASE]
 
+	/* A clock rate of zero means to skip the initialisation. */
+	cmp	r1, #0
+	beq	register_16550
+
 	bl	console_16550_core_init
 	cmp	r0, #0
 	beq	register_fail
 
+register_16550:
 	mov	r0, r4
 	pop	{r4, lr}
 	finish_console_register 16550 putc=1, getc=1, flush=1
diff --git a/drivers/ti/uart/aarch64/16550_console.S b/drivers/ti/uart/aarch64/16550_console.S
index dab46e8c5..80c1b8646 100644
--- a/drivers/ti/uart/aarch64/16550_console.S
+++ b/drivers/ti/uart/aarch64/16550_console.S
@@ -92,9 +92,12 @@ endfunc console_16550_core_init
 	 * Function to initialize and register a new 16550
 	 * console. Storage passed in for the console struct
 	 * *must* be persistent (i.e. not from the stack).
+	 * If w1 (UART clock) is 0, initialisation will be
+	 * skipped, relying on previous code to have done
+	 * this already. w2 is ignored then as well.
 	 * In: x0 - UART register base address
 	 *     w1 - UART clock in Hz
-	 *     w2 - Baud rate
+	 *     w2 - Baud rate (ignored if w1 is 0)
 	 *     x3 - pointer to empty console_16550_t struct
 	 * Out: return 1 on success, 0 on error
 	 * Clobber list : x0, x1, x2, x6, x7, x14
@@ -106,9 +109,13 @@ func console_16550_register
 	cbz	x6, register_fail
 	str	x0, [x6, #CONSOLE_T_16550_BASE]
 
+	/* A clock rate of zero means to skip the initialisation. */
+	cbz	w1, register_16550
+
 	bl	console_16550_core_init
 	cbz	x0, register_fail
 
+register_16550:
 	mov	x0, x6
 	mov	x30, x7
 	finish_console_register 16550 putc=1, getc=1, flush=1