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| author | Alistair Delva <adelva@google.com> | 2021-02-16 21:01:22 +0000 |
|---|---|---|
| committer | Automerger Merge Worker <android-build-automerger-merge-worker@system.gserviceaccount.com> | 2021-02-16 21:01:22 +0000 |
| commit | efb2826bb8160e2d8e0fcec85133a7468484f9fd (patch) | |
| tree | 37a21c69306801ee7cdda5167a30896c8740155b /drivers/renesas/rzg/qos/qos_common.h | |
| parent | b00a71fc312c9781fa6f404dccfb55b062b2ccac (diff) | |
| parent | faa476c0caaa598afa5a6109d17102db5fe35ec6 (diff) | |
| download | platform_external_arm-trusted-firmware-master.tar.gz platform_external_arm-trusted-firmware-master.tar.bz2 platform_external_arm-trusted-firmware-master.zip | |
Merge branch 'aosp/upstream-master' into HEAD am: faa476c0caHEADandroid-s-beta-5android-s-beta-4android-s-beta-3android-s-beta-2android-s-beta-1mastermain-cg-testing-releaseandroid-s-beta-5android-s-beta-4
Original change: https://android-review.googlesource.com/c/platform/external/arm-trusted-firmware/+/1589611
MUST ONLY BE SUBMITTED BY AUTOMERGER
Change-Id: I3a25534ceed4f8e188510641080d8b8ed49b8f62
Diffstat (limited to 'drivers/renesas/rzg/qos/qos_common.h')
| -rw-r--r-- | drivers/renesas/rzg/qos/qos_common.h | 67 |
1 files changed, 67 insertions, 0 deletions
diff --git a/drivers/renesas/rzg/qos/qos_common.h b/drivers/renesas/rzg/qos/qos_common.h new file mode 100644 index 000000000..6e0cf0e85 --- /dev/null +++ b/drivers/renesas/rzg/qos/qos_common.h @@ -0,0 +1,67 @@ +/* + * Copyright (c) 2021, Renesas Electronics Corporation. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef QOS_COMMON_H +#define QOS_COMMON_H + +#define RCAR_REF_DEFAULT 0U + +/* define used for get_refperiod. */ +/* REFPERIOD_CYCLE need smaller than QOSWT_WTSET0_CYCLEs */ +#if (RCAR_REF_INT == RCAR_REF_DEFAULT) /* REF default */ +#define REFPERIOD_CYCLE /* unit:ns */ \ + ((126U * BASE_SUB_SLOT_NUM * 1000U) / 400U) +#else /* REF option */ +#define REFPERIOD_CYCLE /* unit:ns */ \ + ((252U * BASE_SUB_SLOT_NUM * 1000U) / 400U) +#endif + +#if (RCAR_LSI == RCAR_AUTO) || (RCAR_LSI == RZ_G2M) +/* define used for G2M */ +#if (RCAR_REF_INT == RCAR_REF_DEFAULT) /* REF 1.95usec */ +#define SUB_SLOT_CYCLE_G2M_11 0x7EU /* 126 */ +#define SUB_SLOT_CYCLE_G2M_30 0x7EU /* 126 */ +#else /* REF 3.9usec */ +#define SUB_SLOT_CYCLE_G2M_11 0xFCU /* 252 */ +#define SUB_SLOT_CYCLE_G2M_30 0xFCU /* 252 */ +#endif /* (RCAR_REF_INT == RCAR_REF_DEFAULT) */ + +#define SL_INIT_SSLOTCLK_G2M_11 (SUB_SLOT_CYCLE_G2M_11 - 1U) +#define SL_INIT_SSLOTCLK_G2M_30 (SUB_SLOT_CYCLE_G2M_30 - 1U) +#define QOSWT_WTSET0_CYCLE_G2M_11 /* unit:ns */ \ + ((SUB_SLOT_CYCLE_G2M_11 * BASE_SUB_SLOT_NUM * 1000U) / OPERATING_FREQ) +#define QOSWT_WTSET0_CYCLE_G2M_30 /* unit:ns */ \ + ((SUB_SLOT_CYCLE_G2M_30 * BASE_SUB_SLOT_NUM * 1000U) / OPERATING_FREQ) +#endif + +#define OPERATING_FREQ 400U /* MHz */ +#define BASE_SUB_SLOT_NUM 0x6U +#define SUB_SLOT_CYCLE 0x7EU /* 126 */ + +#define QOSWT_WTSET0_CYCLE /* unit:ns */ \ + ((SUB_SLOT_CYCLE * BASE_SUB_SLOT_NUM * 1000U) / OPERATING_FREQ) + +#define SL_INIT_REFFSSLOT (0x3U << 24U) +#define SL_INIT_SLOTSSLOT ((BASE_SUB_SLOT_NUM - 1U) << 16U) +#define SL_INIT_SSLOTCLK (SUB_SLOT_CYCLE - 1U) + +typedef struct { + uintptr_t addr; + uint64_t value; +} mstat_slot_t; + +struct rcar_gen3_dbsc_qos_settings { + uint32_t reg; + uint32_t val; +}; + +extern uint32_t qos_init_ddr_ch; +extern uint8_t qos_init_ddr_phyvalid; + +void rzg_qos_dbsc_setting(const struct rcar_gen3_dbsc_qos_settings *qos, + unsigned int qos_size, bool dbsc_wren); + +#endif /* QOS_COMMON_H */ |