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| author | Stefan Chulski <stefanc@marvell.com> | 2019-06-25 15:41:47 +0300 |
|---|---|---|
| committer | Marcin Wojtas <mw@semihalf.com> | 2020-08-11 12:21:30 +0200 |
| commit | 5e4c97d035a92302f8bce9cec29676306af560a6 (patch) | |
| tree | e742c142ad83cb31b398c38ed08e62f3b32e7bf3 /drivers/marvell/ccu.c | |
| parent | 8f09da46e263cdb97f01edce449aa5b769cca2f5 (diff) | |
| download | platform_external_arm-trusted-firmware-5e4c97d035a92302f8bce9cec29676306af560a6.tar.gz platform_external_arm-trusted-firmware-5e4c97d035a92302f8bce9cec29676306af560a6.tar.bz2 platform_external_arm-trusted-firmware-5e4c97d035a92302f8bce9cec29676306af560a6.zip | |
plat: marvell: ap807: implement workaround for errata-id 3033912
ERRATA ID: RES-3033912 - Internal Address Space Init state causes
a hang upon accesses to [0xf070_0000, 0xf07f_ffff]
Workaround: Boot Firmware (ATF) should configure CCU_RGF_WIN(4) to
split [0x6e_0000, 0xff_ffff] to values [0x6e_0000, 0x6f_ffff] and
[0x80_0000, 0xff_ffff] that cause accesses to the segment of
[0xf070_0000, 0xf07f_ffff] to act as RAZWI. Reuse common
work-around code for both AP806 and AP807.
Change-Id: Ia91a4802d02917d1682faa0c81571093d1687d97
Signed-off-by: Stefan Chulski <stefanc@marvell.com>
Diffstat (limited to 'drivers/marvell/ccu.c')
| -rw-r--r-- | drivers/marvell/ccu.c | 17 |
1 files changed, 17 insertions, 0 deletions
diff --git a/drivers/marvell/ccu.c b/drivers/marvell/ccu.c index c73516eae..ecf5091b4 100644 --- a/drivers/marvell/ccu.c +++ b/drivers/marvell/ccu.c @@ -30,6 +30,9 @@ ((tgt) == DRAM_1_TID) || \ ((tgt) == RAR_TID)) ? 1 : 0) +#define CCU_RGF(win) (MVEBU_CCU_BASE(MVEBU_AP0) + \ + 0x90 + 4 * (win)) + /* For storage of CR, SCR, ALR, AHR abd GCR */ static uint32_t ccu_regs_save[MVEBU_CCU_MAX_WINS * 4 + 1]; @@ -366,3 +369,17 @@ int init_ccu(int ap_index) return 0; } + +void errata_wa_init(void) +{ + /* + * EERATA ID: RES-3033912 - Internal Address Space Init state causes + * a hang upon accesses to [0xf070_0000, 0xf07f_ffff] + * Workaround: Boot Firmware (ATF) should configure CCU_RGF_WIN(4) to + * split [0x6e_0000, 0xff_ffff] to values [0x6e_0000, 0x6f_ffff] and + * [0x80_0000, 0xff_ffff] that cause accesses to the + * segment of [0xf070_0000, 0xf07f_ffff] to act as RAZWI. + */ + mmio_write_32(CCU_RGF(4), 0x37f9b809); + mmio_write_32(CCU_RGF(5), 0x7ffa0009); +} |