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author | Alistair Delva <adelva@google.com> | 2021-02-16 21:01:22 +0000 |
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committer | Automerger Merge Worker <android-build-automerger-merge-worker@system.gserviceaccount.com> | 2021-02-16 21:01:22 +0000 |
commit | efb2826bb8160e2d8e0fcec85133a7468484f9fd (patch) | |
tree | 37a21c69306801ee7cdda5167a30896c8740155b /drivers/arm/tzc/tzc_dmc620.c | |
parent | b00a71fc312c9781fa6f404dccfb55b062b2ccac (diff) | |
parent | faa476c0caaa598afa5a6109d17102db5fe35ec6 (diff) | |
download | platform_external_arm-trusted-firmware-master.tar.gz platform_external_arm-trusted-firmware-master.tar.bz2 platform_external_arm-trusted-firmware-master.zip |
Merge branch 'aosp/upstream-master' into HEAD am: faa476c0caHEADandroid-s-beta-5android-s-beta-4android-s-beta-3android-s-beta-2android-s-beta-1mastermain-cg-testing-releaseandroid-s-beta-5android-s-beta-4
Original change: https://android-review.googlesource.com/c/platform/external/arm-trusted-firmware/+/1589611
MUST ONLY BE SUBMITTED BY AUTOMERGER
Change-Id: I3a25534ceed4f8e188510641080d8b8ed49b8f62
Diffstat (limited to 'drivers/arm/tzc/tzc_dmc620.c')
-rw-r--r-- | drivers/arm/tzc/tzc_dmc620.c | 35 |
1 files changed, 18 insertions, 17 deletions
diff --git a/drivers/arm/tzc/tzc_dmc620.c b/drivers/arm/tzc/tzc_dmc620.c index 64ec5abee..7e307ee50 100644 --- a/drivers/arm/tzc/tzc_dmc620.c +++ b/drivers/arm/tzc/tzc_dmc620.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2018-2020, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -17,7 +17,7 @@ /* Helper macro for getting dmc_base addr of a dmc_inst */ #define DMC_BASE(plat_data, dmc_inst) \ - ((uintptr_t)(plat_data->dmc_base[dmc_inst])) + ((uintptr_t)((plat_data)->dmc_base[(dmc_inst)])) /* Pointer to the tzc_dmc620_config_data structure populated by the platform */ static const tzc_dmc620_config_data_t *g_plat_config_data; @@ -31,8 +31,7 @@ static const tzc_dmc620_config_data_t *g_plat_config_data; static void tzc_dmc620_validate_plat_driver_data( const tzc_dmc620_driver_data_t *plat_driver_data) { - uint8_t dmc_inst, dmc_count; - unsigned int dmc_id; + unsigned int dmc_inst, dmc_count, dmc_id; uintptr_t base; assert(plat_driver_data != NULL); @@ -59,7 +58,7 @@ static void tzc_dmc620_configure_region(int region_no, { uint32_t min_31_00, min_47_32; uint32_t max_31_00, max_47_32; - uint8_t dmc_inst, dmc_count; + unsigned int dmc_inst, dmc_count; uintptr_t base; const tzc_dmc620_driver_data_t *plat_driver_data; @@ -67,19 +66,19 @@ static void tzc_dmc620_configure_region(int region_no, assert(plat_driver_data != NULL); /* Do range checks on regions. */ - assert((region_no >= 0U) && (region_no <= DMC620_ACC_ADDR_COUNT)); + assert((region_no >= 0) && (region_no <= DMC620_ACC_ADDR_COUNT)); /* region_base and (region_top + 1) must be 4KB aligned */ assert(((region_base | (region_top + 1U)) & (4096U - 1U)) == 0U); dmc_count = plat_driver_data->dmc_count; for (dmc_inst = 0U; dmc_inst < dmc_count; dmc_inst++) { - min_31_00 = (region_base & MASK_31_16) | sec_attr; - min_47_32 = (region_base & MASK_47_32) - >> DMC620_ACC_ADDR_WIDTH; - max_31_00 = (region_top & MASK_31_16); - max_47_32 = (region_top & MASK_47_32) - >> DMC620_ACC_ADDR_WIDTH; + min_31_00 = (uint32_t)((region_base & MASK_31_16) | sec_attr); + min_47_32 = (uint32_t)((region_base & MASK_47_32) + >> DMC620_ACC_ADDR_WIDTH); + max_31_00 = (uint32_t)(region_top & MASK_31_16); + max_47_32 = (uint32_t)((region_top & MASK_47_32) + >> DMC620_ACC_ADDR_WIDTH); /* Extract the base address of the DMC-620 instance */ base = DMC_BASE(plat_driver_data, dmc_inst); @@ -100,7 +99,7 @@ static void tzc_dmc620_configure_region(int region_no, */ static void tzc_dmc620_set_action(void) { - uint8_t dmc_inst, dmc_count; + unsigned int dmc_inst, dmc_count; uintptr_t base; const tzc_dmc620_driver_data_t *plat_driver_data; @@ -123,7 +122,7 @@ static void tzc_dmc620_set_action(void) */ static void tzc_dmc620_verify_complete(void) { - uint8_t dmc_inst, dmc_count; + unsigned int dmc_inst, dmc_count; uintptr_t base; const tzc_dmc620_driver_data_t *plat_driver_data; @@ -133,8 +132,9 @@ static void tzc_dmc620_verify_complete(void) /* Extract the base address of the DMC-620 instance */ base = DMC_BASE(plat_driver_data, dmc_inst); while ((mmio_read_32(base + DMC620_MEMC_STATUS) & - DMC620_MEMC_CMD_MASK) != DMC620_MEMC_CMD_GO) + DMC620_MEMC_CMD_MASK) != DMC620_MEMC_CMD_GO) { continue; + } } } @@ -145,7 +145,7 @@ static void tzc_dmc620_verify_complete(void) */ void arm_tzc_dmc620_setup(const tzc_dmc620_config_data_t *plat_config_data) { - int i; + uint8_t i; /* Check if valid pointer is passed */ assert(plat_config_data != NULL); @@ -164,11 +164,12 @@ void arm_tzc_dmc620_setup(const tzc_dmc620_config_data_t *plat_config_data) g_plat_config_data = plat_config_data; INFO("Configuring DMC-620 TZC settings\n"); - for (i = 0U; i < g_plat_config_data->acc_addr_count; i++) + for (i = 0U; i < g_plat_config_data->acc_addr_count; i++) { tzc_dmc620_configure_region(i, g_plat_config_data->plat_acc_addr_data[i].region_base, g_plat_config_data->plat_acc_addr_data[i].region_top, g_plat_config_data->plat_acc_addr_data[i].sec_attr); + } tzc_dmc620_set_action(); tzc_dmc620_verify_complete(); |