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| author | Soby Mathew <soby.mathew@arm.com> | 2018-06-01 16:53:38 +0100 |
|---|---|---|
| committer | Soby Mathew <soby.mathew@arm.com> | 2018-06-07 12:26:19 +0100 |
| commit | c099cd3942fb163a7894536c1ebaf4ffbf677a82 (patch) | |
| tree | fbb3196da85758b6481031ef9ea8fef7c853865c /docs | |
| parent | edcd266e6a9276ac0b2927301c8deec3798a6b1c (diff) | |
| download | platform_external_arm-trusted-firmware-c099cd3942fb163a7894536c1ebaf4ffbf677a82.tar.gz platform_external_arm-trusted-firmware-c099cd3942fb163a7894536c1ebaf4ffbf677a82.tar.bz2 platform_external_arm-trusted-firmware-c099cd3942fb163a7894536c1ebaf4ffbf677a82.zip | |
ARM platforms: Move BL31 below BL2 to enable BL2 overlay
The patch changes the layout of BL images in memory to enable
more efficient use of available space. Previously BL31 was loaded
with the expectation that BL2 memory would be reclaimed by BL32
loaded in SRAM. But with increasing memory requirements in the
firmware, we can no longer fit BL32 in SRAM anymore which means the
BL2 memory is not reclaimed by any runtime image. Positioning BL2
below BL1-RW and above BL31 means that the BL31 NOBITS can be
overlaid on BL2 and BL1-RW.
This patch also propogates the same memory layout to BL32 for AArch32
mode. The reset addresses for the following configurations are also
changed :
* When RESET_TO_SP_MIN=1 for BL32 in AArch32 mode
* When BL2_AT_EL3=1 for BL2
The restriction on BL31 to be only in DRAM when SPM is enabled
is now removed with this change. The update to the firmware design
guide for the BL memory layout is done in the following patch.
Change-Id: Icca438e257abe3e4f5a8215f945b9c3f9fbf29c9
Signed-off-by: Soby Mathew <soby.mathew@arm.com>
Diffstat (limited to 'docs')
| -rw-r--r-- | docs/user-guide.rst | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/docs/user-guide.rst b/docs/user-guide.rst index 5f3823dbe..f6d0c7641 100644 --- a/docs/user-guide.rst +++ b/docs/user-guide.rst @@ -1928,7 +1928,7 @@ with 8 CPUs using the AArch32 build of TF-A. -C cluster1.cpu1.RVBAR=0x04001000 \ -C cluster1.cpu2.RVBAR=0x04001000 \ -C cluster1.cpu3.RVBAR=0x04001000 \ - --data cluster0.cpu0="<path-to>/<bl32-binary>"@0x04001000 \ + --data cluster0.cpu0="<path-to>/<bl32-binary>"@0x04002000 \ --data cluster0.cpu0="<path-to>/<bl33-binary>"@0x88000000 \ --data cluster0.cpu0="<path-to>/<fdt>"@0x82000000 \ --data cluster0.cpu0="<path-to>/<kernel-binary>"@0x80080000 \ @@ -1959,7 +1959,7 @@ boot Linux with 8 CPUs using the AArch64 build of TF-A. -C cluster1.cpu2.RVBARADDR=0x04020000 \ -C cluster1.cpu3.RVBARADDR=0x04020000 \ --data cluster0.cpu0="<path-to>/<bl31-binary>"@0x04020000 \ - --data cluster0.cpu0="<path-to>/<bl32-binary>"@0x04001000 \ + --data cluster0.cpu0="<path-to>/<bl32-binary>"@0x04002000 \ --data cluster0.cpu0="<path-to>/<bl33-binary>"@0x88000000 \ --data cluster0.cpu0="<path-to>/<fdt>"@0x82000000 \ --data cluster0.cpu0="<path-to>/<kernel-binary>"@0x80080000 \ @@ -1982,7 +1982,7 @@ boot Linux with 4 CPUs using the AArch32 build of TF-A. -C cluster0.cpu1.RVBARADDR=0x04001000 \ -C cluster0.cpu2.RVBARADDR=0x04001000 \ -C cluster0.cpu3.RVBARADDR=0x04001000 \ - --data cluster0.cpu0="<path-to>/<bl32-binary>"@0x04001000 \ + --data cluster0.cpu0="<path-to>/<bl32-binary>"@0x04002000 \ --data cluster0.cpu0="<path-to>/<bl33-binary>"@0x88000000 \ --data cluster0.cpu0="<path-to>/<fdt>"@0x82000000 \ --data cluster0.cpu0="<path-to>/<kernel-binary>"@0x80080000 \ |