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| author | Dimitris Papastamos <dimitris.papastamos@arm.com> | 2018-04-05 14:38:26 +0100 |
|---|---|---|
| committer | Dimitris Papastamos <dimitris.papastamos@arm.com> | 2018-05-23 12:45:48 +0100 |
| commit | b8a25bbb0bab4e4afdbfb04bee98f0bf28141c4b (patch) | |
| tree | 06c3f43c7cf979d11c86f7270d407d5edfd1d661 /docs | |
| parent | 2c3a10780df3317c004de74fbe85df53daab94e5 (diff) | |
| download | platform_external_arm-trusted-firmware-b8a25bbb0bab4e4afdbfb04bee98f0bf28141c4b.tar.gz platform_external_arm-trusted-firmware-b8a25bbb0bab4e4afdbfb04bee98f0bf28141c4b.tar.bz2 platform_external_arm-trusted-firmware-b8a25bbb0bab4e4afdbfb04bee98f0bf28141c4b.zip | |
Implement static workaround for CVE-2018-3639
For affected CPUs, this approach enables the mitigation during EL3
initialization, following every PE reset. No mechanism is provided to
disable the mitigation at runtime.
This approach permanently mitigates the entire software stack and no
additional mitigation code is required in other software components.
TF-A implements this approach for the following affected CPUs:
* Cortex-A57 and Cortex-A72, by setting bit 55 (Disable load pass store) of
`CPUACTLR_EL1` (`S3_1_C15_C2_0`).
* Cortex-A73, by setting bit 3 of `S3_0_C15_C0_0` (not documented in the
Technical Reference Manual (TRM)).
* Cortex-A75, by setting bit 35 (reserved in TRM) of `CPUACTLR_EL1`
(`S3_0_C15_C1_0`).
Additionally, a new SMC interface is implemented to allow software
executing in lower ELs to discover whether the system is mitigated
against CVE-2018-3639.
Refer to "Firmware interfaces for mitigating cache speculation
vulnerabilities System Software on Arm Systems"[0] for more
information.
[0] https://developer.arm.com/cache-speculation-vulnerability-firmware-specification
Change-Id: I084aa7c3bc7c26bf2df2248301270f77bed22ceb
Signed-off-by: Dimitris Papastamos <dimitris.papastamos@arm.com>
Diffstat (limited to 'docs')
| -rw-r--r-- | docs/cpu-specific-build-macros.rst | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/docs/cpu-specific-build-macros.rst b/docs/cpu-specific-build-macros.rst index 65f6adb8d..a89305b7d 100644 --- a/docs/cpu-specific-build-macros.rst +++ b/docs/cpu-specific-build-macros.rst @@ -24,6 +24,12 @@ vulnerability workarounds should be applied at runtime. with the recommendation in the spec regarding workaround discovery. Defaults to 1. +- ``WORKAROUND_CVE_2018_3639``: Enables the security workaround for + `CVE-2018-3639`_. Defaults to 1. The TF-A project recommends to keep + the default value of 1 even on platforms that are unaffected by + CVE-2018-3639, in order to comply with the recommendation in the spec + regarding workaround discovery. + CPU Errata Workarounds ---------------------- |